JPH04104542A - Digital demodulator - Google Patents

Abstract

PURPOSE:To save supply of a clock for an A/D converter or a digital filter from a BTR(bit timing reproducing circuit) by converting a Q analog signal to a digital signal by a clock of two-fold or higher bit rate from an oscillator independent of the BTR and changing the tap coefficient of a reception digital filter by the phase difference between received I and Q data. CONSTITUTION:The clock of two-fold or higher bit rate is generated by an oscillator 5 and is given to A/D converters 1 and 2 and digital filters 3 and 4. A BTR 50 consisting of a phase detector 6, a filter 7, a control circuit 8, and a tap coefficient memory 9 obtains the phase difference between output data of digital filters 3 and 4 by the phase detector 6 and the filter 7 and takes out a tap coefficient, which optimizes the response phase in accordance with this phase difference, from the tap coefficient memory 9 based on the phase difference. Thus, the oscillator having a low oscillation frequency can be used, and it is unnecessary to supply the clock for the A/D converter and the digital filter from the BTR.

Description

[Detailed Description of the Invention] [Summary] Regarding a digital demodulator that demodulates digital communication using phase modulation and amplitude modulation in wireless communication, or a modulation signal that combines these, an oscillator with a low oscillation frequency can be used. In addition, the aim is to realize a digital demodulator that does not require the BTR to supply clocks for the A/D converter and digital filter. 1. A/D conversion that converts the Q analog signal input into a digital signal. The tap coefficients of the receiving digital filter are received using a clock that is more than twice the bit rate from an oscillator independent of the BTR.

The bit timing is reproduced by adjusting the digital filter output to a required timing value by changing the phase difference between Q data.

[Industrial application field]

The present invention relates to a digital demodulator, and more particularly to a digital demodulator that demodulates digital communications using a modulated signal that uses phase modulation, amplitude modulation, or a combination of these in wireless communications.

In recent years, the development of digital communication systems has progressed, and along with this, it is desired that the demodulator on the receiving side also be constructed of a fully digital system.

[Prior Art] Fig. 21 shows a conventional digital demodulator (the automatic frequency control loop is omitted), and in the figure, 1.2 is an A/D demodulator.
3. A converter that converts the analog reception signals of the I channel and Q channel into digital data; 3.
4 are digital transversal filters (D
TP), which performs noise removal and waveform shaping (equalization) of the received data waveform of channel and Q channel, 30
is a quasi-synchronous carrier recovery (CR) circuit, and filter 3.
4 regenerates the carrier wave of the received wave from the output data of 1 and outputs the Q channel demodulation data, and 40 is the BTR (
bit timing regeneration circuit), uses the output of the digital filter 3.4 to regenerate a clock having the same rate as the symbol rate f, and supplies it to the carrier wave regeneration circuit 30,
A/D converter 1.2 and filter 3
, 4.

In addition, as shown in FIG. 22, the BTR 40 detects the phase difference between the output data from the digital filter 3.4 with a phase detector 42, and removes noise in this phase difference with a filter 43. Based on the phase difference data
(bit rate) is divided to reproduce a clock with a frequency of 2f. As a result, the frequency and phase of the output of the frequency divider 44 are changed to correctly match the timing of the data identification point, thereby regenerating the bit timing. In addition, 4
5 is a frequency divider for generating a clock of frequency f.

[Problem to be solved by the invention]

However, in order to control the clock phase with an accuracy of a few degrees, it is necessary to use an oscillator 4) that generates a high-frequency clock of 50 times or more the bit rate due to the frequency divider 44, and demodulation of the high bit rate is required. Because it is not compatible with the
This was a bottleneck due to the speed limit of full digital demodulators.

Furthermore, when a clock with N times the bit rate is used, the minimum phase that can be controlled is 360/N, and N cannot be increased at high bit rates, resulting in large phase jitter.

For this reason, when the bit rate increases, even in a digital demodulator, only the VCO 44 of the BTR becomes an analog circuit, making it impossible to realize miniaturization (LSI) with a full digital demodulator.

■Conventional BTRs regenerate bit timing by changing the clock frequency and phase of the A/D converter and digital filter, so preamble data is stored in memory in the burst demodulator and used for CR pull-in and BTR. It was not possible to use it multiple times for different retraction movements.

■Furthermore, since conventional BTR regenerated the bit timing by changing the frequency and phase of the clock of the A/D converter and digital filter, the preamble (repetition of "1" and "0") section for BTR was used in the burst demodulator. In order to improve the BTR pull-in characteristics, it was difficult to improve the BTR pull-in characteristics by changing the digital filter characteristics to a narrow-band band-pass filter. It would be better to make it narrower, but since the BTR loop includes an A/D converter and a digital filter, there are conflicting factors such as a large time constant and slow pull-in. there were.

Therefore, an object of the present invention is to realize a digital demodulator that can use an oscillator with a low oscillation frequency and that does not require clocks for the A/D converter and digital filter to be supplied from the BTR.

[Means and actions to solve the problem]

Hereinafter, various means of the digital demodulator according to the present invention for solving the above problems will be explained.

(1) In principle, if the digital filter used in the digital demodulator has two or more tap coefficients relative to the number of tap coefficients required for accuracy, the output with the same accuracy can be output at ±360/bit interval = 360 degrees. H (H is sample rate/
It can be calculated by changing the tap coefficient within the range of (bit rate).

Utilizing this fact, instead of the conventional method of changing the sample clock to obtain bit timing, the required timing value (for example, data discrimination point) can be calculated by changing the tap coefficient of the digital filter. It turns out that it is possible to output.

Therefore, in the present invention, as shown in principle in FIG.
An A/D converter 1.2 that converts each channel reception signal and Q channel reception signal into digital data, and a digital filter 3 that further shapes the waveform of each digital data.
．． an oscillator 5 which provides a clock of twice the bit rate (R) or more to the digital filters 4 and 4; a phase detector 6 which detects a phase difference from the outputs of both digital filters 3.4; and a phase detector 6 which removes noise within the phase difference. a loop filter 7 for extracting a predetermined frequency component; a control circuit 8 for generating a jump command signal only when the output of the loop filter exceeds a sampling interval; and a control circuit 8 for generating a skip command signal in response to the output of the loop filter. 3.4, a memory 9 for providing a tap coefficient that optimizes the phase of the response, and in response to the jump instruction, the oscillator 5, the phase detector 6, and the loop filter 7.
and a circuit 10 that prohibits clock output to the control circuit 8.
and a frequency dividing circuit 11 that divides the output clock of the inhibiting circuit 10 by two and supplies the frequency to the phase detecting section 6, loop filter 7, and control circuit 8.

That is, the oscillator 5 generates a clock at twice the bit rate or more and supplies it to the A/D converter 1.2 and the digital filters 3 and 4.

In the BTR 50, which is composed of a phase detector 6, a filter 7, a control circuit 8, and a tap coefficient memory 9, a phase difference is determined from the output data of the digital filter 3.4 by the phase detector 6 and the filter. Based on this, a tap coefficient that optimizes the phase of the response is extracted from the tap coefficient memory 9 in accordance with the phase difference.

To explain this using the impulse response waveform shown in FIG. 2, if the output phase difference of the filter 7 is P as shown in the figure within the bit interval T, the data value read from the tap coefficient memory 9 This is a value that makes P "0".

The digital filter 3.4 to which the tap coefficients are given in this way performs operations such as waveform shaping based on the tap coefficients, so even if the output clock of the oscillator 5 cannot latch the center of the receiving eye pattern, the above tap Since the phase is corrected by coefficient correction and sent to the BTR 50, the phase of the clock reproduced by the BTR 50 is accurate.

However, in the case where point P exceeds the sampling interval T1 in FIG. 2 (when point P is not between TI and -T1), the control circuit 8 detects this and sets a circuit for inhibiting the skip command. 10, the clock from the oscillator 5 is made toothless and the clock frequency is tuned to the bit rate.

(2) In addition to the configuration shown in FIG. 1, the present invention further includes a delay device that delays the output of each A'/D converter 1°2 by a predetermined number of clocks, as shown in principle in FIG. 3. 12.13 and the output of each A/D converter 1.2 or each delay device 12.13
A selector 14.15 selects the output of BTR by a selection signal and sends it to each digital filter 3, 4;
A circuit 16 may be further provided for detecting a hang-up state of the initial phase at the time of BTR pull-in from the outputs of both digital filters 3.4 and kicking off the initial phase of the control circuit 8 when the start of the preamble is indicated.

That is, by using the configuration shown in FIG. 1, the A/D converter 1.2 and the digital filter 3.4 are operated by the clock of the oscillator 5 independent of the BTR 50, so that the burst preambles are the same. Even for CR or B
It is possible to draw in for TR.

Therefore, in the present invention, at the time of preamble, each A/D converter 1. The output of A/D converter 1.2 is delayed by a predetermined number of clocks 0 minutes, and the output of A/D converter 1.2 and the output of delay device 12-13 are set to BTR using selectors 14-15.
By selecting using the selection signal indicating the time of retraction, the fourth
As shown in the figure, the initial phase kickoff circuit 16 detects the hang-up state of the initial phase during BTR pull-in from the output of the digital filter 3.4 during n clocks of the preamble for BTR pull-in.

As shown in Figure 14, this hang-up state indicates that the data clock timing occurs at the point where the eye pattern is narrowest, and when the BTR is pulled in in such a hang-up state, a short preamble is generated. Since the retraction may not be completed within this period, when the circuit 16 detects a hang-up state of the initial phase during the first n clocks as shown in FIG. 4, the initial phase of the control circuit 8 in the BTR 50 is kicked off.

In this way, after 99079 minutes have elapsed, normal BTR pull-in can be performed based on the output data of the delay device 12.13.

Therefore, since the preamble data can be used repeatedly, the transmitted preamble data itself can be short.

(3) In the present invention, as shown in principle in FIG. 5 for the CR pull-in during the preamble, in addition to the configuration shown in FIG. Delay devices 17.18 for delaying by a predetermined number of minutes, and selector 14.14 for selecting the output of each A/D converter 1, 2 or the output of delay device 17.18 using a selection signal and sending it to each digital filter 3.4. 1
5 and a carrier wave regeneration circuit 19 that reproduces the frequency difference from the outputs of both digital filters 3.4 and demodulates the outputs of both digital filters 3.4 at the end of frequency pull-in in the CR preamble indicated by the selection signal. A frequency difference reproducing circuit 20 may be further provided to provide the initial value for phase pull-in.

That is, in the present invention, a delay device 17.18 is provided to delay the output of the A/D converter 1.2 by a predetermined number of clocks m, and a selector 14.15 selects the output of the A/D converter 1.2. or the output of the delay device 17 or 18, and select the output of the digital filter 3.
．． Give to 4.

In this case, as shown in FIG. 6, the selection signal is first regenerated by the frequency difference reproducing circuit 20 for the frequency difference corresponding to m vias in the CR pull-in portion of the preamble, and the frequency is pulled in.
After the bit has elapsed, normal CR retraction can be performed.

Therefore, since the preamble data can be used repeatedly, the transmitted preamble data itself can be short.

(4) Furthermore, in the present invention, in addition to the configuration shown in FIG. 5, as shown in principle in FIG. Delay device 12.13
and the output of each A/D converter 1.2 or each delay device 12, 1
CR any output of 3, 17 or 18 by selection signal
A selector 21.22 separates and selects the preamble period for frequency reproduction, initial phase kickoff, and phase reproduction and sends the selected preamble period to each digital filter 3.4, and the selection signal selects the output of both digital filters 3, 4. After the frequency difference regeneration circuit 20 performs frequency regeneration during CR pull-in, the initial phase hang-up state is detected and the carrier wave regeneration circuit 19
A circuit 16 may further be provided for kicking off the initial phase of .

That is, in the present invention, in addition to the frequency pull-in operation shown in FIG.
Carrier wave regeneration circuit 1 performs the initial phase kickoff operation shown in the figure.
As shown in Figure 8, the selection signal divides the CR preamble period into m bits for frequency reproduction, n bits for initial phase kickoff, and phase reproduction, and selects each digital signal. The preamble data is sent to the filter 3.4, and the same preamble data can be used for frequency pull-in, initial phase kickoff, and phase pull-in, and the preamble data to be transmitted can be shortened.

(5) Furthermore, in the present invention, in addition to the configuration shown in FIG. 1, as shown in principle in FIG. L2.13 and
The output of each A/D converter 1, 2 or the output of the delay device 12, 13 is selected by the selection signal, and the digital filter 3
．． 4, the preamble data has a repeating pattern of "1" and uO", and the selection signal can divide the preamble data into one for BTR and one for subsequent CR. can.

That is, as normal preamble data, for example, an all "0" CR preamble is sent first, and then B
A TR preamble is sent, but in the present invention, the preamble data uses a repeating pattern of 1'' and 0, so the selectors 14 and 15 are controlled by a selection signal as shown in FIG. (6) Furthermore, in the present invention, the preamble data can be used first for BTR pull-in, and then the preamble data can be used for CR pull-in, and in this case as well, the preamble data can be shortened. In addition to the composition of
As shown in principle in the figure, another memory 22 containing a frequency band slope coefficient narrower than the frequency band according to the tap coefficient of the memory 9 and connected to the output of each filter, and a BTR
A selector 23 may be further provided, which selects tap coefficients from the memory 22 for the narrow band and applies the same to the digital filter 3.4 when receiving a selection signal indicating reception of a preamble for the narrow band.

That is, in the present invention, the clock of A/D converter 1.2 is B
Since it is independent from TR50, the preamble for BTR (
(repetition of “0” and “1”), the S/N is good < LBT
Since it is better to narrow the bands of the digital filters 3 and 4 in order to speed up R pull-in, the selector 23 digitally selects the tap coefficients stored in the narrow band tap coefficient memory 22 in response to the selection signal indicating the BTR preamble. It is applied to filter 3°4.

[Example] FIG. 12(a) shows the results of FIG.
9 and 11) shows one embodiment of the control circuit 8 in the BTR 50 used in the digital demodulator according to the present invention shown in FIGS.

Note that an AND gate can be used as the inhibition circuit 10 in FIG. 1, and the other components can be the same as those of the conventional example.

In FIG. 12(a), the control circuit 8 according to this embodiment
is the adder (integrator) 81 and the output X of this adder 81
and a reference value 90/K or -90/, respectively, and a comparator 82.83 that processes the output of the adder 81 based on the outputs and the output Z sent to the adder 81 and the AND gate 10
It consists of an arithmetic unit 84 that sends data to the computer. Furthermore, the comparator 82
K in the reference value of ゜83 indicates the phase accuracy of the BTR (determined by the capacity of the tap coefficient memory 9) when the focus interval is 360 degrees, and is 360 R/K f (R is the pit rate, f is the oscillator). in this case f = 4 R)
The reference value of 90/ corresponds to the position where the focus distance T is divided into four as shown by the dotted line in FIG.

In the control circuit 9 having such a configuration, if the point P in FIG. 2 is between "0" and T1 or -T1, for example,
The output of the calculation unit 84 is given to the memory 9 as is, and the tap coefficient is forcibly corrected to the "0" position (the position where the eye pattern is most open) by the phase difference X, and waveform shaping is performed. will be exposed. At this time, the output Z is as shown in Fig. 12 (b
) as shown in the time chart, AND gate 1
The clock of oscillator 5, which is the other input of 0, is inhibited by half. That is, normally the output of the oscillator 5 (frequency NR
=4R) is divided by N/2 to extract the necessary 2R.

On the other hand, if the P point exceeds T1 or -T1, the comparator 82 or 83 uses X>90/K or X<-90.
The output becomes 1'' at /, and the arithmetic unit 84 that receives this generates an output of Y=X-90/K or Y=X+90/, and output Z as shown in FIG. 12(b). change.

Thereby, the AND gate 1o controls the clock of the oscillator 5. At this time, the output Y of the arithmetic unit 84 is sent to the memory 9, and the tap coefficients of the digital filter 3.4 are read out after being corrected to the corresponding tap coefficients.

FIG. 13 is an embodiment showing a combination of the initial phase kickoff circuit 16 and the control circuit 8 used in the present invention shown in FIG. Input (output of digital filter 3.4)
A latch circuit 16 that captures the clock using the output clock of the frequency divider 11.
1 and an integrator 1 that integrates the output of this latch circuit 161.
62, a comparison section 163 that compares the output of the integrator 162 with a reference value, and a switch SWI that selects the initial phase kickoff value 180/K based on the output of the comparison section 163. The output is added to the output Y of the arithmetic unit 84 in an adder 85 added to the control circuit 8.

In such a kink-off circuit I6, the frequency divider 11
The digital filter 3 uses the clock from the
4 and integrates the output of the launch circuit 161 during a preamble period of n clocks from the time when the start of BTR indicated by the selection signal shown in FIG. 3 is indicated.

As a result, if this integrated value does not exceed the reference value and remains a small value, as shown in FIG. 180/K is selected and added to output Y in adder 85. Incidentally, this kink-off value of 180/ is a value corresponding to exactly half the phase of the horizontal width of the eye pattern, as shown in FIG.

As a result, the clock phase at the correct timing is given to the control circuit 8 from the phase in the hang-up state in FIG. 14 as the initial phase.

Therefore, the control circuit 8 can shorten the preamble period for subsequent BTR pull-in.

FIG. 15 shows the switching timing of the switch SWI, and shows the CR part and the BTR part during the preamble period.
During the period of n clocks, the switch is selected between terminals B and C, but when the hang amplifier is in the hang amplifier state at the end of n clocks, the switch SWI is switched to the terminal A and C side, and the kickoff is temporarily switched. and then
It will soon be switched between terminals 113-C.

FIG. 16 shows an embodiment showing a combination of the frequency difference regeneration circuit 20 and the carrier regeneration circuit 19 used in the present invention shown in FIG. A phase rotation unit 191 that rotates the phase of the output to generate demodulated data, a phase detector 192 that detects a phase difference from the output of the phase rotation unit 191, and a loop filter 19 that removes noise from the output of the phase detector 192.
3 and a digital VCO 194 that controls the phase rotation of the phase rotation unit 191 according to the phase difference between them. The frequency difference reproducing circuit 20 is configured to provide an output from a frequency difference reproducing circuit 20, which is comprised of a frequency difference detecting section 201 that reproduces a frequency difference from the output, and an average value calculating section 202 that calculates the average value of this frequency difference.

Therefore, in the frequency difference reproducing circuit 20, the first
As shown in FIG. 7, during the frequency pull-in period during the CR preamble period, the average value calculation unit 202 averages the frequency difference and loads the result into the filter 193.

As a result, the filter 193 subsequently performs OCR acquisition while being reset to the average frequency difference, so that acquisition can be performed quickly.

FIG. 18 is an embodiment showing a combination of the initial phase kickoff circuit 16, the frequency difference regeneration circuit 20, and the carrier wave regeneration circuit 19 of the present invention shown in FIG. The relationship with the circuit 19 is specifically shown.

In this embodiment, the initial phase kickoff circuit 16 includes integrators 16a and 16b that integrate the output of the digital filter 3.4 for a certain period of time, a ROM 16c that generates a judgment output from the outputs of these integrators, and a ROM 16c that is activated by a selection signal.
The VCO 194 of the carrier wave regeneration circuit 19 includes an adder 194a that adds the output of the filter 193 and the output of the switch SW2, and a selection signal that selects the output of the adder 194a. It is composed of an integrator 194b that performs integration by the integrator 194b, and a ROM 194c that outputs phase rotation data based on the integration result of the integrator 194b. As for the frequency difference reproducing circuit 20, the averaged frequency difference is applied to the filter 193 as shown in FIG.

First, in the selection signal (2 bits) in this case, the CR period in the preamble data period is set to 3 as shown in FIG.
During the first CR period, the frequency difference regeneration circuit 20
Frequency difference reproduction is performed as explained in FIG. 6, and in the next CR period, integrators 16a and 16b in the initial phase kickoff circuit 16 integrate the output of the digital filter 3.4.

The outputs of the integrators 16a and 16b are, for example, 8 binods, and when the difference between them is smaller than the comparison reference value of the ROM 16c, as shown in FIG. If it is larger than the reference value, it is determined that the initial phase state is on the ■ shown in Fig. 20 or on the Q channel axis, and corresponds to 45° shown in Fig. 20. ROMI 6 c outputs the phase value.

The timing to kick off the initial phase at this time is the first
As shown in FIG. 9, this is when the third CR period starts, and the selection signal indicates this, so that
The switch SW2 connected between terminals A and C is switched between terminals A and C as shown in FIG.
The output is given to the integrator 194b of C0194.

As a result, the integrator 194b operates as shown in FIG.
A phase difference of 45° is given between the channel and the Q channel for kick-off, and subsequent CR (phase) pull-in can be performed quickly, making it possible to shorten the preamble period. Note that the switch SW2 is immediately switched between terminals B and C after the kink-off operation.

〔Effect of the invention〕

As explained above, according to the digital demodulator according to the present invention, the A/D conversion for converting the [,Q analog signal input into a digital signal] is performed using a clock with a clock rate of more than twice the pin rate from an oscillator independent of the BTR. The tap coefficients of the reception digital filter are determined by the reception 1. By changing the phase difference between the Q data, the digital filter output is adjusted to the required timing value and the bit timing is regenerated, so the oscillator clock rate is twice the pin rate. Therefore, digital BTR can support up to high bit rates.

In addition, by removing the A/D converter from the BTR loop, it becomes possible to store received data in a delay device and use it for various independent processes, reducing preamble data and improving the transmission efficiency of burst communication. You can improve.

Furthermore, by keeping the length of the preamble data the same as before, the line quality of burst communication can be improved. Also, unlike before, the minimum phase that can be controlled can be determined by the type of tap coefficient regardless of the BTR's focus rate, and the phase accuracy of the tap coefficient memory can be finely adjusted (by setting
Accordingly, highly accurate phase control can be performed.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle configuration of the digital demodulator (part 1) according to the present invention, Fig. 2 is an impulse response waveform diagram for explaining the principle of the tap coefficient memory used in the present invention, □ Fig. 3 teeth,
FIG. 4 is a block diagram of the principle configuration of the digital demodulator (Part 2) according to the present invention; FIG. 4 is a time chart diagram for explaining the present invention in detail in FIG. 3; FIG. 6 is a time chart diagram for explaining in detail the present invention of FIG. 5. FIG. 7 is a block diagram of the principle configuration of the digital demodulator (part 4) according to the present invention. 8 is a time chart diagram for explaining in detail the present invention in FIG. 7; FIG. 9 is a block diagram of the principle configuration of the digital demodulator (part 5) according to the present invention; FIG. 10 is a time chart diagram for explaining in detail the present invention in FIG. 9, and FIG. 11 is a digital demodulator (part 6) according to the present invention.
FIG. 12 is a diagram showing an example of the configuration and operation of a control circuit used in the present invention; FIG. 13 is a diagram showing an example of a combination of an initial phase kickoff circuit and a control circuit used in the present invention. A block diagram showing an example; FIG. 14 is an eye pattern waveform diagram for explaining the hang-up state; FIG. 15 is an operation time chart of the switch used in the embodiment of FIG. 13; A block diagram showing an embodiment of a combination of a frequency regeneration circuit and a carrier wave regeneration circuit used in the invention, FIG. 17 is a time chart diagram for explaining the operation of the embodiment of FIG. 16, and FIG. FIG. 19 is a block diagram showing an embodiment of a combination of a frequency difference regeneration circuit, an initial phase kink-off circuit, and a carrier wave regeneration circuit used in the invention; FIG. 19 is an operation time chart of a switch used in the embodiment of FIG. 18; 21 is a block diagram showing a conventional example, and FIG. 22 is a bit timing recovery circuit used in the conventional example. FIG. 2 is a block diagram showing the configuration. In the figure, 1.2... A/D converter, 3.4... Digital filter, 5... Oscillator, 6... Phase detector, 7... Loop filter, 8... Control Circuit, 9... Tap coefficient memory, 10... Inhibition circuit, 11... Frequency divider, 12.13.17.18... Delay device, 14.15.2
1.22...Selector, 16...Initial phase kickoff circuit, 19...Carrier recovery circuit, 20...Frequency difference recovery circuit, 23...Narrowband tap coefficient memory, 23...Selection vessel. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (6)

[Claims] (1) A/D converter (1) that converts the I channel received signal and Q channel received signal into digital data, respectively.
(2), digital filters (3) and (4) that further shape the waveform of each digital data, an oscillator (5) that provides a clock of more than twice the bit rate, and the output of both digital filters (3) and (4). A phase detector (6) that detects a phase difference; a loop filter (7) that removes noise from the phase difference and extracts a predetermined frequency component; Control that generates a jump command signal only when the
), a memory (9) for providing tap coefficients for optimizing the phase of the response to the digital filters (3) and (4) according to the output of the loop filter (7); From the oscillator (5) to the phase detector (6), loop filter (7) and control circuit (8)
a circuit (10) that inhibits the output of a clock to the circuit (10), and divides the output clock of the inhibit circuit (10) into two and supplies the divided clock to the phase detector (6), the loop filter (7), and the control circuit (8). A digital demodulator comprising: a frequency dividing circuit (11); (2) Delay devices (12) and (13) that delay the output of each A/D converter (1) and (2) by a predetermined number of clocks;
/D converter (1) (2) output or each delay device (12) (
a selector (14) (15) that selects the output of (13) using a selection signal and sends the selected output to each digital filter (3) (4);
When the selection signal indicates the start of the BTR preamble, the hang-up state of the initial phase at the time of BTR pull-in is detected from the outputs of both digital filters (3) and (4), and the initial phase of the control circuit (8) is kicked off. 2. A digital demodulator according to claim 1, further comprising a circuit (16) for. (3) Delay devices (17) and (18) that delay the output of each A/D converter (1) and (2) by a predetermined number of clocks;
/D converter (1) (2) output or the delay device (17) (
a selector (14) (15) that selects the output of (18) using a selection signal and sends the selected output to each digital filter (3) (4);
Carrier wave regeneration that reproduces the frequency difference from the outputs of both digital filters (3) and (4), and demodulates the outputs of both digital filters (3) and (4) at the end of frequency pull-in in the CR preamble indicated by the selection signal. Circuit (1
9) A frequency difference regeneration circuit (
20). The digital demodulator according to claim 1, further comprising: 20). (4) Another delay device (12) (13) that delays the output of each A/D converter (1) (2) by another predetermined number of clocks.
and the output of each A/D converter (1) (2) or each delay device (
12) (13) (17) (18) The output of each digital filter (3) ( 4) Selector (21) sent to
(22), and both digital filters (
3) From the output of (4), detect the hang-up state of the initial phase after the frequency difference regeneration circuit (20) performs frequency regeneration during CR pull-in, and kick off the initial phase of the carrier wave regeneration circuit (19). 4. A digital demodulator according to claim 3, further comprising a circuit (16) for. (5) Delay devices (12) and (13) that delay the output of each A/D converter (1) and (2) by a predetermined number of clocks;
/D converter (1) (2) output or the delay device (12) (
13) is further provided with selectors (14) and (15) which select the output of the filter according to a selection signal and send the selected output to the digital filters (3) and (4). 2. The digital demodulator according to claim 1, wherein the selection signal divides the preamble data into BTR data and subsequent CR data. (6) Each filter (7) has a tap coefficient in a frequency band narrower than the frequency band by the tap coefficient in the memory (9).
Another memory (22) connected to the output of the digital filter selects tap coefficients from the narrowband memory (22) when receiving a selection signal indicating that a BTR preamble has been received. The digital demodulator according to claim 1, further comprising: (3) a selector (23) for applying to (4).