JPH0399466A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent a leakage current from flowing into an element due to an interfacial instability by a method wherein the element is formed on an island-like semiconductor layer isolated through the intermediary of an insulating layer, and a second gate electrode is formed at an interface between the base of the channel region of the element and the insulating layer. CONSTITUTION:A MESFET composed of N<+>-type source and drain regions 8 and 10, an N-type channel region sandwiched between the regions 8 and 10, a source electrode 14, a drain electrode 16, and a first gate electrode 18, the three electrodes being formed on these regions respectively, is formed on an island-like semi-insulating GaAs layer 6. As an adjacent element is formed on another island-like semi-insulating GaAs layer through the intermediary of an insulating layer 4, the adjacent elements are prevented from electrically affecting each other and consequently a side gate effect is restrained. As a second gate electrode 20 is formed at the interface between the base of the channel region 12 and the insulating layer 4, a leakage current, which is induced due to an interfacial instability which occurs when the base of the channel region is in direct contact with the insulating layer 4, can be prevented from flowing into the channel region 12.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a semiconductor device and a method for manufacturing the same, and in particular to an integrated circuit using a compound semiconductor such as GaAs, by stably suppressing side gate effects without reducing the effective area of the device. The purpose of the present invention is to provide a semiconductor device that improves the integration density of the semiconductor device and improves the signal driving ability of the element. a source region and a drain region, a channel region sandwiched between the source region and the drain region, a first gate electrode formed on the channel region, and a boundary between the bottom surface of the channel region and the insulating layer. and a second gate electrode, and is configured to apply a voltage to the second gate electrode so as to control the channel thickness of the channel region.

[Industrial Field of Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to a semiconductor device and a method for manufacturing the same.
The present invention relates to an integrated circuit using a compound semiconductor such as As and a method for manufacturing the same.

[Prior Art] In a compound semiconductor crystal such as a GaAs crystal, the electron traveling speed is about five times faster than that in Si.
C1rcuit). In order to realize logic functions with high integration density, such as number or gate scale, on a single chip IC, transistors, which are the elements that drive signals, are miniaturized to increase their signal driving ability and reduce the distance between elements. Therefore, it is necessary to establish a technology for forming a large number of elements within a small area.

However, if multiple GaAs FETs (Field E
When transistors (transistors) are formed close to each other on the same substrate, as the distance between the elements is shortened, a phenomenon is observed in which the voltage applied to one element changes the characteristics of the other element. This phenomenon is called the side gate effect.

This side gate effect will be explained using FIG. 7. In FIG. 7(a), on a semi-insulating GaAs substrate 52,
n++ source region 54a, n+ type drain region 56a
These n++ source and drain regions 54 a + 56
It consists of an n-type channel region 58a sandwiched between M 60 a and M 60 a, and source electrodes M 60 a, M 60 a,
Drain electric f! A first FET 66a is formed having a gate electrode 62a and a gate electrode 64a. Adjacent to this first FET 66a with an inter-element distance of 10 μm, an n++ source region 54b having the same structure as the first FET 66a, an n+ type drain region 56b, an n type channel region 58b, a source electrode [, 60b, Drain electricity [!
62b and a gate electrode 64b.
b is formed.

Now, the source electrode 160a and the gate electrode 64a of the first FET 66a are connected, and the source electrode 60a and the drain 7
Source-drain voltage VD! between the 4-pole 62a! is applied and one drain current B is measured. At this time, the first
When a side gate voltage vlIo is applied between the source electrode 60a of the FET 66a and the source electrode 60b of the adjacent second FET 66b, for example, as shown in FIG.
As shown in , when the side gate voltage V1° exceeds 5V, the train current I increases. S begins to decrease. That is, in this example, the side gate effect threshold voltage v8 = 5V, and when the voltage exceeds this value, the characteristics of the first FET 66b begin to be influenced by the second FET 66b.

Therefore, in order to prevent such side gate effects, it is necessary to increase the spacing between elements, which is a major obstacle to increasing the integration density of GaAs ICs.

By the way, the cause of the side gate effect is that the voltage applied to the adjacent second FET 66b is semi-insulating and semi-insulating Ga.
The problem is that it reaches the bottom surface of the channel region 58a of the first FET 66a via the As substrate 52, changing the effective thickness of the channel.

As a means to prevent this side gate effect, as shown in FIG.
It has been considered to form an element isolation region 68 made of, for example, a highly concentrated n + impurity layer between a and 66b, and maintain it at an appropriate potential via a wiring layer 70, usually connecting it to the ground power supply GND. .

However, in this method, the effective area within the IC chip is reduced by the element isolation region 68 and the wiring layer 70 leading to the ground power supply GND.

[Problems to be Solved by the Invention] As described above, in conventional GaAs ICs, the distance between elements cannot be increased due to the side gate effect in which the effective channel thickness of the FET is affected by the voltage applied to adjacent elements. There was a problem in that it was not possible to achieve high density by shortening the length.

Further, when an element isolation region is provided between elements to prevent this side gate effect, the effective area is reduced by that amount, which again poses a problem of hindering high integration.

Therefore, it has been a challenge to establish a technique for preventing the side gate effect that requires a small area, to improve the integration density, and to improve the signal driving ability. .

Therefore, the present invention provides a semiconductor device and its manufacturing method that stably suppresses the side gate effect without reducing the effective area of an IC chip, improves the integration density of elements, and improves the signal driving ability of the elements. The purpose is to

[Means for Solving the Problems] The above-mentioned problems include: a semiconductor layer formed in an island shape in an insulating layer on a semiconductor substrate; a source region and a drain region formed in the semiconductor layer; a channel region sandwiched between regions, a first gate electrode formed on the channel region, and a second gate electrode formed at a boundary between the bottom surface of the channel region and the insulating layer; said second to control the channel thickness of
This is achieved by a semiconductor device characterized in that a voltage is applied to the gate electrode.

Moreover, the above-mentioned problem is solved in the above-mentioned device by the second gate tfl! are formed on the bottom and side surfaces of the channel region and connected to the first gate electrode.

Furthermore, the above problem is solved by a first step of etching the surface of a first semiconductor substrate into a mesa shape, and a step of etching a second gate on the channel layer after forming a channel region on the mesa-shaped first semiconductor substrate surface. forming an electrode, forming a source region and a drain region sandwiching the channel layer therebetween, and further forming an insulating layer on the entire surface; bonding a second semiconductor substrate on the insulating layer; polishing and removing the bottom surface of the first semiconductor substrate until the insulating layer is exposed so that the mesa-shaped first semiconductor substrate becomes an island-shaped semiconductor layer in the insulating layer; This is achieved by a method of manufacturing a semiconductor device, which comprises the steps of: forming a first gate electrode;

Further, the above problem is solved in the above method by selectively etching the semiconductor layer until it reaches the second gate electrode when forming the first gate electrode on the channel region, thereby etching the side surfaces of the channel region. This is achieved by a method of manufacturing a semiconductor device, which is characterized in that the first gate electrode is exposed, and the first gate electrode is formed on and on the side surface of the channel region, and connected to the second gate electrode.

[Function] According to the present invention, by forming elements in island-shaped semiconductor layers separated through an insulating layer, mutual electrical influence can be eliminated without providing a special element isolation region between the elements. do not interact with each other, and the Suidgate effect is therefore suppressed.

In addition, since the second gate electrode is formed at the boundary between the bottom surface of the channel region and the insulating layer of the device, leakage current due to instability of the interface when the bottom surface of the channel region and the insulating layer are in direct contact with each other is reduced. In addition to preventing the inflow, it is possible to suppress variations in the threshold voltage of the element due to variations in the density of interface states.

Furthermore, by applying a voltage to the second gate electrode,
The operating speed of the device can be increased by controlling the channel thickness of the channel region.

[Example] The present invention will be specifically described below based on an illustrative example.

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

For example, in an insulating layer 4 formed on a silicon St substrate 2, an island-shaped semi-insulating GaAs layer 6 is formed. This semi-insulating GaAs layer 6 has an n” type source region 8.
and n+ type drain region 10 are formed, and these n++
An n-type channel region 12 is formed sandwiched between source and drain regions 8.10. Further, on the n++ source region 8 and the n+ type drain region 10, a source voltage f! made of, for example, A.sub.U Ge/A.sub.u is applied, respectively. 14 and a drain electrode 16 are ohmically connected to each other.

Further, above the n-type channel region 12, a first gate electrode 18 made of, for example, WSlx (tungsten silicide) is formed to make a rectifying junction with GaAs. A second gate electrode 20 made of the same material as the first gate electrode 18 is formed at the boundary between the bottom surface of the n-type channel head region 12 and the insulating layer 4.

In this way, the second gate t is formed on the bottom surface of the n-type channel region 12.
MES (Metl-8
eIIiconductor) FET is formed in island-shaped semi-insulating GaAs layers 6 separated by insulating layers 4.

Next, the operation will be explained.

In the semiconductor device shown in FIG. 1, an n++ source, a drain region 8, 10, an n-type channel region 12 sandwiched therebetween, and a source formed on top of these are connected to a pole 14, a drain electrode 16, and a first MESFET consisting of gate electrode 18 is one island-shaped semi-insulating GaAs
Since the adjacent elements are formed on other island-shaped semi-insulating GaAs layers via the insulating layer 4, they do not have any electrical influence on each other, so there is no side gate effect. is suppressed.

In particular, since the second gate electrode 20 is provided on the bottom surface of the n-type channel region 12, the effect of blocking electrical influence from adjacent elements on the n-type channel region 12 is large. It also has a large deterrent effect.

In addition, since this second gate electrode 20 is formed at the boundary between the bottom surface of the channel region 12 and the insulating layer 4, it is possible to cause instability at the interface that occurs when the bottom surface of the channel region 20 and the insulating layer 4 are in direct contact with each other. It can prevent leaks from flowing in. Furthermore, variations in the threshold voltage of the MESFET due to variations in interface state density can be suppressed. Therefore, the side gate effect can be stably suppressed.

Now, if we plot the relationship between the side gate voltages V, O and the drain current l011 with an inter-element distance 1 = 10 μm between adjacent elements, as shown in Fig. 2, the side gate voltage VsO = Drain current Ios begins to decrease above 20V. That is, the side gate effect threshold voltage V −T = 20 V, and the conventional V mr =
Compared to 5 V, the side gate effect suppression effect is greatly improved.

Further, by applying a predetermined voltage to the second gate electrode 20, the channel thickness aCO of the n-type channel region 12 can be controlled.

For example, as shown in FIG. 3(a), the source electrode 14
and a source-drain voltage V between the drain electrode 16 and the drain electrode 16 . ,
and apply the first gate voltage! 18 has a positive gate voltage vQ
Apply 1. When a negative gate voltage (G2) is applied to the second gate electrode 20, the channel thickness acM of the channel region 12 is reduced by this negative bias. Therefore, the value of the normalized transfer conductance ga of the MESFET, i.e., g, = 2K (VGI - Vth), i.e., K = μCWo / 2 a cHL or increases. Here, Vtk is the gate threshold voltage, μ is the electron mobility, and ε
is GaAs mobility, Wo is gate width, L, 3. is the length of the first gate electrode 18.

For example, if the channel thickness acM is effectively thinned by a factor of two, the K value increases by a factor of two. Therefore, the operating speed is increased and the signal driving ability is improved.

Furthermore, as shown in FIG. 3(b), even if the first gate electrode 18 and the second gate electrode 20 are connected and a positive gate voltage V is applied, there is an effect of increasing the K value. . In this case, the carriers in the channel are controlled by the electric field spreading from above and below by the gate voltage v(l) applied to the first and second gate electrodes 18 and 20. At this time, the channel is divided into an upper half and a lower half. When you think about it, for each person,
, K2 is K,=μεWa/2 (a (H/2) L
o.

= μt Wc+ / a cnL at 2 = μt
Wa/2 (acn/2) Lo2=μεW6
/aCHL, l12. Here it is. 2 is the length of the second gate electrode 20.

Therefore, the effective value is K = K r + K 2 ” (μI; Wa / ac, 1l-at) (1
+L, a+/l-02), and the channel thickness acI
It increases as l becomes effectively thinner. Therefore, the operating speed of the element is increased and the signal driving ability is improved.

In this way, in this embodiment, MESFE'I' is 1
MBSFE
A second gate electrode 20 is provided on the bottom surface of the n-type channel region 12 of T.
, it is possible to stably and sufficiently suppress side gate effects from adjacent elements.

Furthermore, by applying a predetermined voltage to the second gate electrode 20 to effectively reduce the channel thickness ace of the n-type channel region 12 and increase the value of the normalized transfer conductance of the MESFBT, the operating speed can be increased. Speed up MESF
The signal driving ability of ET can be improved.

Next, a semiconductor device according to another embodiment of the present invention will be described using FIG. 4.

While FIG. 1 is a cross-sectional view of the n1 type source region 8, the n+ type drain region 10, and the n type channel region 12 sandwiched between these n'' type source and drain regions 8 and 10, FIG. 1 is a cross-sectional view of the n-type channel region 12 perpendicular to the cross section thereof.

In FIG. 4, a second gate electrode 20 made of WSix
is formed not only at the boundary between the bottom surface of the n-type channel region 12 and the insulating layer 4, but also on the side surface of the n-type channel region 12, and is formed on the first gate electrode 22 formed above the n-type channel region 12. is connected to. That is,
The n-type channel region 12, except for the portion sandwiched between the n++ source and drain regions 8.10, has its upper, bottom and side surfaces all covered by first and second gate electrodes 22.20.

Therefore, according to this embodiment, the side gate effect from adjacent elements can be suppressed stably and sufficiently more than in the above embodiments. Further, by applying a predetermined voltage to the second gate @'l1120 connected to the first gate voltage w122 and effectively controlling the channel thickness aeH of the n-type channel region 12, the signal driving ability of the MESFET is increased. What can be improved is the same as in the case shown in FIG. 3(b) above.

In each of the embodiments shown in FIGS. 1 and 4 above, the island-shaped semi-insulating GaAs layer 6 in the insulating layer 4 is
We have described the case where one MBSFET is formed in the
ET, i.e. operating at approximately the same potential to increase the side gate voltage v
9.3 is a sufficiently small MESFET, not only one MESFET but a plurality of MESFETs may be formed in one island-shaped semi-insulating GaAs layer 6. As a result, one MESFET
The integration density can be improved by not forming the island-shaped semi-insulating GaAs layer 6 in each case.

Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be explained using FIG. 5.

For example, a resist is applied on the semi-insulating GaAs substrate 6a, and then patterned, and using the patterned resist 30 as a mask, the surface of the semi-insulating GaAs substrate 6a is selectively etched to a depth of about 0.3 μm. to form a mesa shape and separate the element formation region (see Fig. 5(a)).
)reference).

Next, resist patterning is performed again, and using the resist 32 as a mask, for example, silicon ions St+ are deposited at an acceleration voltage of 100 keV and a dose of 2X10"crrh-.
Ion implantation is performed under the conditions of ', to form an n-type channel region 12 on the surface of the mesa-shaped semi-insulating GaAs substrate 6a (see FIG. 5(b)).

Next, WSix with a thickness of about 0.3 μm was formed by sputtering.
After depositing the layer on the entire surface, resist patterning is performed, and using the resist as a mask, anisotropic etching is performed using a mixed gas of CF and 02 to form n.
A second gate electrode 20 made of WSix is formed on the type channel region 12 by rectifying bonding (see FIG. 5(c)).
.

Next, resist patterning is performed to form the resist 34 and the second gate 'gjkf! 20 as a mask,
For example, silicon ions Sl" are accelerated at a voltage of 200 keV,
Ion implantation is performed at a dose of 2 x 10" cm-2 to form an n++ source region 8 and an n+ type drain region 10 on the surface of the mesa-shaped semi-insulating GaAs substrate 68 with an n-type channel region 12 sandwiched therebetween (fifth (See figure (d)).

Next, CVD (Chen+1cal Vapor
After a StO2 layer 36 with a thickness of about 0.1 .mu.m is deposited on the entire surface by a deposition method, an annealing treatment is performed at a temperature of 850.degree. C. for 10 minutes in a N2 atmosphere (see FIG. 5(e)).

Next, after removing the 8102 layer 36, a Si Ot I'rl 4 film with a thickness of about 0.1 μm is formed again by CVD.
A is deposited on the entire surface, and then a layer 4b of StO having a thickness of about 0.8 μm is coated on the entire surface by a spin-on method. Then, heat treatment is performed at a temperature of 500° C. for 10 minutes (see FIG. 5(f)). ).

Next, after coating the entire surface with resist, CH.

This resist and the Sin layer 4b are etched back by dry etching using F gas, and StO2 is etched back.
The layer 4b is planarized (see FIG. 5(g)).

Next, on a separately prepared Si substrate 2, a film with a thickness of 0.5 μm was heat-treated at a temperature of 1000° C. in an 02 atmosphere.
3102 layer 4c is formed (see FIG. 5(h)).

Next, a semi-insulating GaAS substrate 6a shown in FIG. 5(g)
SIO□ layer 4b and S of the St substrate 2 shown in FIG. 5(h).
The iO□ layer 4c is placed face to face and pressure bonded. Then, a DC voltage of 300 V was applied for 0°03 seconds at a temperature of 850°C in an N2 atmosphere, and the semi-insulating GaAs
The substrate 6a and the S1 substrate 2 are bonded together. As a result, 5i02JI4a, 4 on the semi-insulating GaAs substrate 6a
b and the Sin layer 4c on the S1 substrate 2 form an insulating layer 4 (see FIG. 5(i)).

Next, the back surface of the semi-insulating GaAs substrate 6a is polished, and further wet etching and dry etching are performed.
Insulating layer 4 is exposed. As a result, an n++ source region 8, an n+ type drain region 10 and an n type channel region 12 are formed.
The mesa-shaped semi-insulating GaAs substrate 6a on which is formed becomes an island-shaped semi-insulating GaAs layer 6 in the insulating layer 4 (see FIG. 5(j)).

Next, resist patterning is performed, and using the resist 38 as a mask, the semi-insulating GaAs layer 6 on the second gate electrode 20 is selectively etched to form a contact window 40 on the second gate electrode @20. It opens (see Fig. 5(k)).

Next, WSix with a thickness of about 0.4 μm was formed by sputtering.
After the layer is deposited over the entire surface, resist patterning is performed. Then use the resist as a mask to apply CF4
By anisotropic etching using a mixed gas of and 02,
A first gate electrode 18 made of WSix and an extraction electrode 42 connected to the second gate yoke 20 through a contact window 40 are formed above the n-type channel region 12 by rectifying bonding (FIG. 5(J)). reference).

Next, a 5-layer film with a thickness of about 0.1 μm was formed by plasma CVD
An iNx (silicon nitride) layer 44 is deposited, and an sio layer with a thickness of about 0.3 μm is formed by CVD.
Deposit a layer to form Sl 0 x /S i N
Form x layer. Subsequently, resist buttering was performed to selectively etch 5 lots/SiNx layer.
A contact window is opened on the n++ source region 8 and the n1 type drain region 10. and A with a thickness of about 0.05 μm
A uGe layer and an approximately 0.35 μm thick Au layer are sequentially deposited to form an A u Ge /A u layer.

Subsequently, the resist and the 8102 layer are removed to leave the SiNx layer 44, and the n++ source region 8 and n+
The AuGe/Au layer is left above the molded drain region 10, and a source electrode 14 and a drain electrode 16 made of AuGe/Au are ohmically connected to each other. and at a temperature of 8 in N2 atmosphere.
Heat treatment is performed at 50° C. for 5 minutes (see FIG. 5(m)).

In this way, the MES of FIG.
A FET is formed.

Next, a method for manufacturing the semiconductor device shown in FIG. 4 will be explained using FIG. 6.

Among the process diagrams in FIG. 5, the steps shown in FIGS. 5(a) to 5(J) are common.

Therefore, following the step shown in FIG. 5(J), resist buttering is performed, and using the resist 46 as a mask, the semi-insulating GaAs layer 6 on the second gate electrode 20 is selectively etched. Contact windows 48 and 50 are opened on the second gate electrode i20 so as to expose the side surface of the type channel region 12 (see FIG. 6(a)).

Next, WSix with a thickness of about 0.4 μm was formed by sputtering.
After depositing the layer on the entire surface, resist buttering is performed, and the resist is used as a mask for anisotropic etching using a mixed gas of CF and 02 to form n.
A first gate electrode 22 made of WSix is formed above the type channel region 12 by rectifying junction. . That is, not only the upper and bottom surfaces of the n-type channel region 12 but also its side surfaces are covered by the first and second gates i'IfA22.20 (see FIG. 6(b)).

Next, a layer of 5iNx144 with a thickness of about 0.1 μm and a layer of 5102 with a thickness of about 0.3 μm were sequentially deposited to form the Si
Form an O2/S i N x layer, and this Si 02
/ SIN x layer is selectively etched to form n+
A contact window is opened above the + source region 8 and the n + -type drain region 10. And AuG with a thickness of about 0°05μm
An e layer and an Au layer with a thickness of about 0.35 μm are sequentially deposited,
Form A u G e / A u layer.

Subsequently, the resist and SiO layers are peeled off to form SiNx.
With layer 44 remaining, n++ source region 8 and n
On the + type drain region 10, a source electrode 14 and a drain electrode 16 made of AuGe/Au are formed by ohmic contact, respectively. Then, heat treatment is performed in a N2 atmosphere at a temperature of 850°C for 5 minutes (Fig. 6 (
c).

In this way, the n-type channel region 12 formed in the island-shaped semi-insulating GaAs layer 6 separated by the insulating layer 4 is
Except for the part sandwiched between the n1 type source and drain regions, the upper, bottom and side surfaces are all covered by the first and second
M in FIG. 4 covered by gate electrodes [22, 20
An ESFET is formed.

In the above embodiment, the case where the MESFET is formed in the semi-insulating GaAs layer 6 has been described, but the semiconductor crystal in which the element is formed is not limited to GaAS, but may be other It may be a binary, ternary or quaternary compound semiconductor consisting of elements. Alternatively, it may be a unitary semiconductor composed of a group Ⅰ element.

[Effects of the Invention] As described above, according to the present invention, an element is formed in an island-shaped semiconductor layer separated through an insulating layer, and a second gate is formed at the boundary between the bottom surface of the channel region of this element and the insulating layer. By providing the electrode, side gate effects from adjacent elements can be stably and sufficiently suppressed. Also,
By applying a predetermined voltage to the second gate electrode to control the channel thickness of the channel region, the operating speed of the device can be increased.

Thereby, it is possible to improve the integration density of the elements and improve the signal driving ability of the elements.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention, FIGS. 2 and 3 are diagrams for explaining the operation of the semiconductor device of FIG. 1, and FIG. 4 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. 5 and 6 are process diagrams showing a method of manufacturing the semiconductor device of FIGS. 1 and 4, respectively, and FIGS. 7 and 8 are cross-sectional views of a conventional semiconductor device, respectively. FIG. 2 is a diagram for explaining the device. In the figure, 2...81 substrate, 4...insulating layer, 4a, 4b, 4c, 36...5IO2N, 6...
...Semi-insulating GaAs layer, 6a, 52... Semi-insulating GaAs substrate, 8.5
4a, 54b... n+ type source region, 10.5
6a, 56b... n" type drain region, 12.
58a, 58b... n-type channel region, 14
．． 60a, 60b...-source electrode, 16.62a
, 62b...Drain electrode, 18.22...
...first gate electrode, 20...second gate electrode, 30.32.34.38.46...resist,
40.48.50...Contact window, 42...
...Extraction electrode, 44...SiNx layer, 64a, 64b...gate electrode, 66a,
66 b=---FET. 68... Element isolation region, 70... Wiring layer.

Claims (1)

[Claims] 1. A semiconductor layer formed in an island shape in an insulating layer on a semiconductor substrate; a source region and a drain region formed in the semiconductor layer; and a semiconductor layer sandwiched between the source region and the drain region. a channel region; a first gate electrode formed on the channel region; and a second gate electrode formed at a boundary between the bottom surface of the channel region and the insulating layer, and controlling the channel thickness of the channel region. A semiconductor device characterized in that a voltage is applied to the second gate electrode so that the voltage is applied to the second gate electrode. 2. The semiconductor device according to claim 1, wherein the second gate electrode is formed on the bottom and side surfaces of the channel region and is connected to the first gate electrode. 3. A first step of etching the surface of the first semiconductor substrate into a mesa shape, and after forming a channel region on the mesa-shaped first semiconductor substrate surface, forming a second gate electrode on the channel layer. , forming a source region and a drain region sandwiching the channel layer therebetween, and further forming an insulating layer over the entire surface; bonding a second semiconductor substrate onto the insulating layer; polishing and removing the bottom surface of the substrate until the insulating layer is exposed so that the mesa-shaped first semiconductor substrate becomes an island-shaped semiconductor layer in the insulating layer; and forming a first gate on the channel region of the semiconductor layer. 1. A method of manufacturing a semiconductor device, comprising the step of forming an electrode. 4. The method according to claim 3, when forming the first gate electrode on the channel region, selectively etching the semiconductor layer until reaching the second gate electrode to expose side surfaces of the channel region. A method of manufacturing a semiconductor device, characterized in that the first gate electrode is formed on the channel region and on the side surface thereof and connected to the second gate electrode.