JPH0398305A - Differential amplifier - Google Patents
Differential amplifierInfo
- Publication number
- JPH0398305A JPH0398305A JP23528289A JP23528289A JPH0398305A JP H0398305 A JPH0398305 A JP H0398305A JP 23528289 A JP23528289 A JP 23528289A JP 23528289 A JP23528289 A JP 23528289A JP H0398305 A JPH0398305 A JP H0398305A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- input terminal
- resistor
- differential amplifier
- resistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 abstract description 7
- 230000003321 amplification Effects 0.000 abstract description 2
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 101150030723 RIR2 gene Proteins 0.000 description 1
Abstract
Description
【発明の詳細な説明】
く産業上の利用分野〉
本発明は、差動増幅器の許容入力同相電圧範囲の改善に
関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an improvement in the allowable input common mode voltage range of a differential amplifier.
く従来の技術〉
第２図は従来の差動増幅器の基本的構或の一例を示す図
である。図において、Ａは電圧利得がＧの差動増幅器で
、正相入力端子ＩＮ＋と、逆相入力端子ＩＮ−と、入力
接地端子ＩＮＣＯＭの３つの入力端子があり、出力端子
ＯＵＴと出力接地端子ＯＵＴＣＯＭの２つの出力端子を
有する。なお、入力接地端子ＩＮＣＯＭと出力接地端子
ＯＵＴＣＯＭは、共に差動増幅器Ａの接地端子ＡＣＯＭ
に接続されている。2. Prior Art FIG. 2 is a diagram showing an example of the basic structure of a conventional differential amplifier. In the figure, A is a differential amplifier with a voltage gain of G, and has three input terminals: a positive-phase input terminal IN+, a negative-phase input terminal IN-, and an input ground terminal INCOM, and an output terminal OUT and an output ground terminal OUTCOM. It has two output terminals. Note that the input ground terminal INCOM and the output ground terminal OUTCOM are both the ground terminal ACOM of the differential amplifier A.
It is connected to the.
入力信号源としては、２つの差動信号源Ｖｄ／２と、１
つの同相信号源Ｖｃｍがある。理想的な差動増幅器にお
いては、出力電圧ｖＯは入力差動電圧Ｖｄの利得Ｇ倍で
あり、入力同相電圧Ｖｃｍの大きさによって変化しない
ようになっている。As input signal sources, two differential signal sources Vd/2 and 1
There are two in-phase signal sources Vcm. In an ideal differential amplifier, the output voltage vO is a gain G times the input differential voltage Vd, and does not change depending on the magnitude of the input common mode voltage Vcm.
く発明が解決しようとする課題〉
しかしながら、現実の差動増幅器では、有限の電源電圧
＋Ｖ’ｃｃおよび−Ｖｃｃが供給されており、入力接地
端子ＩＮＣＯＭを基準とする正相入力端子ＩＮ＋および
逆相入力端子ＩＮ−の電位が十Ｖｃｃ〜−Ｖｃｃ範囲を
越えることができず、これを越えた場合、すなわち同相
入力電圧Ｖｃｍが電源電圧を越えた場合は、差動増幅器
Ａの内部回路は正しく動作できなくなるという問題があ
った。Problems to be Solved by the Invention> However, in an actual differential amplifier, finite power supply voltages +V'cc and -Vcc are supplied, and the positive phase input terminal IN+ and negative phase input terminal IN+ with respect to the input ground terminal INCOM are If the potential of the input terminal IN- cannot exceed the range of 10Vcc to -Vcc, that is, if the common-mode input voltage Vcm exceeds the power supply voltage, the internal circuit of differential amplifier A will not operate correctly. The problem was that I couldn't do it.
本発明は、このような点に鑑みてなされたもので、その
目的は、正負の電源電圧の範囲をはるかに越えた同相入
力電圧に対しても影響を受けず正しく差動電圧戊分を増
幅することのできる差動増幅器を提供することにある。The present invention has been made in view of these points, and its purpose is to amplify differential voltage components correctly without being affected by common-mode input voltages that far exceed the range of positive and negative power supply voltages. The object of the present invention is to provide a differential amplifier that can perform
く課題を解決するための手段〉
このような［１的を達或するための本発明は、正相入力
端子と差動入力端子の間に接続される第１の抵抗と、逆
相入力端子と差動増幅器の反転入力端子に接続される第
２の抵抗と、正相入力端子と逆相入力端子の間に接続さ
れる直列接続の第３および第４の抵抗と、
第３および第４の抵抗の共通接続点の電位を電流に変換
し、差動増幅器の非反転入力端子に与える第１の電圧一
電流変換器と、
第３および第４の抵抗の八通接続点の電位を電流に変換
し、差動増幅器の非反転入力端子に与える第２の電圧一
電流変換器とを具備したことを特徴とする。Means for Solving the Problems> The present invention for achieving the first object has a first resistor connected between a positive phase input terminal and a differential input terminal, and a negative phase input terminal. and a second resistor connected to the inverting input terminal of the differential amplifier; third and fourth resistors connected in series between the positive phase input terminal and the negative phase input terminal; The first voltage-to-current converter converts the potential at the common connection point of the resistors into a current and supplies it to the non-inverting input terminal of the differential amplifier. The present invention is characterized by comprising a second voltage-to-current converter for converting the voltage into the voltage and applying it to the non-inverting input terminal of the differential amplifier.
く作用〉
第３および第４の抵抗を同じ大きさに設定すると共に、
第１の電圧一電流変換器の変換利得Ｋ１を第１の抵抗の
値の逆数に、また第２の電圧一電流変換器の変換利得Ｋ
２を第２の抵抗の値の逆数に設定すると、第１および第
２の抵抗の電圧降下は共に入力同相電圧に等しくなる。Effect〉 Setting the third and fourth resistors to the same magnitude,
The conversion gain K1 of the first voltage-to-current converter is the reciprocal of the value of the first resistor, and the conversion gain K1 of the second voltage-to-current converter is
If 2 is set to be the reciprocal of the value of the second resistor, the voltage drops across the first and second resistors will both be equal to the input common mode voltage.
これにより、差動増幅器の入力同相電圧は見か３
４
け上零となり、入力同相電圧の影響を受けずに差動入力
電圧を増幅することができる。As a result, the input common mode voltage of the differential amplifier becomes approximately 34 times zero, and the differential input voltage can be amplified without being affected by the input common mode voltage.
く実施例〉 以下図面を参照して本発明を詳細に説明する。Example The present invention will be described in detail below with reference to the drawings.
第１図は本発明に係る差動増幅器の一実施例を示す構成
図である。図において、第２図と同等部分には同一符号
を付しその説明は省略する。Ｒ１，Ｒ２，Ｒ３，Ｒ４は
抵抗、ＶＩ１，ＶＩ２は電圧一電流変換器である。FIG. 1 is a block diagram showing one embodiment of a differential amplifier according to the present invention. In the figure, the same parts as those in FIG. 2 are given the same reference numerals, and the explanation thereof will be omitted. R1, R2, R3, and R4 are resistors, and VI1 and VI2 are voltage-to-current converters.
第２図と異なるところは、差動増幅器Ａの反転および非
反転入力端子対と、正相および逆相入力端子ＩＮ＋，Ｉ
Ｎ−との間に、４本の抵抗ＲＩＲ２，Ｒ３，Ｒ４と２つ
の電圧一電流変換器Ｖｌ１，ＶＩ２が挿入接続されて構
成された同相電圧除去回路が挿入された点である。The difference from FIG. 2 is that the pair of inverting and non-inverting input terminals of the differential amplifier A and the positive-phase and negative-phase input terminals IN+, I
A common mode voltage removal circuit configured by inserting and connecting four resistors RIR2, R3, R4 and two voltage-to-current converters Vl1, VI2 is inserted between N- and N-.
第１の抵抗Ｒ１は正相入力端子ＩＮ＋と差動増幅器Ａの
非反転入力端子の間に接続され、第２の抵抗Ｒ２は逆相
入力端子ＩＮ一と差動増幅器Ａの反転入力端子の間に接
続される。The first resistor R1 is connected between the positive phase input terminal IN+ and the non-inverting input terminal of the differential amplifier A, and the second resistor R2 is connected between the negative phase input terminal IN1 and the inverting input terminal of the differential amplifier A. connected to.
第３の抵抗Ｒ３はその一端が正相入力端子ＩＮ十と第１
の抵抗Ｒ１との共通接続点に接続され、第４の抵抗は逆
相入力端子ＩＮ一と第３の抵抗Ｒ３の他端の間に接続さ
れる。The third resistor R3 has one end connected to the positive phase input terminal IN
The fourth resistor is connected to a common connection point with the resistor R1, and the fourth resistor is connected between the negative phase input terminal IN1 and the other end of the third resistor R3.
イマ、抵抗Ｒ３，Ｒ４を互いに等しい抵抗値とすること
により、両抵抗の共通接続点Ｐの電位は丁度入力同相電
圧Ｖｃｍと等しくなる。By setting the resistors R3 and R4 to have the same resistance value, the potential at the common connection point P of both resistors becomes exactly equal to the input common mode voltage Vcm.
第１の電圧一電流変換器Ｖｌｌと第２の電圧一電流変換
器ＶＩ２には、前記Ｐ点の電圧がそれぞれ与えられ、Ｖ
Ｉ１の出力電流Ｊ１は差動増幅器Ａの非反転入力に、ま
たＶＩ２の出力電流は差動増幅器Ａの反転入力にそれぞ
れ与えられる。The voltage at the point P is applied to the first voltage-to-current converter Vll and the second voltage-to-current converter VI2, and V
The output current J1 of I1 is applied to the non-inverting input of differential amplifier A, and the output current of VI2 is applied to the inverting input of differential amplifier A.
このような構成における動作を次に詳細に説明する。こ
こで、差動増幅器Ａの入力インピーダンスは抵抗Ｒｌ，
Ｒ２に比べて十分に大きい値であるとすると、電圧一電
流変換器Ｖｌｌの出力電流Ｊ１はすべて抵抗Ｒ１に流れ
、また電圧一電流変換器ＶＩ２の出力電流Ｊ２はすべて
抵抗Ｒ２に流れることになる。このとき正相入力端子Ｉ
Ｎ＋と差動増幅器Ａの非反転入力との間の電位差はＪ１
×Ｒ１、他方逆相入力端子ＩＮ一と差動増幅器Ａの反転
入力との電位差はＪ２ＸＲ２であり、ＩＮ＋およびＩＮ
一にかかっていた同相電圧ＶｃｍはそれぞれＪ１ｘＲ１
，Ｊ２ｘＲ２だけ減少して差動増幅器Ａにかかることに
なる。The operation in such a configuration will be described in detail below. Here, the input impedance of the differential amplifier A is the resistance Rl,
Assuming that the value is sufficiently large compared to R2, all the output current J1 of the voltage-to-current converter Vll will flow to the resistor R1, and all the output current J2 of the voltage-to-current converter VI2 will flow to the resistor R2. . At this time, the positive phase input terminal I
The potential difference between N+ and the non-inverting input of differential amplifier A is J1
×R1, the potential difference between the other negative phase input terminal IN1 and the inverting input of the differential amplifier A is J2XR2, and the potential difference between IN+ and IN+
The common mode voltage Vcm applied to each J1xR1
, J2xR2 is applied to the differential amplifier A.
一方、前述のように、２つの電圧一電流変換器の入力は
共にＰ点に接続され、この点には入力同相電圧Ｖｃｍに
等しい電圧がかかっている。On the other hand, as described above, the inputs of the two voltage-to-current converters are both connected to point P, and a voltage equal to the input common mode voltage Vcm is applied to this point.
いま、電圧一電流変換器ｖ■１の変換利得をＫ１とし、
Ｋ１＝１／Ｒｌ
と設定した場合、入力同相電圧Ｖｃｍにおける抵抗Ｒ１
の電圧降下は、
ＪＩＸＲ１＝Ｖｃｍ
となり、丁度入力同相電圧に等しくなる。Now, if the conversion gain of the voltage-to-current converter v■1 is set as K1 and K1=1/Rl, then the resistance R1 at the input common mode voltage Vcm
The voltage drop is JIXR1=Vcm, which is exactly equal to the input common mode voltage.
同様にして、電圧一電流変換器ＶＩ２の変換利得をＫ２
とし、
Ｋ２＝１／Ｒ２
と設定した場合の入力同相電圧Ｖｃｍにおける抵抗Ｒ２
の電圧降下は、
Ｊ２ｘＲ２＝Ｖｃｍ
となり、これも丁度入力同相電圧に等しくなる。Similarly, the conversion gain of the voltage-to-current converter VI2 is set to K2
The resistance R2 at the input common mode voltage Vcm when K2=1/R2 is set.
The voltage drop is J2xR2=Vcm, which is also exactly equal to the input common mode voltage.
以上のような回路定数に設定することにより、差動増幅
器Ａの入力同相電圧は見かけ上Ｖｃｍの大きさにかかわ
らず常に零となり、原理的には入力同相電圧Ｖｃｍがい
かに大きな値となっても差動増幅器Ａは入力の差動電圧
Ｖｄを正しく増幅することができることになる。By setting the circuit constants as described above, the input common-mode voltage of differential amplifier A is always zero regardless of the apparent magnitude of Vcm, and in principle, no matter how large the input common-mode voltage Vcm becomes. The differential amplifier A can correctly amplify the input differential voltage Vd.
〈発明の効果〉
以上詳細に説明したように、本発明によれば、正負の電
源電圧をはるかに上回る大きさの同相電圧を含む差動入
力電圧についても、同相電圧の影響を受けずに正しく増
幅することができる差動増幅器を実現することができる
。<Effects of the Invention> As explained in detail above, according to the present invention, even a differential input voltage including a common mode voltage far exceeding the positive and negative power supply voltages can be correctly processed without being affected by the common mode voltage. A differential amplifier capable of amplification can be realized.
第１図は本発明に係る差動増幅器の一実施例を示す構成
図、第２図は従来の差動増幅器の一例を示す構成図であ
る。
Ａ・・・差動増幅器
Ｊｌ，Ｊ２・・・電圧−電流変換器
Ｒ１〜Ｒ４・・・抵抗 Ｖｃｍ・・・入力同相電圧Ｖ
ｄ／２・・・差動信号源
９FIG. 1 is a block diagram showing an embodiment of a differential amplifier according to the present invention, and FIG. 2 is a block diagram showing an example of a conventional differential amplifier. A... Differential amplifier Jl, J2... Voltage-current converter R1 to R4... Resistor Vcm... Input common mode voltage V
d/2...Differential signal source 9
Claims (1)
と、 差動入力電圧を増幅して出力する差動増幅器と、この差
動増幅器の非反転入力端子に一端が接続され、他端が正
相入力端子に接続された第１の抵抗と、 前記差動増幅器の反転入力端子に一端が接続され、他端
が逆相入力端子に接続された第２の抵抗と、 正相入力端子と前記第１の抵抗の共通接続点の間に一端
が接続された第３の抵抗と、 逆相入力端子と前記第２の抵抗の共通接続点と前記第２
の抵抗との間に接続された第４の抵抗と、第３と第４の
抵抗の共通接続点の電位を電流に変換し、その電流出力
を前記差動増幅器の非反転入力に与える第１の電圧−電
流変換器と、 第３と第４の抵抗の共通接続点の電位を電流に変換し、
その電流出力を前記差動増幅器の反転入力に与える第２
の電圧−電流変換器とを具備した差動増幅器。[Claims] A positive phase input terminal and a negative phase input terminal to which a differential input voltage is applied, a differential amplifier that amplifies and outputs the differential input voltage, and a non-inverting input terminal of this differential amplifier. a first resistor having one end connected to the positive phase input terminal and the other end connected to the positive phase input terminal; and a second resistor having one end connected to the inverting input terminal of the differential amplifier and the other end connected to the negative phase input terminal. a third resistor, one end of which is connected between the common connection point of the positive phase input terminal and the first resistor, and the common connection point of the negative phase input terminal and the second resistor, and the second resistor.
a fourth resistor connected between the fourth resistor and the first resistor, which converts the potential at the common connection point of the third and fourth resistors into a current, and supplies the current output to the non-inverting input of the differential amplifier. converting the potential at the common connection point of the third and fourth resistors into a current;
a second circuit whose current output is applied to the inverting input of the differential amplifier;
A differential amplifier comprising a voltage-to-current converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23528289A JPH0398305A (en) | 1989-09-11 | 1989-09-11 | Differential amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23528289A JPH0398305A (en) | 1989-09-11 | 1989-09-11 | Differential amplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0398305A true JPH0398305A (en) | 1991-04-23 |
Family
ID=16983793
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23528289A Pending JPH0398305A (en) | 1989-09-11 | 1989-09-11 | Differential amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0398305A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012235376A (en) * | 2011-05-06 | 2012-11-29 | Sumitomo Electric Ind Ltd | Electronic circuit and light-receiving circuit |
-
1989
- 1989-09-11 JP JP23528289A patent/JPH0398305A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012235376A (en) * | 2011-05-06 | 2012-11-29 | Sumitomo Electric Ind Ltd | Electronic circuit and light-receiving circuit |
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