JPH0397192A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To realize multi-function with simple constitution by sending an output signal externally via an output selection circuit receiving a readout signal comprising plural bits and shifting selectively one or plural bits in positive and/or negative direction according to a prescribed control signal. CONSTITUTION:Switch control is applied by using an alternative selection signal formed by a shift register SR acting like a pointer to switch MOSFETs Q1, Q2 and Q3, Q4. In order to attain a serial output from an optional bit, an output signal of the final stage of the shift register SR is fed back to a 1st stage circuit. Since a data outputted serially is subject to weight control, it is inputted to an output selection circuit (shifter) to apply weight change such as X1/2 or X2 to the data. The shifter SFT according to a control signal OS shifts one or plural bits altogether in positive or negative direction of the inputted data and gives the result to an output circuit DOB. Thus, the output signal with weight change of X1/2 or X2 is simply obtained by the switching of the output selection circuit SFT.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and in particular to a technique that is effective for use in an image memory equipped with a serial output function.

[Conventional technology]

As a RAM (random access memory) for image processing to display characters and figures on a CRT (cathode ray tube) screen, for example, Nikkei McGraw-Hill Co., Ltd. 1985 2
March 11th r Nikkei Electronics” pages 219-22
The serial access memory (dual port RAM) described in No. 9 is well known. In this RAM, a data line of a memory array is connected in parallel to a data register via a switch circuit, and data is serially output between the data register and an external terminal. As a result, the storage information of the memory cell connected to the selected word line is output serially, so C
Pixel data can be easily extracted in synchronization with the RT rask scan timing.

[Problem to be solved by the invention]

In image application systems, ×1 for image data
Weight controls such as 72, x2, and x4 are required. For example, by controlling the weighting as described above, a desired color tone can be obtained by changing color classification and brightness. However, since the above-mentioned RAM outputs the stored information serially as it is, it is necessary to process the image data as described above using a microprocessor, etc., and the data processing takes time. , which increases the burden on the software.

An object of the present invention is to provide a semiconductor memory device that achieves multiple functions with a simple structure.

Another object of the present invention is to provide a semiconductor memory device for images that is equipped with a high-speed weight control function for image data.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the output signal is sent to the outside via an output selection circuit that receives a read signal consisting of a plurality of bits and selectively shifts one bit or a plurality of bits in the positive and/or negative direction according to a predetermined control signal.

[For production]

According to the above-mentioned means, it is possible to easily obtain an output signal whose weight has been changed by ×l/2 or ×2 by switching the output selection circuit.

〔Example〕

FIG. 7 shows a block diagram of an embodiment of an image memory to which the present invention is applied. Each circuit block in the figure is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon using known semiconductor integrated circuit manufacturing techniques.

Although the semiconductor memory device of this example is not particularly limited,
The basic configuration is a dynamic RAM that is accessed in units of 4 bits (x4 bit structure), and has a serial output function as described below, as well as an internal output selection circuit for changing the weight of output data. A circuit is added. Although not particularly limited, the memory section RAM in the figure is
It consists of four sets of memory arrays, sense amplifiers, and address decoder circuits. Although not shown, the memory section RAM includes address selection MOSFEs arranged in a matrix.
It includes a Dyna5 type memory cell consisting of an insulated gate field effect transistor (T) and a capacitor for storing information. MOS for address selection of the above memory cells
The FET has its gate coupled to a corresponding word line;
A drain is coupled to one corresponding data line.

The structure of such a memory section RAM is similar to that of a known dynamic RAM having a ×4 bit structure.
A detailed explanation thereof will be omitted.

Signals on complementary data lines in the memory array are transferred to data launch circuit FF via switch circuit SW, although not particularly limited thereto. These switch circuits SW and latch circuits FF are provided respectively for the four sets of memory arrays. The switch MOSFET that constitutes the switch circuit SW is turned on by a transfer tying signal φS, and transmits the data of each complementary data line amplified by the sense amplifier in the RAM to the latch circuit FF. It is. In order to serially output the data held in the latch circuit FF, each complementary holding signal D of the launch circuit FF is
o, DO or Dn, Dn are switch MOSFETQ
Common data line CD via I, Q2 or Q3, Q4
, is transmitted to the CD.

Each of the above switches MOSFET QI, Q2 to Q3, Q
4 is switch-controlled by an alternative selection signal formed by a shift register SR acting as a pointer. In this embodiment, although not particularly limited, in order to enable serial output from arbitrary bits, the output signal of the final stage of the shift register SR is fed back to the first stage circuit. By this, shift register SR
is assumed to perform a ring-shaped shift operation. Although not particularly limited, the shift register SR has its initial value (logic "1") set by a decode signal of a column address signal supplied during a serial transfer mode, which will be described later. In other words, in the shift register SR, a selection signal of logic "1" is set in the bit corresponding to the complementary data line of the RAM designated by the RAM address signal.

The shift register SR receives a shift clock signal φ generated by the timing control circuit TC based on a clock signal supplied from an external terminal SC, and shifts the selection signal (logic "1"). As a result, data for one word line can be serially output in units of 4 bits.

In this embodiment, the data output serially is
In order to perform weight control, in other words, it is input to an output selection circuit (thick) SFT for changing the weight of data such as xl/2 or x2. The shifter SFT shifts manually input data by one bit or a plurality of bits in the positive or negative direction at once and transmits the shifted data to the output circuit DOB according to the control signal OS.

In this embodiment, although not particularly limited, the ×4 bit data stored in the RAM is image data;
Eight levels of gradation are displayed using bits. Therefore, when performing color display using the three primary colors of red, blue, and green, data for displaying one pixel is composed of three RAMs. Alternatively, in the case of black-and-white display, 8-level gradation display (including black) is performed using the x4-bit image data.

Row address buffer R-ADB receives timing signal φr generated by row address strobe signal RAS.
Row-related address signal AX consisting of multiple bits in synchronization with
and forms an internal complementary address signal to be transmitted to the row address decoder.

The row address decoder included in the memory section RAM decodes the address signal and selects a predetermined word line and dummy word line in synchronization with the word line selection timing signal.

The column address buffer C-ADB takes in a column-related address signal AY consisting of a plurality of bits and transmits it to the column address decoder in synchronization with a timing signal φC formed by a column address strobe signal CAS that is supplied with a delay. The column address decoder included in the memory section RAM decodes the address signal, and
The data line selection operation is performed in synchronization with the data line selection timing signal. In the RAM data parallel transfer operation mode described later, the decode output corresponding to the data line selection signal in the column address decoder is as follows.
It is used to form the initial value (logic "1") of the shift register SR.

In the figure, the signal path for setting the initial value is omitted to prevent the circuit from becoming complicated.

In order to perform writing by random access in units of ×4 bits, the data manual circuit IB consists of a total of four circuits, and when it is put into the operating state by the operation timing signal φin, the data input circuit IB is Each of the 4-bit signals is amplified and connected to the input/output line I/O of the memory section RAM.
Tell O. As a result, a write operation is performed on each of the four memory cells selected by the address selection circuit.

In order to perform a read operation by random access in units of ×4 bits, the data output circuit OB has a total of 4Mi
When activated by the operation timing signal φop, the circuit amplifies the signal consisting of a total of 4 bits of the corresponding input/output line I/O of the memory section RAM and sends it to the external terminal D. let

The timing control circuit TC receives address strobe signals RAS and C supplied from external terminals, although this is not particularly limited.
AS, write enable signal WE, data transfer signal DT
, cross clock signal SC for operation of shift register SR
and a serial output enable signal SOE, it identifies the operating mode and formats various timing signals accordingly. A control signal OS for weight control of the serial output data is also input. This signal OS
In addition to those that are supplied to the output selection circuit through a suitable input bathophore circuit or decoder circuit, they are once input to the timing control circuit TC, and from this control circuit TC, a control signal is formed that is supplied to the output selection circuit SFT. It is also possible to do so. The signal OS may be a signal consisting of multiple bits, as described later, in addition to an 1-bit signal.

The refresh control circuit REFC includes a refresh address counter circuit that controls the refresh address signal. The refresh address counter circuit is
Before the signal RAS goes from high level to low level,
In response to the refresh signal φrf generated when it is determined that the signal CAS is at a low level, an address increment (counting operation) is performed using the signal RAS as a clock signal. In the refresh mode (CAS before RAS refresh), the refresh address signal formed by the refresh control circuit REFC is transmitted to the row address buffer R-ADB,
A memory cell refresh operation is performed by a row-related selection operation such as being supplied to the row decoder of the memory section RAM through the row address buffer sofa R-ADB. In order to realize the above refresh operation, the input section of the row address buffer R-ADB is equipped with a multiplexer that switches between the address signal supplied from the external terminal and the address signal formed by the automatic refresh control circuit REFC. A function is provided.

Next, according to the timing diagram shown in FIG.
An outline of the serial output operation in M is explained b. When the data transfer signal DT is set to low level before the row address strobe signal RAS changes from high level to low level, the timing control circuit TC detects this and transfers the data. Determine mode. In synchronization with the low level of the row address strobe signal RAS, a row-related address signal AX is taken in, and a RAM row-related selection operation, that is, one word line selection operation, is performed.
The amplification operation of the sense amplifier is performed, and a signal according to the stored information of the selected memory cell appears on each complementary data line of the RAM.

When the column address strobe signal CAS is set to a low level, a column-related address signal AY is taken in in synchronization with this. In this operation mode, initial value setting of the shift register SR is performed instead of the column system selection operation. That is, a selection signal of logic "1" is taken into the bit of the shift register SR designated by the decoded output of the address signal AY of the input RAM system. Also,
In accordance with the change of the data transfer signal DT from low level to high level, the transfer timing signal φS (not shown) is generated, and the signals on each complementary data line of the RAM are transferred in parallel to the latch circuit FF.

Thereafter, when the serial output enable signal ``E'' is changed from high level to low level, shift register SR starts a shift operation. As a result, the information held in the latch circuit FF corresponding to the bit of the shift register SR designated by the column-system address signal AY is serially output.

In this serial output operation, the output selection circuit SFT, which serves as a bit shifter for output data, determines whether to transmit the information bits consisting of 4 bits as is or to shift the information bits by 1 bit in the positive direction according to the control signal OS, for example.
Shift only bits in the negative direction. This allows RAM
It is possible to perform weight changes of x1, x2, and x1/2 on the image data read out from the image data section.

FIG. 1 shows a circuit diagram of an embodiment of the output selection circuit SFT having the x2 weight changing function described above.

In this embodiment, a clothed inverter circuit is utilized. That is, an inverter circuit having a tri-state output function whose output is selectively brought into a high impedance state by a control signal supplied to a cross-link terminal is used. Clocked inverter circuits CNO to CN3 are provided to transmit the image data DO-D3 outputted from the serial readout circuit to the output circuit as is, in other words, to perform ×1 weight control.

These crossed inverter circuits CNO to CN3
The above-mentioned image data DO to D3 are supplied to the human power. These clocked inverter circuits CNO or C
The output signal of N3 is sent out from external terminals OUTO to OUT3 via output circuits DOBO to DOB3.

On the other hand, in order to shift the image data Do-D3 output from the serial readout circuit in the positive direction by 1 bit and transmit it to the output circuit, in other words, to perform ×2 weight control, the clocked inverter Circuits CN4 to CN7 are provided. The clocked inverter circuit CN4 is supplied with the ground potential of the circuit corresponding to the logic "O", and other clocked inverter circuits C
Image data DO is provided for human power of N5 to CN7 respectively.
to D2 are supplied. The most significant bit data D3 will overflow in the case of x2 weight control, so it is not supplied to any of the clock and quadrature inverter circuits CN4 to CN7. The output signals of these clocked inverter circuits CN4 to CN7 are shifted by 1 bit and output to output circuits DOBO to DOB.
3 input. That is, the output signal of the clocked inverter circuit CN4 that receives logic "0" is applied to the output circuit DOBO corresponding to the bit BO, and the output signal of the clocked inverter circuit CN5 that receives the image data Do is applied to the bit Bl. The output signal of the cross inverter circuit CN6 which receives the image data Di at the input of the corresponding output circuit DOB1 is outputted to the output circuit D corresponding to the image data B2.
The output signal of the clocked inverter circuit CN7 which receives the image data D2 at the input of OB2 is supplied to the input of the output circuit DOB3 corresponding to bit 1-83.

In the crossed inverter circuits CNO to CN3 that perform the above x1 weight control, the control signal OS is at a low level (logic "0-"), as shown in the operation waveform diagram of FIG.
It is activated when , and transmits the input image data DO to D3 as is to the output circuits DOBO to DOB3 of the corresponding bits BO to B3. This results in
Image data D is output from output terminals OUTO to OUT3.
o to D3 are output.

The crossed inverter circuits CN4 to CN7 that perform the weight control of the above-mentioned Of the image data Do to D3, the image data DO to D2 are shifted in the positive direction by one bit and transmitted to the output circuits DOB1 to DOB3 of the image data B1 to B3. Further, the output signal of the crossed inverter circuit CN4 receiving logic "0" is transmitted to the lowest bit BO. This allows the output terminal OU
From TO to OUT3, logic “O” is output as image data.
” and D1 or D2 are output.

Note that the output circuits DOBO to DOB3 output the input bits BO to B3 when activated by the output control signal DOC, and when rendered inactive by the output control signal DOC. Put the output into high impedance state. Further, when a clocked inverter circuit is used as the output selection circuit SFT as described above, the manually input image data DO to D3 are inverted and transmitted to the output circuits DOBO to DOB3. Therefore, the output circuits DOBO to DOB3 invert the human input signal to return it to its original state and output it.

FIG. 4 shows a circuit diagram of an embodiment of an output selection circuit SFT having a weight change function of x2 and x1/2.

In this embodiment, ×l/2 is added to the circuit shown in FIG.
Black inverter circuits CN8 to CNII are added to realize the weight changing function.

Image data D output from the above serial readout circuit
In order to shift o-D3 by 1 bit in the negative direction and transmit it to the output circuit, in other words, in order to perform the above-mentioned weight control of ×l/2, the crossed inverter circuit CN is used.
Clocked inverter circuit C from 8 to CNII
The input of NII is supplied with the ground potential of the circuit corresponding to the logic "O", and the inputs of other crossed inverter circuits CN8 to CNIO are supplied with image data DI to D3, respectively. The data DO of the lowest Bisoto is ×
In the case of 1/2 weight control, underflow occurs, so the above clocked inverter circuit CN8 or C
It will not be supplied to any of NII's manpower. The output signals of these crossed inverter circuits CN8 to CNII are supplied to the inputs of output circuits DOBO to DOB3 after being shifted in the negative direction by 1bit7}. That is, the logic “O
The output signal of the clocked inverter circuit CNl1 which receives the image data D3 is outputted from the clocked inverter circuit C which receives the image data D3 to the output circuit DOB3 corresponding to bit B3.
The output signal of NIO is output from output circuit D corresponding to Bift B2.
The output signal of the clocked inverter circuit CN9 which receives the image data D2 at the input of OB2 is the output signal of the clocked inverter circuit CN8 which receives the image data DI at the input of the output circuit DOB1 corresponding to bits I-Bl. are respectively supplied to the output circuit DOBO corresponding to the BISOTO BO.

In this example, ×2 including the ×1 weight control.
It is necessary to make three output selections consisting of and x 1/2. Therefore, it is necessary to use three types of control signals: ○S and OS3. Although not particularly limited, these control signals OS1 to OS3 are formed by decoding a control signal consisting of 2 bits.

The control terminals of the clocked inverter circuits CNO to CN3 that realize ×1 weight control are shared and supplied with a control signal OSI. Crossed inverter circuits CN4 to CN7 that realize ×2 weight control
The control terminals of are shared and supplied with a control signal ○S2. Then, newly added clocked inverter circuits CN8 to C realize weight control of ×l/2.
The Nil control terminal is shared and supplied with a control signal OS3.

In this structure, when the control signal OS1 is set to high level during normal operation and the other control signals OS2 and OS3 are set to low level, the clocked inverter circuits CNO to CN3 that perform x1 weight control are activated.
The other clocked inverter circuits CN4 to CNII are placed in an output high impedance state. As a result, the image data DO to D3 serially read out from the memory section are directly output to the output terminals OUT through the output circuits DOBO to DOB3 of the corresponding BISOTO BO to B3.
Sent from I to OUT3.

Further, in the case of ×2 operation, when the control signal OS2 is set to high level and the other control signals OSI and OS3 are set to low level, the clocked inverter circuits CN4 to CN7 that perform ×2 weight control are activated, and the other control signals The clocked inverter circuits CNO to CN3 and CN8 to CNI1 are placed in an output high impedance state. As a result, the image data Do to D3 serially read out from the memory section are shifted in the positive direction by one bit, and the data DO- to D2 are output to the output terminal ○ through the output circuits DOBI to DOB3 of bits Bl to B3. The signal is sent from UTI to OUT3, an inverted signal of logic "0" is supplied to the least significant bit BO, and the signal is sent from the output terminal OUTO through the output circuit DOBO.

When the control signal OS3 is set to a high level and the other control signals OSI and OS2 are set to a low level during ×l/2 operation, the cloth impedance circuits CN8 to CNII that perform ×l/2 weight control are in the operating state. and other crossed inverter circuits CNO to CN7
is placed in an output high-impedance state. This results in
The image data Do to D3 that are serially read out from the memory section are shifted in the negative direction by 1 bit all at once, and the data DI to D3 are output to the output terminal OUT through the output circuits DOBO to DOB2 of bits I-BO to B2.
The most significant bit B3 is supplied with an inverted signal of logic "0" and is sent out from the output terminal OUT3 through the output circuit DOB3.

With this configuration, weight control can be selectively performed in three ways including x1, x2, and x1/2. As a result, for example, in black and white gradation display, the brightness of a pixel can be quickly doubled or halved simply by controlling the output selection circuit provided in the serial output section, without rewriting the image data in the memory section. .

In addition, if you add a crossed inverter circuit that shifts 2 bits in the positive and/or negative direction, it will be possible to quadruple and/or l
/4 weight control can be performed. In this case, it is necessary to perform five types of control including the weight control of x1 described above, so 3 bits are used as the control signal, which is decoded to generate the one control signal described above alternatively. Just let it happen.

FIG. 5 shows a circuit diagram of an embodiment of the clocked inverter circuit.

P-channel MOSFETs QI and Q2 and N-channel MOSFETs Q3 and Q4 are connected in series. Above P-channel MOSFET Q2 and N-channel MOS
The gates of FETQ3 are commonly connected to the input terminal IN
It is said that The gate of the N-channel MOSFET Q4 is connected to the clock terminal CK, and the gate of the P-channel MOSFET Q4 is connected to the clock terminal CK.
The gate of SFETQ1 is connected to a clock terminal CK via an inverter circuit N1. As a result, when the level of the control signal supplied to the clock terminal CK is high level, the N-channel MOSFETQ4 and P
Channel MOSFETQI turns on and receives a signal from input terminal IN.CMOS consists of P-channel MOSFETQ2 and N-channel MOSFETQ3.
The inverter circuit is activated and an output signal corresponding to the signal at the input terminal IN is formed. When the level of the control signal supplied to the clock terminal CK is low level, the N-channel MOSFET Q4 and the P-channel MOSFET
Q1 turns off and P receives the signal from the human input terminal IN.
Channel MOSFETQ2 and N-channel MOSFET
The CMOS inverter circuit consisting of TQ3 becomes inactive and the output OUT becomes a high impedance state.

Note that when constructing a clocked inverter circuit that becomes active when the level supplied to the clock terminal CK is low level, the gate of the P-channel MOSFET QI is connected to the cloth terminal, and the gate of the N-channel MOSFET QI is connected to the cloth terminal.
A cloth terminal GK is connected to the gate of S FETQ 4 via an inverter circuit.

FIG. 6 shows a circuit diagram of another embodiment of the unit selection circuit used in the output selection circuit. In this embodiment, a P-channel MOSFET Q5 and an N-channel MOSFET are connected to the output section of the CMOS inverter circuit N2.
A CMOS switch circuit consisting of Q6 is provided. The gate of the MOSFET Q6 is connected to a control terminal (closing terminal) CK, and the gate of the MOSFET Q5 is connected to the control terminal CK via an inverter circuit N3.

In this configuration, when a high level is supplied to the control terminal CK, the N-channel MOS that constitutes the CMOS switch circuit
Both FETQ6 and P-channel MOSFETQ5 are turned on and transmit the output signal of the human-powered inverter circuit N2 to the output terminal OUT.

When a low level is supplied to the control terminal CK, the N-channel MOSFETQ6 and P
Both channel MOSFETQ5 are in the off state,
The output terminal OUT is brought into a high impedance state regardless of the output signal of the input inverter circuit N2.

As a result, the circuit shown in FIG. 6 performs an operation equivalent to the clocked inverter circuit described above, and can be used in place of the clocked inverter circuit shown in FIGS. 1 and 4. .

In FIG. 6, the input inverter circuit N2 may be omitted. In this configuration, selective signal transmission paths are established by CMOS switch circuits. With this configuration, the signal is transmitted as is without phase inversion on the selected signal transmission path. Therefore, in the output circuit, it is necessary to invert the phase, and the input signal may be amplified as it is and sent out from the output terminal. If only such a CMOS switch circuit is used, the output selection circuit SFT does not have a signal amplification function, so the gain of the output circuit is set taking this into account.

The effects obtained from the above examples are as follows. That is, [1] A readout signal consisting of a plurality of bits is received, and an output signal is received via an output selection circuit that selectively shifts one bit or a plurality of bits in the positive and/or negative direction according to a predetermined control signal. By switching the output selection circuit, it can be easily configured and at high speed.
The effect is that it is possible to obtain an output signal whose weight has been changed by /2 or ×2.

(2) With +11 above, for image data that displays gradations, weight control can be performed at the same time as serial readout, reducing the burden on image data processing software while improving data processing capacity on the system side. You can get the effect that you can.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the number of bits of the data to be read may be a plurality of bits such as 4 bits, 8 bits, or the like. In addition to the dual-port dynamic RAM that has a random port and a serial port as described above, the image memory also uses a Guinamisoku-type RAM that has only a random port.
It may also be applied to M. That is, an output selection circuit as described above may be added to the output circuit. In this case, for the information read by normal read operation (page mode, column static mode, nibble mode) etc.,
Such weight control is performed. Furthermore, in addition to the dynamic RAM as described above, a static RAM may be used as the basic structure, and an additional circuit as in the above embodiment may be incorporated.

The present invention can be widely used in semiconductor memory devices in which memory access is performed in units of multiple bits.

〔Effect of the invention〕

A brief explanation of the effects obtained by the representative inventions among the two inventions disclosed in this application is as follows. That is, receiving a read signal consisting of multiple bits,
Switching of the output selection circuit is performed by receiving an output signal through an output selection circuit that selectively shifts 7 bits or multiple bits in the positive and/or negative direction and transmitting it to the outside. This makes it possible to obtain output signals with weight changes of x1/2 or x2 at high speed with a simple configuration.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the output selection circuit used in the present invention, Fig. 2 is an operation waveform diagram for explaining an example of its normal output operation (x1), and Fig. 3 is , an operation waveform diagram for explaining an example of the ×2 output operation, FIG. 4 is a circuit diagram showing another embodiment of the output selection circuit used in the present invention, and FIG. FIG. 6 is a circuit diagram showing an embodiment of a clocked inverter circuit to be used. FIG. 6 is a circuit diagram showing an embodiment of a unit selection circuit used in an output selection circuit. dynamic ivy-shaped RAM
FIG. 8 is a block diagram showing one embodiment of the present invention, and a timing chart showing an example of its serial output operation. FIG. 4 is a logic circuit diagram of a cyclic encoder showing another embodiment of the present invention, RAM...memory section, R-ADB...row address buffer sofa, C-ADB...column address buffer sofa, OB・
・Data output circuit, IB...Data input circuit, TC...
Tying control circuit, REFC...refresh control circuit, SW...swift circuit, FF...latch circuit, SR
・・Shift register, SFT・・Output selection circuit, DOB
O~DOB3...Output circuit, CNO-CNI 1...Clocked inverter circuit, N1~N3...CMOS S inverter circuit

Claims (1)

[Claims] 1. An output selection circuit that receives a read signal consisting of a plurality of bits and selectively shifts one or more bits in the positive and/or negative direction according to a control signal, and an output through the output selection circuit. 1. A semiconductor memory device comprising: an output circuit that receives a signal and forms an output signal to be sent to the outside. 2. Claim 1, wherein the semiconductor memory device includes a random input/output port and a serial output port, and the read signal consisting of a plurality of bits is a read signal outputted through the serial output port.
The semiconductor storage device described in 1. 3. The semiconductor memory device according to claim 1 or 2, wherein the read signal consisting of a plurality of bits is binary weighted image data.