JPH0391959A - Photodiode monolithically built in bipolar cmos device - Google Patents

Abstract

PURPOSE:To optimize a photodiode in spectral characteristics without changing a process by a method wherein the photodiode is composed of a cathode layer formed of an N-type diffusion layer and an anode layer formed of a P-type diffusion layer and a P-type buried layer. CONSTITUTION:A photodiode is built integrally in a bipolar CMOS device whose analog characteristics are important. The photodiode has a cathode of a 0.2-0.4mum deep N-type diffused layer formed together with a source/drain layer 28 of an NMOS transistor; and an anode including a 1-1.5mum thick P-type diffused layer 9 which forms the well layer of an NMOS transistor, and a P<+>-type buried layer 6. By this setup, a photodiode, which is sensitive to blue light 400nm or below in wavelength through red light 700nm or above in wavelength, can be obtained without changing a process an monolithically built in a bipolar CMOS device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a photodiode monolithically incorporated into a bipolar CMOS device.

[Conventional technology]

Conventionally, sensors, analog circuits, and
Digital circuit. Regarding a semiconductor device in which electronic circuits such as an actuator drive circuit are integrally formed on the same monolithic substrate, for example, Japanese Patent Application Laid-open No. 106278/1983 discloses a semiconductor device in which electronic circuits such as an actuator drive circuit are integrally formed on the same monolithic substrate. Japanese Patent Publication No. 60-72255. Japanese Patent Publication No. 62-21955
No. 5, etc., disclose bipolar CMOS devices including vertical PNP transistors that can be formed simultaneously without increasing the number of masks by placing emphasis on analog characteristics. In addition, compared to analog characteristics, bipolar NPN transistors with low early voltage and low withstand voltage and high-speed CMOS gates are used to realize high-speed bipolar/CMOS gates.
A bipolar CMOS device in which MOS transistors are monolithically integrated is disclosed in, for example, Japanese Patent Application Laid-Open No. 52-2292.
issue. JP-A-54-46487, JP-A-57-1888
No. 62, etc.

Also, in Japanese Patent Application Laid-open No. 122267/1983, bipolar NP
The base region of the NMOS transistor and the P4 layer of the P''N-photodiode are formed by boron ion implantation, and the source/drain region of the NMOS transistor and the N
A method is shown for forming the emitter of a PN l-transistor as well as the N0 layer of an N''P-photodiode by arsenic ion implantation.

[Problem to be solved by the invention]

Bipolar CMOS devices that have been proposed so far are
■Sonic digital circuit can be replaced with conventional CMOS circuit or ELC
Instead of constructing circuits, the current technology has been limited to replacing them with low power consumption and high speed bipolar CMOS gates, and monolithically integrating digital and analog circuits.

However, in recent years, there has been a demand for ultra-small, high-speed, high-precision photo-sensing components, and there is a demand for monolithic photo-sensors and high-precision digital/analog circuits. That is, as shown in FIG. 10 (8), a photodiode array 101 consisting of one photodiode or a large number of photodiodes is connected to an analog circuit 102 such as a MOS input type high-precision operational amplifier or an analog filter, and a CPU or actuator. When used in connection with a bipolar CMOS device 104 consisting of a high-speed digital circuit 103 constituting an interface with a computer, noise easily enters and the influence of noise becomes large. Therefore, as shown in Figure 10), the photodiode or photodiode array 1
There is a need to integrate 01 into the above-mentioned bipolar CMOS device to reduce noise.

In devices constructed in this way, it is necessary to increase the precision of analog and digital circuits, so it is possible to integrate optimized photodiodes without degrading the original performance of bipolar or CMOS devices. It is necessary to create a However, there have been no proposals yet that take this point into consideration, and even with the method disclosed in Japanese Patent Application Laid-Open No. 122267/1983, it is not possible to obtain a photodiode with optimal sensitivity and spectral characteristics.

In order to optimize the photodiode, sensitivity, quantum efficiency. It is necessary to consider the spectral characteristics, but in particular, bipolar and C
In MOS devices, it has not been feasible to integrally form optimized photodiodes.

The present invention was made to solve the above-mentioned problems in conventional bipolar/CMOS devices, and is highly sensitive and optimal for being integrated into bipolar/CMOS devices that emphasize analog characteristics without changing the process. The purpose is to provide a photodiode that is

[Means and effects for solving the problem] A normal photodiode needs to be separated from the substrate potential. For this reason p
When a photodiode is integrated into a normal bipolar CMOS device using a type substrate, the photodiode consists of an anode layer made of P-type diffused Na and an n-type diffused layer b, as shown in Figure 1. It is formed using a cathode layer. In FIG. 1, C is a p-type substrate, d is an anode electrode made of AI, and e is a cathode electrode made of AI.

However, as shown in FIG. 2, even if the photodiode is constructed by arranging the anode layer a to be fixed at the substrate potential, for example, as shown in FIG. It can be used with an operational amplifier f as shown in Figure 1). Note that FIG. 3A shows a mode in which the photodiode PD is used in a reverse bias state, and FIG. 3B shows a mode in which it is used in a zero bias state.

The characteristics of the photodiode constructed in this way are indicated by the spectral sensitivity characteristics. In the case of the photodiode shown in FIG. 2, the short wavelength sensitivity depends on the thickness Xj. of the n-type diffusion layer b. The long wavelength sensitivity is determined by the thickness Xjp of the p-type diffusion layer a. That is, as shown in Fig. 4, when the n-type diffusion layer b is made thicker, the spectral sensitivity characteristic decreases in the short wavelength region as shown in ■, and when the p-type diffusion layer a is made thicker, the spectral sensitivity characteristic decreases. As shown in (2), the sensitivity in the long wavelength region increases.

Further, since elements such as vertical NPN transistors and vertical PNP transistors have a plurality of PN junctions in the thickness direction, these junctions can be used as photodiodes. In that case, the spectral characteristics of each junction are different, with the one closer to the surface being sensitive to short wavelengths and the other being sensitive to longer wavelengths. Therefore, by using a single junction or a combination of these junctions, it is possible to provide spectral characteristics depending on the purpose. For example, P
When an NPN structure is formed, three diodes similarly formed in the thickness direction can be used as photodiodes.

In bipolar CMOS devices that place emphasis on analog characteristics, the n-type diffusion layer constituting the cathode layer is a highly doped, thick layer x Shallow layer and deeper thickness of vertical PNP l-transistor
, 20. A paste layer of 4 to 0.7 μm can usually be used. In addition, as the p-type diffusion layer constituting the anode layer, N
A p-type well nodule area can be used to ensure the source/drain breakdown voltage of MOS transistors, and a p-type buried layer can be used to improve the latch-up resistance of NMOS transistors, isolate devices, and reduce the collector resistance of vertical PNP transistors. It is. Furthermore, when constructing a photodiode with an NPN structure or a vertical PNP structure, the source/drain layer of a PMOS transistor, the base diffusion layer of an NPN transistor, the n''l type buried layer, the epitaxial layer, etc. can also be used.

In order to use these diffusion layers in the construction of a photodiode, first of all, regarding the blue sensitivity of the photodiode, if we use the same diffusion layer as the source/drain layer of an NMOS transistor, which is shallower, that is, with a smaller X,
Sensitivity can be provided to light in the near-ultraviolet region of nm or less. In addition, if sensitivity is required for the blue wavelength of 450 nm to 500 nm, a vertical PNP with Xj of 0.4 to 0.7 μm is used.
The base layer of the transistor is optimal.

On the other hand, as a P-type diffusion layer for an anonide layer, 1 to 1.5
By using a .mu.m-thick .rho.-type well layer and a P-type buried layer in an overlapping manner, it is possible to provide sufficient red sensitivity in the region of about 800 rv+.

Furthermore, if sensitivity in the infrared region is required, a PN junction formed by an n-type buried layer and a substrate can be used as a photodiode.

Based on the principles described above, the present invention provides a photodiode that is integrated into a bipolar CMOS device that places emphasis on analog characteristics, and has a diffusion depth of 0.0 that is formed simultaneously with the source and drain layers of an NMOS transistor.
a cathode layer consisting of an n-type diffusion layer of 2 to 0.4 μm;
The thickness of the well layer of the MOS transistor is l~1.
It consists of a 5 μm p-type diffusion layer and an anode layer consisting of a p-type buried layer.

With this structure, a photodiode having blue sensitivity in a wavelength region of 400 nm or less and red sensitivity in a wavelength region of 700 nm or more can be converted into a bipolar C photodiode.
It can be obtained integrally without changing the MOS device and process.

Note that the sensitivity of a photodiode constructed in this manner is about 50 to 70% inferior to that formed by a process dedicated to photodiodes, but in this regard, the present invention can be applied to bipolar CMOS devices. Due to the feature of incorporating a photodiode, by combining this photodiode with, for example, a MOS-T○P operational amplifier, connection can be made with small stray capacitance and low noise, so that low sensitivity can be sufficiently compensated for.

〔Example〕

Prior to describing embodiments, an example of the structure of a bipolar CMOS device with emphasis on analog characteristics will be described with reference to FIG. This configuration example consists of a high-speed CMOS transistor, an NPNI transistor with a high withstand voltage (20 V), a high early voltage (=60 V or more), a high f, and a high withstand voltage (20 V) and high rt (IGHz).
vertical PNP transistor and high Early voltage (χ6
In order to configure each device to have the optimum characteristics as described above, an n-type buried layer 3 is buried on the p-type substrate 1, and the first After forming the n-type epitaxial layer 4a, the second n-type epitaxial layer 4b is laminated using the P'' type buried layer 5 as the collector layer of the vertical PNP transistor. In FIG. 5, 6 is a low concentration p-type buried layer, 7 is a p-type collector electrode section, 8 is an n-type collector electrode section, 9 is a P-type well layer, 10 is an n-type well layer, and l1 is a p-type a channel stopper layer; 12 is a p-type base diffusion layer; l3 is an n-type base diffusion layer; l5 is a gate electrode;
16 is the tip of the vertical PNP transistor, 17 is the collector raising electrode, 18 is the external base of the vertical NPN transistor, 19 is the emitter of the horizontal PNP transistor, 20. 21 is the collector of the horizontal PNP transistor;
22 is the source/drain layer of the PMOS l-transistor, 23 is the emitter of the vertical NPN transistor, 24 is the collector pull-up electrode thereof, 25 is the external base of the vertical PNP transistor, 26 is the N-terminal pull-up electrode, and 27 is the pull-up electrode of the vertical PNP transistor. The external base of the lateral PNP transistor and 28 are the source/drain layers of the NMOS transistor.

This bipolar CMOS device is equipped with many diffusion layers for high performance, and the n-type layers include n'''-type source and drain Ji28 (in order of shallowness of Xj).
x, =0.2 ~ 0.4 μm), n'' type base layer 13 (xJ = 0.4 ~ 0.7 μm), n' type well layer 1
0 (x j = 1.0 to 1.5 p m). Epitaxial layer 71 (x, = 1 to 3 μm), n” type buried layer 3
(xJ=5 to 8 μm), etc. On the other hand, as a p-type layer, a p+-type source/drain layer 22 (xJ=0.2-0.
4μm). p1 type base layer 12 (x==0.4 ~0
．． 7 μm). p'' type well layer 9 (x7=1.
0 to 1. 5 tt m), p” type buried layer 5
, 6 (x; = 3.0 to 5.0 μm), etc. By effectively using these various diffusion layers, it is possible to create a photodiode with desired optimal characteristics.

FIG. 6(9) shows a first embodiment of a photodiode according to the present invention. In this embodiment, the source/drain layer 28 of the NMOS transistor, which is the shallowest among the diffusion layers, is used as the cathode layer, and the P-type well layer 9 and the p-type buried layer 6 are used as the anode layer. In FIG. 6(8), 30 is a cathode electrode, and 3l is an anode electrode.

The spectral characteristics of the photodiode in this example are shown in the sixth section.
(Zuda). In this example, the cathode layer is
Because it uses a shallow diffusion layer with a diameter of 0.2 to 0.4 μm, it has high sensitivity in the short wavelength region. In addition, since the diffusion depth of the p-type well layer 9 is relatively deep at 1.0 to 1.5 μm,
High sensitivity even in long wavelength range.

FIG. 7(8) is a schematic sectional view showing a second embodiment of the present invention. This embodiment is an effective configuration when it is desired to obtain a photodiode having characteristics with reduced sensitivity at short wavelengths. That is, as a cathode layer, the n-type base diffusion layer 13 (x j = 0.4 ~
0. 7 pm). When the n-type base diffusion layer l3 is used as the cathode layer in this way, the sensitivity in the wavelength range of 400 nm or less is considerably reduced, as shown in FIG. 7(8). Note that the sensitivity on the long wavelength side is the first
This is almost the same as the example.

In the first and second embodiments described above, the electrode 31 is provided for the anode layer, but since the anode layer has the same potential as the p-type substrate 1, the positive energy generated by light incidence does not need to be provided. The holes flow into the P-type substrate l. Therefore, it is not necessary to provide three anode electrodes. Further, the photodiodes shown in the first and second embodiments have a limitation in how they can be used because their anode potential is the same as that of the p-type substrate 1.

FIG. 8(2) is a schematic sectional view showing a third embodiment of the present invention. In this example, the bipolar
Using a p-type well layer 9 instead of a base layer in a vertical NPN transistor in a CMOS device
The structure is a photodiode. For the first cathode layer K1, if sensitivity at particularly short wavelengths is required, the source/drain layer 28 of an NMOS transistor is used; otherwise, the n-type base layer l3 of a vertical PNP transistor is used. . Anode layer A
is composed of a P-type well layer 9, and a second cathode layer K2 is formed of epitaxial layers 4a, 4b and an n-type buried layer 3.

The first cathode layer K1 and the anode layer A constitute a first photodiode PDI, and the anode layer A and the second photodiode PDI constitute a first photodiode PDI.
If we consider that the second photodiode PD2 is composed of the cathode layer K2 and the cathode layer K2, as shown in FIG. As a result, the second photodiode PD2 has high sensitivity on the long wavelength side. These two photodiodes PDI PD2 may be used individually, or each of the electrodes 30 . 32 is connected to take out the sum of the photocurrents of the first and second photodiodes PDI and PD2, and a photodiode (PD1+) with sensitivity over a wide wavelength range is obtained.
It can be used as PD2).

In addition, the second photodiode PD2 in this embodiment
uses a diffusion layer located deeper than the photodiodes shown in the first and second embodiments, so it has higher sensitivity in the long wavelength range than the photodiodes shown in the first and second embodiments. characteristics are obtained.

In addition, as a photodiode with an NPN structure, a normal NPN
It can also be constructed using a PN transistor. In this case, since the p-type base layer 12 used as an anode layer has a shallow diffusion depth g of 0.4 to 0.7 μm, a photodiode consisting of an n-type source/drain layer 28 and a p-type base N12 is formed. is sensitive only to a narrow wavelength range of short wavelengths, and the p-type base layer 12 and the epitaxial layer 4a,
4b and the n-type buried layer 3 has sensitivity from relatively short wavelengths to long wavelengths. The two photodiodes obtained with this configuration can also be used individually or in combination.

FIG. 9(8) is a schematic sectional view showing a fourth embodiment of the present invention. In this example, the bipolar
A photodiode is constructed using a vertical PNP structure (PNPN structure) of a vertical PNP transistor in a CMOS device.

In this example, P is used as the first anode layer At.
The source/drain layer 22 of the MOS transistor, the epitaxial layer 4b as the first cathode layer K1, the p-type buried layer 5 as the second anode layer A2, and the second cathode layer K
2, an n-type buried layer 3 is used. The first photodiode PD1 is the first anode layer At and the first cathode layer Kl, the second photodiode PD2 is the first cathode layer K1 and the second anode layer A2, and the third photodiode PD3 is the second anode NA2. and a second cathode layer K2. Note 30. 32 is the first and second
Cathode electrode, 31. 33 are first and second anode electrodes.

In this case, as shown in FIG. 9 (Bl), the first photodiode PDI, second photodiode PD2, and third photodiode PD3 have higher sensitivity in the short wavelength range in this order.Three photodiodes configured in this way photodiode PDI
, PD2, and PD3 can be used alone or in combination of two or three to obtain spectral sensitivity characteristics depending on the purpose.

In addition, the photodiode using the vertical PNP structure in this example may be formed by forming the first anode layer AI with a p-type base layer l2 as shown in FIG. 9, or by using the structure of a normal vertical PNP transistor. This can also be realized by forming the first cathode layer K1 from the n-type base layer l3 and an epitaxial layer. 3 obtained with that configuration
Spectral characteristics suitable for the purpose can be obtained using individual photodiodes or in combination.

Note that in both the photodiodes shown in the third and fourth embodiments, the second cathode layer K2 and the p-type base #5
．． A parasitic diode is added between 1 and 1. This substrate parasitic diode can also be used as a photodiode if no problem occurs in the circuit structure of the next stage, and in this case, a photodiode with improved sensitivity in the infrared region can be obtained.

(Effects of the Invention) As explained above based on the embodiments, by constructing a photodiode according to the present invention in a bipolar CMOS device that emphasizes analog characteristics, the spectral characteristics can be optimized without changing the process. A photodiode with such characteristics can be easily obtained, and a photodiode with such characteristics can be easily monolithically integrated with an analog circuit such as a high-precision operational amplifier and a digital circuit constituting an interface with a CPU.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the general structure of a photodiode incorporated into a bipolar CMOS device, and FIG. 2 is a diagram showing the basic configuration of a photodiode according to the present invention incorporated into a bipolar CMOS device. , 3rd
Figure 8, field) shows the use of the photodiode shown in Figure 2.
FIG. 4 is a diagram showing changes in spectral sensitivity characteristics depending on the thickness of the diffusion layer constituting the photodiode shown in FIG. 2, and FIG. FIG. 6 (8) is a schematic cross-sectional view showing the first embodiment of the photodiode according to the present invention, and FIG. FIG. 7 (8) is a diagram showing the sensitivity characteristics, and FIG. 7 (8) is a schematic cross-sectional view showing the second embodiment. FIG. The schematic cross-sectional view shown in FIG. 8(B) is a diagram showing the spectral sensitivity characteristics,
FIG. 9 (8) is a schematic cross-sectional view showing the fourth embodiment, FIG. 9 (B) is a diagram showing its spectral sensitivity characteristics, and FIG. 10 (8)
．． (B) is a diagram illustrating a coexistence mode of photodiodes, analog circuits, and digital circuits. In the figure, l is a substrate, 3 is an n-type buried layer, 4a is a first epitaxial layer, 4b is a second epitaxial layer, 5 is a high concentration p-type buried layer, 6 is a low concentration p-type buried layer, 8 is an n-type collector electrode part, 9 is a p-type well layer, 10 is an n-type well layer,
12 is a P-type base diffusion layer, 13 is an N-type base diffusion layer, 2
2 is the source/drain layer of the PMOS l-transistor;
28 indicates the source/drain layer of the NMOS transistor.

Claims (1)

[Claims] 1. In a photodiode integrated into a bipolar/CMOS device with emphasis on analog characteristics, the same thickness as the source/drain layer of the NMOS transistor of the bipolar/CMOS device is 0.2 to 0. ．．
A cathode layer consisting of a 4 μm n-type diffusion layer and a NM
The same thickness as the p-type well layer of the OS transistor is 1.0~
A photodiode integrated with a bipolar CMOS device, comprising an anode layer consisting of a 1.5 μm p-type diffusion layer and a 3-5 μm thick p-type buried layer. 2. In a photodiode that is integrated into a bipolar/CMOS device that emphasizes analog characteristics, an n-type diffusion layer with a thickness of 0.4 to 0.7 μm, which is the same thickness as the base layer of the vertical PNP transistor of the bipolar/CMOS device, is used. a cathode layer consisting of a layer of bipolar C
It is composed of an anode layer consisting of a p-type diffused layer with a thickness of 1.0 to 1.5 μm, which is the same as the p-type well layer of an NMOS transistor in a MOS device, and a p-type buried layer with a thickness of 3 to 5 μm. A photodiode integrated with a bipolar CMOS device featuring: 3. In a photodiode that is integrated into a bipolar/CMOS device that emphasizes analog characteristics, a plurality of photodiodes are formed using a plurality of PN junctions of the bipolar/CMOS device, and each photodiode is used singly or in combination. A photodiode integrated with a bipolar CMOS device, characterized in that the photodiode is configured to be used in a bipolar CMOS device. 4. A first cathode layer consisting of an n-type diffusion layer that is the same as the source/drain layer of the NMOS transistor of the bipolar CMOS device or an n-type diffusion layer that is the same as the base layer of the vertical PNP transistor, and a p-type well of the NMOS transistor as well. A first photodiode formed of an anode layer made of the same p-type diffusion layer as the layer, and a second photodiode formed of the anode layer and a second cathode layer made of an n-type epitaxial layer and an n-type buried layer. The bipolar CMO according to claim 3, characterized in that the bipolar CMO is configured with a diode.
Photodiode integrated with S device. 5. A first anode layer consisting of the same p-type diffusion layer as the source/drain layer of the PMOS transistor of the bipolar CMOS device, and consisting of the same n-type diffusion layer and n-type epitaxial layer as the base layer of the vertical PNP transistor, or A first photodiode formed of a first cathode layer made of only an n-type epitaxial layer, and a second photodiode formed of the first cathode layer and a second anode layer made of a p-type buried layer; the second anode layer and n
Claim 3 characterized in that the second cathode layer is formed of a mold-buried layer and the third photodiode is formed of the second cathode layer.
A photodiode integrated with the bipolar CMOS device described. 6. The photodiode according to any one of claims 3 to 5, characterized in that the photodiode is constituted by a parasitic diode formed between the n-type buried layer and the p-type substrate of the bipolar CMOS device. Photodiode integrated with bipolar/CMOS device.