JPH0388490A - Processor module for picture processor - Google Patents

Abstract

PURPOSE:To decrease the number of processor modules by connecting a specific arithmetic processing means using an exclusive hardware in deputy for an arithmetic processing such as filter processing or cosine transformation requiring much time in the software processing by the processor to the processor. CONSTITUTION:A specific arithmetic processing means 14 provided with an exclusive hardware in deputy for an arithmetic processing such as filter processing or cosine transformation is connected to a processor 15. Then the filter processing or cosine transformation requiring much time by the processor is implemented in deputy by the specific arithmetic processing means 14. Thus, the throughput per unit processor 15 is improved and the number of required processor modules 7 is saved and the cost is reduced due to the reduction in the scale of the hardware.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a processor module for an image processing device used in an image processing device such as a high-efficiency image encoding processing device used in a video conference system, etc. It is.

[Conventional technology]

FIG. 5 is a block diagram showing, for example, a conventional processor module for an image processing apparatus, which is shown in the 1988 Institute of Electronics, Information and Communication Engineers Technical Research Report Vol. 1.88fk488 DSP88-54. In the figure, 1 is a processor module for this image processing device, 2 is an input image data bus through which input image data to this processor module 1 is transmitted, and 3 is a reference signal that is fed back to the processor module 1. a feedback image data bus through which image data is transmitted; 4 is an output image data bus through which output image data outputted from the processor module 1 to the next stage and reference image data fed back to its own stage are transmitted; be.

A processor 10 is located in the processor module 1 and executes arithmetic processing such as motion compensation, vector quantization, filter processing, and cosine transformation in an software manner, and encodes or decodes image data. 11 is a reference image data memory that temporarily stores reference image data fed back from the feedback image data bus 3 to the shift processor 10; 112 is an input image data node 2;
This is an input image data memory that temporarily stores input image data input to the processor 10 from the processor 10. Reference numeral 13 denotes an output pin 7a for temporarily accumulating output image data to be outputted from the processor 10 to the output image data bus 4.

FIG. 6 is a block diagram showing an example of an image encoding processing device configured with the processor module 1 in two stages. In the figure, 31 is a feedback image data node that transmits the reference image data of each processor module 1 of the first stage, and 445.32 is a feedback image data node that transmits the reference image data of each processor module 1 of the second stage. It's a bus. 5 is encoding,
In order to process decoding, 6 is a host processor that controls the processor modules of each stage.
This is the control signal node to be transmitted to.

Next, the operation will be explained. The input image data supplied from the input image data node 2 is divided into blocks into a predetermined number of blocks under the control of the host processor 5.
The signal is input to each processor module 1 of the first stage, and the first stage encoding process is performed. That is, the first
Each processor module 1 of the stage stores the reference image data of the corresponding block fed back via the feedback image data bus 31 in the reference image data memory 11, and stores the reference image data of the corresponding block from the input image data bus 2. When the input image data of the block to be processed is received, it is first stored in the input image data memory 12.

Next, the processor 10 in each processor module 1 of the first stage reads the input image data and the reference image data from the input image data memory 12 and the reference image data memory 11, and encodes the allocated block. is executed by software. Each processor 1
0 temporarily stores the processing result in the output buffer 13 and outputs it to the output image data bus 31 as the output image data of the first stage. When reference image data of the previous frame beyond the range of screen division is required for processing such as motion compensation, it is sent to each processor in the first stage via the feedback image data bus 31 under the control of the host processor 5. The reference image data is transferred between the modules 1.

The feedback image data bus 31 of the first stage also functions as the input image data bus of the second stage.
l The input image data supplied from this feedback image data bus 31 is input to each processor module 1 of the second stage in each block divided into screens under the control of the host processor 5. Below, the first
As in the case of a stage, the encoding process of each block of the stage is performed by the processor 1 of each processor module 1.
The encoding result of the second stage is output to the output image data bus 4 via the output buffer 13. In this case too, processor module 1
If mutual transfer of reference image data is necessary, the reference image data is transferred using the second stage feedback image data bus 32.

[Problem to be solved by the invention]

Conventional processor modules for image processing devices are configured as described above, so the load is distributed and the processor 1
In order to compensate for the processing speed of 0, it is necessary to have a multi-processor configuration with multiple stages of processor modules 1 connected in parallel, which requires a large number of processor modules 1 and increases the hardware cost. Hardware and software configurations are also becoming more complex.
There were issues such as the inability to respond flexibly to changes in encoding and decoding methods.

This invention was made to solve the above-mentioned problems. It reduces the number of processor modules, reduces hardware costs, and provides image processing that allows easy changes in encoding and decoding methods. The purpose is to obtain a processor module for a device.

[Means to solve the problem]

A processor module for an image processing device according to the present invention connects to the processor a specific arithmetic processing means that performs arithmetic processing such as filter processing or cosine transformation on behalf of the processor using dedicated hardware, which takes time when software processing by the processor is performed. This is what I did.

[Effect]

In the flow of encoding or decoding processing, when the processor in this invention executes processing that requires a large amount of calculations using a large amount of data, such as filter processing or cosine transformation, the processor uses its own software processing. By not performing that processing, but by having the dedicated hardware of the connected specific arithmetic processing means perform the processing,
To realize a processor module for an image processing device that is low cost and can flexibly respond to changes in encoding and decoding methods.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 2 is an input image data bus, 3 is a feedback image data bus, 4 is an output image data bus, 11 is a reference image data memory, 12 is an input image data memory,
Reference numeral 13 denotes an output buffer 7, which is the same or equivalent to the conventional one denoted by the same reference numeral in FIG. 5, so detailed explanation will be omitted.

Further, 14 is a specific arithmetic processing means that includes dedicated hardware for filter processing and performs high-speed arithmetic processing of filter processing using the dedicated hardware, and is constituted by, for example, a large-scale integrated circuit. 15 is a processor that differs from the conventional processor 10 in that this specific arithmetic processing means 14 is connected and the specific arithmetic processing means 14 performs the filtering process, which takes a lot of processing time in software processing. . 1 is a processor module that differs from the conventional processor module 1 in that it is equipped with these specific arithmetic processing means 14 and a processor 15.

FIG. 2 is a block diagram showing an example of an image encoding processing device configured in a single stage in the processor module 1. In the figure, 2 is an input image data bus, 3 is a feedback image data bus, 4 is an output image data bus, 5 is a host processor, 6 is a control signal bus, and T is a processor module. 6
It is the same or equivalent part to the one with the same reference numeral in the figure.

Next, the operation will be explained. Input image data supplied from the input image data bus 2 is input to each processor module 7 for each block obtained by dividing the screen into a predetermined number of blocks under the control of the host processor 5, and is subjected to encoding processing. Here, FIG. 3 shows an example of screen division of one screen's worth of input image data when encoding processing is performed by three processor modules 7 as shown in FIG. 2. The host processor 5 encodes the input image data divided into blocks #1 to #3 in this way.
Each processor module 7 is caused to execute the processing.

That is, each processor module 7 stores the reference image data of the corresponding block fed back through the feedback image data bus 3 into the reference image data memory 1.
When the input image data of the corresponding block is received from the input image data bus 2, it is stored in the input image data memory 12. Next, the processor 15 in each processor module T reads the input image data and the reference image data from the input image data memory 12 and the reference image data memory 11, and executes the encoding process of the allocated block. At this time, processing such as motion compensation and vector quantization is processed by the processor 15 itself using software, and when performing filter processing that uses a large amount of data and requires a large amount of calculations, the processing is performed by specific calculation processing. The means 14 is used instead.

The specific arithmetic processing means 14 receives the pixel data from the processor 15, performs arithmetic processing on it at high speed using dedicated hardware for filter processing, and returns the arithmetic results to the processor 15.

When a series of encoding processes is completed in this way, each processor 15 temporarily stores the processing results in the output buffer 13 and outputs them to the output image data bus 4 as output image data. When reference image data of the previous frame beyond the range of both image divisions is required for processing such as motion compensation, the host processor 5 mediates the operations between each processor module 7 and uses the feedback image data bus. The reference image data is transferred between the respective processor modules T via 3.

In addition, in the above embodiment, the specific calculation processing means 14 includes dedicated hardware for filter processing,
Although the explanation has been given using an encoding processing algorithm centered on vector quantization as an example, it is also possible to use a coding processing algorithm centered on cosine transformation by using a device equipped with dedicated hardware for cosine transform calculation as the specific calculation processing means 14. May be applied.

Further, in the above embodiment, a case has been described in which the feedback image data bus 3 is coupled to the output image data bus 4, but as shown in FIG. 4, the feedback image data bus 3 is separated from the output image data bus 4. A structure similar to that of the above embodiment may also be used, and the same effects as in the above embodiment can be achieved.

〔Effect of the invention〕

As described above, according to the present invention, a specific arithmetic processing means equipped with dedicated hardware for filter processing or cosine transformation is connected to a processor, and the filter processing or cosine transformation, which takes time in software processing by the processor, is performed. Since the configuration is configured so that the conversion processing is performed on behalf of the unit processor, the processing capacity of each unit processor can be improved, and the number of required processor modules can be reduced, which reduces costs by reducing the hardware scale. This has the effect of providing a processor module for an image processing apparatus that can flexibly respond to changes in encoding and decoding methods by simplifying the hardware, software, and software configurations.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a processor module for an image processing device according to an embodiment of this invention, and FIGS.
The figure is a block diagram showing an example of an image encoding processing device using the same, FIG. 3 is an explanatory diagram showing an example of screen division of input image data for one screen, and FIG. 5 is a conventional processor module for an image processing device. FIG. 6 is a block diagram showing an example of an image encoding processing device using the same. rh processor module, 14 is specific arithmetic processing means;
15 is a processor. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a processor module for an image processing device that includes a processor therein and encodes and decodes image data, the processor module is connected to the processor and performs the filter processing or cosine transformation calculation processing that takes time in software processing by the processor; A processor module for an image processing apparatus, characterized in that a specific arithmetic processing means is provided that is executed using dedicated hardware in place of the processor.