JPH0385633A - Divisional arithmetic circuit - Google Patents

Abstract

PURPOSE:To execute display precise arithmetic operation through simple configuration by obtaining the quotient by converting a divisor into a reciprocal and multiplying a dividend by it, and simultaneously, executing the arithmetic operation by bit-shifting the divisor and the dividend according to the absolute value of the divisor. CONSTITUTION:The table of the reciprocal of input data is formed previously in one area of a ROM 5, and simultaneously, the table of the reciprocal of the data obtained by bit-shifting the input data is formed previously in another area. The absolute value of divisor data from a RAM 1 is discriminated by an ALU 3, and when this absolute value is larger than a prescribed value, the divisor data is shifted by prescribed number of bits, and is converted by using other area of the ROM 5. Simultaneously with this, this converted data and the data obtained by shifting the dividend data from the RAM 1 by prescribed number of bits are multiplied by a multiplier 7, and the quotient is obtained. Thus, the highly precise divisional arithmetic operation can be executed through the simple configuration.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a division arithmetic circuit used for address calculation, etc., in an image processing device, for example.

[Summary of the invention]

The present invention relates to a division arithmetic circuit, which obtains a quotient by converting the divisor into a reciprocal and multiplying it by the dividend, and also performs a simple operation by bit-shifting the divisor and dividend according to the absolute value of the divisor. The configuration allows highly accurate calculations to be performed.

[Conventional technology]

Conventionally, circuits that perform division operations have been: ■ Performed by software using ALU etc. ■ Use a table that calculates the quotient for all combinations of the divisor and dividend ■ Calculate the dividend and reciprocal using a table that calculates the reciprocal of the divisor Measures such as multiplication are being considered.

[Problem to be solved by the invention]

However, in such a circuit, the computation time becomes extremely long in case 2, and the memory size of the table becomes enormous in case 2.

On the other hand, with ■, the calculation time and memory size are appropriate, but as the absolute value of the divisor increases, the value of its reciprocal decreases, so the accuracy of the calculation decreases significantly when the absolute value of the divisor is large. There was a problem.

In view of these points, this application is intended to perform highly accurate division operations with a simple configuration.

[Means to solve the problem]

The present invention provides a first memory IJ (RAM
(1) ”), ALU (3), a second memory for storing coefficients (ROM (5)), a multiplier (7) that can select the upper and lower digits of the output, and a control device (CPU (100)).
), in the second memory, a table of reciprocals of input data is formed in one area, and a table of reciprocals of data obtained by shifting the manual data by a predetermined bit is formed in another area, and The absolute value of the divisor data from the first memory is determined by the ALU, and when this absolute value is less than or equal to a predetermined value, the divisor data is converted using one area of the second memory, and the converted data is and the dividend data from the first memory are multiplied by the multiplier, and when the absolute value is greater than or equal to a predetermined value, the divisor data is shifted by a predetermined bit and converted using another area of the second memory. and the converted data and data obtained by shifting the dividend data from the first memory by a predetermined bit are multiplied by the multiplier to obtain a quotient.

[Effect]

According to this, a table for converting a divisor into a reciprocal is divided, and when the absolute value of the divisor data is greater than or equal to a predetermined value, the divisor data is shifted by a predetermined bit for conversion, and the dividend data is also shifted by a predetermined bit for calculation. By doing
High-precision division operations can be performed with a simple configuration.

〔Example〕

FIG. 1 shows the hardware configuration. In this figure (
100) is a CPU serving as a control device, and this C
The P U (100) and each part constituting the processing circuit are interconnected through a pass line (101).

And (1) is R, which is the first memory for data storage.
AM, and this RAM (1) is a pass line (1
01) Processing data and processing result data are input and output to and from the CPU (100), and address and read/write control signals are sent to the CPU (100).
(100). This RAM (1)
The data from A L U (
3), and this ALU (3) is supplied to the CPU
(100) is driven by a control signal from.

The data from this ALU (3) is stored in the register (4).
ROM serves as a second memory for coefficient storage through
(5) As well as being supplied to address manpower, ALU
(3) MSB of data from CPU (100)
data from the CPU (100) is supplied to R
Applied to the MSB of the address input of OM (5).

Data from this ROM (5) is supplied through a register (6) to a multiplier (7) that can select the upper and lower digits of the output. Furthermore, data from A L U (3) is supplied to a multiplier (7) through a register (8). The output from this multiplier (7) is the CPU (100)
The upper and lower digits are selected by the control signal from , and this output data is sent to RAM (1) through register (9).
supplied to

Note that registers (2) (4) (6) (8) (9)
are each driven by a clock enable signal from the CPU (100).

Furthermore, FIG. 2 is a diagram for explaining the processing means of the calculation, and in this figure, the contents of address q (dividend) are divided by the contents of address p (divisor) of RAM (1), and the quotient is transferred to address r. p (1=r).

In this example, the data for each numerical value is 16 bits, soto (15 bits of numerical value and sign 1 bit) (MSB)), and R
Assume that the address input of OM (5) is 11 bits (2K addresses) and the data of each address is 16 bits. In this case, each address of ROM (5) has n
(Q<n ball 1023”) address, (n +0.5)
-' However, when n=0, '0111111111111111
``Also at address m (1024 2m ball 2047) ((m
-1024+0.5) X 2 ) However, when m=1024, a table of '0111111111111111' is formed.

Further, as a preliminary preparation, the memory at address 0 of ALU (3) stores a numerical value of 1024'''' in advance.

When the process starts in the figure, the first step [1] is to supply the address p from the CPU (100) to the RAM (1) and hold the output data at this time in the register (2). . Further step [2
] When the next clock is supplied, the data in the register (2) is stored in the memory at address 1 of the ALU (3), and its MSB is output to the CPU (100). By this, the CPU determines the sign of the divisor, and here the MSBI
When t111, the divisor is negative, and when MSB-"0", the divisor is non-negative.

If MSB="0" in this step [2], then in step [38] the content of the memory at address 0 is subtracted from the content of memory at address 1 of ALU (3), and the resulting MSB is c.
Output to P U (100). Also step [2
], when MSB="l", AL in step [3B]
Adds the contents of the memory at address 0 to the contents of memory at address 0 of U (3) and outputs the MSB of the result to CPU (100). As a result, the CPU (100) determines whether the absolute value of the divisor is large or small.

In other words, when MSB="0" in STEP [38], the absolute value of the divisor is the predetermined value ("1") stored in the memory at address 0.
024″′), and when MSB="1", it is smaller than the predetermined value. Also, in step [3B], MSB="
1”, the absolute value of the divisor is set to the specified value, MS
When B-"0", it is smaller than the predetermined value.

Then, when MSB="0" in step [3A], the contents of memory at address 1 of ALU (3) are shifted down by 5 bits in step [4A], and the contents of memory at address 1 are shifted down in step [5A]. Hold in register (4).

Furthermore, in step [6A], CPU (100) is '1
” data, and in step [7A], ROM (5
) is held in register (6).

On the other hand, when the MSB is "1" in step [3B], A L is sent in step [4B] as in step [4A].
The contents of the memory at address 1 in U (3) are shifted down by 5 bits, and in step [5B] the contents of memory at address 1 are subtracted from 0'' and held in register (4).Furthermore, (
C in this step [6B] as well as step [68]
P U (100) outputs data 11111, and step 7B outputs the same data as step 78 (this RO
The output data of M (5) is held in the register (6).

On the other hand, when the MSB is "1" in step [38], the ALU is directly transferred to step [5C] in the same way as step [5A].
The contents of memory at address 1 in (3) are held in register (4). Furthermore, in step [6C] CPU (100)
outputs “0” data, and in step [7C] RO
The output data of M(5) is held in register (6).

Also, when MSB="O"' in step [3B], the ALU
The contents of memory at address 1 in (3) are subtracted from "0"' and held in register (4). Furthermore, in step [6D], CPU (100) is 0 as in step [6C].
" data is output, and in step [7D] it is stored in the ROM (5
) is held in register (6).

Then, in steps [8A] to [8D], RAM (1)
Supply the address of address q to , and store the output data in the register (
2). And in step [2] MSB゛0”
At step C9A) (9C:], the data in register (2) is ALU by supplying the next clock.
(3) Store in memory at address 2. Also step [2]
When the MSB is “1”, step [9B] [:90]
When the next clock is supplied, data 0 in register (2) is subtracted from "o" and stored in memory at address 2 of ALU (3).

Furthermore, when MSB=“0″′ in step [3A] and MSB=“1” in step [3B], step [10]
At step [11], the contents of the memory at address 2 of ALU (3) are shifted down by 4 bits, and at step [11], the contents of memory at address 2 are held in register (8). On the other hand, if MSB = "1" in step [38] and MSB - "0" in step [3B], A is directly determined in step [11].
Register (8) the contents of memory at address 2 of L U (3)
to hold.

Then, in step [12], the data in register (6) and the data in register (8) are multiplied by the multiplier (7), and the upper and lower digits are selected by the control signal from c p u (100), and the data in register ( 9). Further step [13
] supplies address r and a write control signal to RAM (1) and stores the data in register (9) at address r of RAM (1).

That is, in this circuit, the value of the divisor p is 132768
2 When p<-1024, q'-(-) 6 (truncated) p'=(-)p (truncated) 2 Reciprocal: ((p'+0.5) x 2 )1024<
When p < 0, q'-(-1)q p'-(-1) p Reciprocal: (p'+0.5) When 0≦p<1024, q'-q p'-p Reciprocal: (p' +0.5) When 1024≦p<32768, q'-()q 6 (truncated) p'=()p (truncated) 2 Reciprocal: ((p'+0.5) x 2 ) as q'×
The quotient r is determined by (reciprocal).

Note that in this case, adding 0.5 when calculating the reciprocal number corresponds to rounding off. In addition, the accuracy of calculation is improved by calculating the reciprocal with a double value in a range where the absolute value is large.

Furthermore, for the above-mentioned purpose, the divisor and the dividend can be operated on either integers or real numbers, respectively.

In that case, when the divisor and dividend are both integers or real numbers, the calculation is performed considering the integers,
In step [12], the lower digits of the output data are selected (rounding is not possible).

On the other hand, when the divisor is an integer and the dividend is a real number, the calculation is performed as is, and in step [12], the upper digit of the output data is selected (rounding is possible).

Note that this circuit is applied when (absolute value of dividend) < (absolute value of divisor).

In this way, according to the above-mentioned circuit, the table for converting the divisor into the reciprocal is divided, and when the absolute value of the divisor data is greater than or equal to a predetermined value, the divisor data is shifted by a predetermined bit to perform the conversion, and the dividend data is also converted into a predetermined one. By performing operations with bit shifting, highly accurate division operations can be performed with a simple configuration.

Note that the above-mentioned ROM (5) may be configured with a RAM to store the reciprocal table before calculation processing.

〔Effect of the invention〕

According to this invention, a table for converting a divisor into a reciprocal is divided, and when the absolute value of the divisor data is greater than or equal to a predetermined value, the divisor data is shifted by a predetermined bit for conversion, and the dividend data is also shifted by a predetermined bit. By performing this calculation, it became possible to perform highly accurate division calculations with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of the hardware of a division arithmetic circuit according to the present invention, and FIG. 2 is a diagram for explaining the processing procedure of the arithmetic operation. (1) is RAM, (2) (4) (6) (8
) (9) is a register, (3) is an ALU, (5) is an RO
M, (7) is a multiplier, and (100) is a CPU. 4 (101) is a pass line.

Claims (1)

[Claims] The second memory includes a first memory for storing data, an ALU, a second memory for storing coefficients, a multiplier that can select upper and lower digits of the output, and a control device. A table of reciprocals of input data is formed in one area, and a table of reciprocals of data obtained by shifting the input data by a predetermined bit is formed in the other area, and the absolute value of the divisor data from the first memory is Above AL
When the absolute value is less than or equal to a predetermined value, the divisor data is converted using one area of the second memory, and this converted data and the dividend data from the first memory are When the absolute value is greater than or equal to a predetermined value, the divisor data is shifted by a predetermined bit and converted using another area of the second memory, and this converted data and the first memory are converted. A division arithmetic circuit configured to obtain a quotient by multiplying the dividend data by the data obtained by shifting the dividend data by a predetermined bit in the multiplier.