JPH0383150A - Control system for cache device with address converting mechanism - Google Patents

Abstract

PURPOSE:To resolve a synonym problem in a single CPU by introducing an inverse TLB besides a TLB, a TAG, and cache data and using a logical cache which does not require address conversion at the time of cache hit. CONSTITUTION:Such control is performed that a physical address corresponding to the logical address of a cache block registered in a TAG 2 is certainly registered in an inverse TLB 3. When a system bus is monitored to find that the physical address transmitted to a main device hits the inverse TLB 3, the TAG 2 is accessed by the corresponding logical address as the output of the inverse TLB 3, and the operation to secure the consistency of the cache is performed in the case of hit. Thus, the logical cache is used to resolve a synonym problem, and the snoop function is realized.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Fig. 9) Means for Solving the Problems to be Solved by the Invention (Fig. 1) Working Examples (Fig. 2) - Figure 8) Effects of the invention [Summary] The purpose of this invention is to solve the synonym problem by using a control method logical cache of a cache device with an address translation mechanism, and also to realize a snob function. In a cache device with an address translation mechanism that performs buffering, a TLB, an inverse TLB, and a
AG, the contents of the given logical address bus, and the result of converting the logical address to a physical address, and further inverse T.
A comparator is provided to compare the contents of the internal logical address bus reversely converted by the LB, and the physical address of the cache block registered in the TAG is controlled so that it is always registered in the reverse TLB, and If the physical address on the bus hits the inverted TLB, the TAG is accessed using the output of the inverted TLB, and if the TAG is hit, an operation is executed to ensure cache coherence.

[Industrial application field]

The present invention relates to a control method for a cache device with an address translation mechanism, and more specifically, it is used in a data processing device, and in particular, it uses a logical cache as a cache to solve the synonym problem and also realize a snob function. This invention relates to a control method for a cache device with an address translation mechanism.

[Conventional technology]

FIG. 9 is an explanatory diagram of a conventional example, in which (a) is an explanatory diagram of address conversion, and (b) is an explanatory diagram of a parallel access method using a physical cache.

Traditionally, to maintain cache coherency when multiple logical addresses may be translated into one physical address,
More high-performance systems that use a physical cache (searching the cache using physical addresses) use a parallel access method that simultaneously accesses the TLB RAM and the cache's TAGRAM (the part that stores addresses, etc.). .

(B) As shown in the figure, bits 0 to 1 of the logical address are an offset (an address within a page, the same as a physical address), and this part is not converted when converting to a physical address.

Therefore, only the remaining 12 to 31 bits of logical page addresses are converted into physical page addresses.

(b) In the figure, TLBLA (logical address part of TI, B) is drawn using the 12th to 16th bits of the logical address, and the output of the result and the 1st bit of the logical address are drawn.
Compare the 7 to 31 bit addresses and check the TLB hit based on the comparison result.

Also, T in the 12-16 bit logical address
Subtract LBPA (physical address part of TLB), compare the output physical address with the physical address subtracted from TAG using the address (physical address) of the 4th to 11th pins of the logical address, and use this comparison result and the above TLB.
If both of the results of the comparison result in one loss, the result is a hit.

Then, the output of TLBPA and the logical address 0 to 11
Converts a bit address to a physical address.

In this way, the logical address is generally used to
The parallel access method described above has improved this point, which required a two-step RAM drawing operation: drawing B, converting it to a physical address, and using this physical address to draw the cache. This results in a high-performance system.

As described above, in order to access the TLB and TAG simultaneously in the physical cache, the address portion for accessing the TAGRAM needs to be a bit that is not subject to address translation.

For example, if one page of address translation is 4KB and both the logical address and physical address are 32 bits, Figure 9 (
As in (b), the offset (address within the page) of the lower 12 degrees of focus is not subject to address translation (it remains a physical address).

The fact that the address is 12 bits means that the cache capacity is only allowed up to 4KB (=page size).

Therefore, the set associativity is increased to 4 ways or 16 ways, but there is a limit due to the problems of high speed and complexity of control.

Even if it is 16 ways, 4KB x 16 = 64KB.

On the other hand, those with larger main memory capacities range from 100MB to several GB. In such a case, it is necessary to increase the cache capacity, and the logical cache capacity is 100K.
Canches of several MB from B are no longer rare.

[Problem to be solved by the invention]

The above-mentioned conventional devices had the following drawbacks.

(1) A large capacity logical cache can be used, but it is difficult to increase the capacity of a physical cache.

(2) Physical cache takes longer to search than logical cache.

In other words, in the logical cache, as long as the cache is hinted, there is no need to use the address translation result (even if accessed in parallel), but in the physical cache, it is not necessary to use the address translation result (TLB Did you give a hint to)? It needs to be added to the il logic and becomes a critical bus.

(3) In a logical cache, multiple logical addresses are
When converted into two physical addresses, it is difficult to identify that they are the same data.

This is called the synonym problem.

Also, since the physical address is on the system bus,
This is because it is not possible to monitor the address and change the state of the cache block.

It is an object of the present invention to overcome such conventional drawbacks, to solve the synonym problem using a logical cache, and to also realize a snob function.

[Means to solve the problem]

FIG. 1 is a diagram of the principle of the present invention, where 1 is the TLB and 2 is the TA.
G, 3 is an inverse TLB, 4 is a data section, 5 is an l unit, and 6 is a bus interface.

In the present invention, in order to solve the problem of cache capacity,
TLBI, TA are used to solve the synonym problem of the logical cache and to realize the snob function.
In addition to G2 and cache data 4, a reverse TLB3 is introduced.

This inverse TLB 3 stores translation pairs from physical addresses to logical addresses, and in order to solve the synonym problem, blocks with logical addresses that are translated to the same physical address in the cache are always Control so that there is only one.

For this purpose, a comparator 5 is provided to compare the given logical address and the logical address obtained by inversely converting the result of converting the logical address into a physical address using an inverse TLB.

Furthermore, in order to prevent errors in the reverse TLB 3 from becoming a problem, control is performed to ensure that when a block registered in the cache is searched for the reverse TLB 3 using the physical address of the block, a hit occurs.

[Effect]

Since the present invention is configured as described above, the physical address corresponding to the logical address of the cache block registered in the TAG is controlled so that it is always registered in the reverse TLB, and the system bus is monitored and the real address is controlled. When the physical address transmitted within the device hints to the reverse TLB, the TAG is accessed using the corresponding logical address that is the output of the reverse TLB, and when the TAG is hit, the cache coherency is guaranteed. This is what we do.

Therefore, the synonym problem can be solved using a logical cache, and the snob function can also be realized.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 2 is a block diagram of one embodiment of the present invention, where 1 is a TLB, 2 is a TAG, 3 is a reverse TLB, 4 is a data section, and 5 is a block diagram of an embodiment of the present invention.
1 is a comparator, 6 is a bus interface, 100 is a main memory, 101-103 are CPUs, 104-106 are address translator cache devices, and 107 is a bus.

Note that the configuration within CPUI 01 is the same for other CPUs, and the main memory I7100 is commonly used by many CPUs.

Cache devices 104 to 106 with address translation mechanisms provided in each CPUI 01 to 103 are connected to an upper level bus and a system bus.

The upper bus includes a logical address bus, an upper data bus,
The system bus includes the above-mentioned control signal bus, and the system bus includes a physical address bus, a lower data bus, and a lower control bus. A TLB (address translation buffer) 1 is connected to the logical address bus and the physical address bus, and is connected to the logical address bus. A finite number of address translation pairs to physical addresses are stored.

When given a logical address, this TLB 1 searches to see if a physical address corresponding to the logical address is registered, outputs the search results, and if the search runs out, it searches for the corresponding physical address. Outputs the address to the physical address bus.

The inverse TLB (reverse address translation buffer) 3 is connected to the physical address bus and the internal logical address bus, and stores a finite number of inverse translation pairs from physical addresses to logical addresses.

When the inverse TLB 3 is given a physical address, it searches to see if a logical address corresponding to the physical address is registered, outputs the search results, and if the search is exhausted, it searches for the corresponding logical address. output to the internal logical address bus.

TAG2 is connected to the logical address bus and the internal logical address bus, stores the logical address of the block registered in the cache, checks whether the address of the logical address bus or the internal address bus is registered in the cache, Output the result.

The data section 4 is a data storage section of the cache, and is connected to a logical pulse bus, an upper data bus, and a lower data bus.

The comparator 5 compares the contents of the given logical address bus with the contents of the internal logical address bus obtained by inversely converting the result of the logical address conversion using the inverse TLB.

The system bus interface 6 interfaces access requests from the cache device with an address translation mechanism to the system bus, and also transmits predetermined types of accesses on the system bus into the device.

In the above configuration, the snoop function can be implemented as follows.

Each of the CPUs 104 to 106 uses a bus 107 that is commonly used.
is monitored, and when a write is made to the main memory 100, the physical address on the bus 107 is taken in.

The captured physical address is sent from the bus interface 6 to the inverse TLB 3 and converted into a logical address.

Look at TAG2 with the converted logical address and see if the same address exists (whether it is a logical address in your own cache).

As a result, if there is a cache hit, that is, the same logical address, that logical address is invalidated.

Also, to solve the synonym problem, do the following:

That is, in the cache, the number of blocks having logical addresses that are translated into the same physical address may be controlled to be limited to one at any time.

Therefore, in the comparator 5, the given logical address and the result of converting the logical address into a physical address are
Furthermore, it is compared with the logical address translated by inverse TLB3.

As a result, if the two do not match, the reverse TLB is executed again.
TAG2 is subtracted using the logical address from 3, and if it is a hit, it is determined that there is a synonym problem, and in other cases, it is determined that it is normal and processing is performed.

This will be explained in detail below.

First, in the case of reading, control is performed as follows.

(11 When a logical address is given from outside, TLBl
Then, among the logical addresses, the RAM is read using the lower N bits of the page address as an address.

At the same time, in TAG2 and data 4, among the logical addresses,
The RAM is read using the lower L pinto of the logical page address and the upper M bits of the intra-page offset.

Reading data 4 may be performed after reading TLB 1 and TAG 2. If high speed is not required,
TLB 1 may be subtracted after it is known that the cache has missed.

(2) When TLBI misses, the address translation table on the main memory 100 is searched and the translation pair is transferred to TLB.
, and re-execute from (1) above.

(3) If TLBI is hit, check for cache miss.

If the cache is hinted, the data read from the data section 4 using the lower bits of the logical address is returned to the data bus and the process ends.

(4) If there is a miss hint in the cache, inverted T
If LB3 is searched and reverse TLB3 is missed, proceed to (6) below.

(5) When the inverse TLB 3 is hinted, the comparator 5 compares the internal logical address output from the inverse TLB 3 with the original logical address.

As a result, if the two match, it is treated as a normal state, but if they do not match, TAG2 is subtracted once again using the logical address from reverse TLB 3.

If there is no hint in TAG2, it is processed as normal, and if there is a hint, it is determined that there is a synonym problem.

If this synonym problem occurs, invalidate the corresponding synonym block (in store-back caches, it may be necessary to transfer the synonym block to the main memory 100), then proceed to (6) below. .

(6) Using the physical address obtained in (1) above, transfer the block from the main memory 100 to the cache and register it in the cache.

(7) Furthermore, the physical address to logical address conversion pair of the block is registered in the inverse TLB3.

Here, several methods can be considered for registration in the reverse TLB 3.

B1 For example, each entry of the inverse TLB3 is made to correspond to each entry of TAG2. In this case, we define the inverse transform pair as the old inverse T
It is sufficient to overwrite the LB entry.

First, remove the old entry from reverse TLB3 by some method.

For example, if the inverse TLB 3 is a direct address from a physical address, the entry that is directly addressed from a part of the physical address will be the target of eviction.

Furthermore, if the inverse TLB 3 is fully associative using the FIFO method, the oldest registered entry will be the target of eviction.

Regarding the entry to be evicted, if a block within one logical page indicated by the logical address is registered in the cache (in general, there are a plurality of blocks), it is evicted from the cache.

In this embodiment, since a one-way store method is assumed, it is sufficient to invalidate the cache using the logical page as a key.

In this way, it is possible to guarantee that blocks registered in the cache are always set in the reverse TLB3.

For lights it looks like this:

(1) Read TLBLA and TLBPA in TLBl simultaneously.

<z) 'Check rt, ss, TLB 1
If there is a mistake, register in TLBI based on the address translation table in main memory 100, and perform (1) above.
Rerun from.

(3) Data is written to the main memory 100 using the physical address of the TLBI output, and the following processing can be performed in parallel with writing to the main memory 100.

(4) Check for a cache miss, and if it is a cache miss, apply the physical address of the TLBI output to the inverse TLB3 and proceed to the next step.

If the cache is hinted, data is written to data 4 using the given logical address and the process ends.

(5) If the inverse TLB 3 is hit, the comparator 5 compares the internal logical address output from the inverse TLB 3 with the original logical address.

As a result, if the two match, it is treated as a normal state, but if they do not match, TAG2 is subtracted once again using the logical address from reverse TLB 3.

If there is no hint in TAG2, it is processed as normal, and if it is a hit, it is determined that there is a synonym problem, and the processing is performed in the same way as when reading.

Next, data is written into the data section 4 using the logical address output from the inverse TLB 3. Furthermore, if there is a mishint in the reverse TLB, the data section 4 is left as is and the process ends.

Next, we will explain the operation when there is a write on the system bus.

(1) Reverse TLB at the physical address on the system bus
Search for 3.

(2) If there is a miss in reverse TLB3, the process ends without doing anything (because if there is a miss in reverse TLB3, it is guaranteed that the data of that physical page is not registered in the cache).

(3) If the inverse TLB3 is hit, search TAG2 using the logical address of the output of the inverse TLB3.

(If there is a miss on 41TAG2, the process ends without doing anything.

(5) If you hint at TAG 2, invalidate that cashoche bronc.

TLB 1, reverse T'LB3, TAG in the above embodiment
2. Data 4 will be explained in more detail as follows.

TLBI is separated from TLBLA (logical address part of TLB) and TLBPA (physical address part of TLB), and also for reverse TLB3, respectively.
It consists of BLA and reverse TLBPA.

Figure 3 shows an example of the configuration of TLBLA, where 1-1 is a comparator,
1-2 indicates a decoder.

This example is a configuration example when the page size is 4 KB (the minimum unit of address translation), and has a direct matrix configuration of 256 entries.

Normally, bits 19 to 12 (8 bits) of the logical address are supplied to the RAM decoder 1-2, and the read 1
Comparator 1-1 compares the 2 bits with bits 31 to 20 (12 pins) of the logical address.

V (Valid) which also indicates the validity of the entry
The bit is also read, and when the focus is 0, a TLB miss is output regardless of the comparison result of the comparator 1-1.

At the time of registration, bits 31-20 of the logical address are written to the entry specified by bits 19-12 of the logical address, and 1 is written to the V bit.

FIG. 4 is a diagram showing an example of the configuration of TLBPA, and 1-
3 indicates a decoder.

Similarly to TLBLA, TLBPA also provides bits 19 to 12 (8 bits) of the logical address to the RAM decoder 1-3.

The output of the RAM is 20 bits, which is output to the upper 20 bits of the physical address bus.

The lower 12 bits of the physical address bus output the same value as the contents of the lower 12 bits of the logical address bus. T.L.B.
When registering to , the upper 20 bits of the physical address bus are written to the entry specified by pins 19 to 12 of the logical address.

FIG. 5 is a diagram showing an example of the configuration of TAG, and 2-1.
2-2 shows a comparator.

Cache Direct Mabutsu, 1 block 16 bytes, 16 entries, capacity 256MB, TAGRA
M has 2 boats.

What draws one port of TAGRAM are bits 17 to 4 (14 bits) of the logical address, and the output is the 14-bit registered address and the V bit.

When registering to TAG, bits 17 to 4 of the logical address
Bits 31 to 31 of the logical address are added to the entry specified by
Write 18 (14 pinto) and V=1, TAGRAM
Bits 17 to 4 of the internal logical address draw another 1 vote, and the contents of the TAG are similarly compared with the above 14 bits of the internal logical address.

It also has a function of setting the V bit of the TAG entry corresponding to the logical page specified by the upper 20 pins of the internal logical address bus to 0.

FIG. 6 is a diagram showing an example of the configuration of DATA.

The data portion of the cache is accessed by bits 17 to 4 (14 bits) of the logical address, similar to the TAG.

Of the 16 bytes of the selected entry (block), only the bytes determined by the lower 4 bits of the logical address and the access size are accessed.

At the time of reading, the accessed data is read to the upper data bus.

There are two types of writes: I is a write to the cache when a cache hit occurs, and the other is a write for registering data transferred from the main memory in the cache when a cache miss occurs.

FIG. 7 shows a configuration example of an inverse TLBPA, where 3-1 shows a comparator and 3-2 shows a decoder.

The reverse TLB has a configuration in which the logical address and physical address of the TLB are reversed. In this example, a direct computer configuration with 256 entries is used.

Normally, bits 19 to 12 of the physical address are supplied to the RAM decoder 3-2, and the read 12 bits are
The physical address pinpoints 31 to 20 are compared with the comparator 3-1.

At the same time, V (Valid
) bit is also read, and when the V bit is O, a reverse TLB miss is output regardless of the comparison result.

At the time of registration, bits 31 to 20 of the physical address are written to the entry specified by bits 19 to 12 of the physical address, and 1 is written to the V bit.

FIG. 8 is a diagram showing an example of the configuration of a reverse TLBLA.
-3 indicates a decoder.

Similar to reverse TLBPA, reverse TLBLA also transfers bits 19 to 12 (8 bits) of the physical address to the RAM decoder 3.
-Give to 3.

The output of the RAM is 20 bits, which is output to the upper 20 bits of the internal logical address bus.

The lower 12 bits of the logical address bus output the same value as the contents of the lower 12 bits of the physical address bus.

When registering to the reverse TLB, bits 19 to 19 of the physical address
Write the upper 20 bits of the physical address bus to the entry specified by 12.

Although the above embodiment has been described using a store-through method, the present invention is not limited to this method, but can be similarly applied to various store-back parallel cache methods.

Further, the present invention can be similarly applied to both multiprocessors and single processors.

Furthermore, the cache device may have each entry in the reverse TLB for each entry in the TAG. The data in the page indicated by the previously stored logical address may be evicted from the cache.

〔Effect of the invention〕

As explained above, the present invention has the following effects.

(1) A logical cache that does not require address translation at cache time can be used to solve the synonym problem within a single CPU.

(2) Supports snoop function for multiprocessors,
It can also solve the synonym problem between multiple processors.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of the control system of the Kish device with an address translation mechanism according to the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, and Fig. 3 is a TL
Figure 4 shows an example of the configuration of BLA, Figure 4 shows an example of the configuration of TLBPA, Figure 5 shows an example of the configuration of TAG, Figure 6 shows an example of the configuration of DATA, Figure 7 shows an example of the configuration of DATA. The figure is reverse TL
FIG. 8 is a diagram showing a configuration example of a BLA, FIG. 8 is a diagram showing a configuration example of a reverse TLBPA, and FIG. 9 is an explanatory diagram of a conventional example. Yato・-TLB 2-・TAG3-・-inverted T
LB 4-Data

Claims (1)

[Scope of Claims] In a control method for a cache device with an address translation mechanism that performs address translation and buffering, a TLB (TLB) connected to a logical address bus and a physical address bus and storing address translation pairs from logical addresses to physical addresses. 1)
and connected to the physical address bus and internal logical address bus,
It is connected to an inverse TLB (3) that stores inverse translation pairs from physical addresses to logical addresses, a logical address bus, and an internal logical address bus,
The TAG (2) that stores the logical address of the block registered in the logical cache, the contents of the given logical address bus, and the result of converting the logical address into a physical address are further inverted by the inverse TLB (3). A comparator (5) is provided to compare the contents of the converted internal logical address bus, and control is performed so that the physical address of the cache block registered in the TAG (2) is always registered in the inverse TLB (3). And, if the external bus is monitored and the physical address on the bus hits the reverse TLB (3), the inverse TLB (3) is checked.
Access TAG(2) with the output of 3), and
1. A control method for a cache device with an address translation mechanism, characterized in that if there is a hit, an operation is executed to guarantee cache coherence.