JPH0379035A - Mos transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain an inexpensive semiconductor layer with improved crystal and restrict kink phenomena by forming a diffusion layer with a higher impurity concentration near a drain region than that of a semiconductor layer and by biasing a substrate through the diffusion layer. CONSTITUTION:A diffusion layer 11 with a higher impurity concentration than that of a semiconductor layer is formed near a drain region 10 and a substrate is biased through the diffusion layer. For example, an electrode material for biasing source/substrate 13 which is grounded through a contact hole 12 is placed and a drain electrode material 15 where a positive voltage is applied to through a contact hole 14 is placed. Also, a positive voltage is applied to a polysilicon film 5a which becomes a gate electrode, thus obtaining an inexpensive semiconductor layer with improved crystal and restricting kink phenomena.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a MOS transistor formed on an insulating layer, and in particular to a MOS transistor that can suppress the kink phenomenon.
This relates to OS transistors.

[Prior Art] A technique for preventing the kink phenomenon of a MOS transistor formed on an insulating layer is disclosed in, for example, Japanese Patent Laid-Open No. 60-24126.
This is shown in Publication No. 6. This is to efficiently eliminate the holes generated in the active layer that cause the kink phenomenon.
Two new electrodes (areas) through which majority carriers (holes) in the active layer can pass are provided.

[Problems to be solved by the invention] However, the semiconductor layer (active layer) is formed by SIMOX, and although it is possible to make the semiconductor aC active layer thinner, it is not possible to obtain better crystals, and there are many ion implantation holes, which increases the cost. was inviting. Furthermore, the SIMOX technology itself is unfinished.

An object of the present invention is to provide a MOS transistor in which an inexpensive and well-crystalline semiconductor layer can be obtained and a kink phenomenon can be suppressed.

[Means for Solving the Problems] A first invention provides a MOS transistor provided in a semiconductor layer on an insulating layer formed by a wafer direct bonding method, in which a MOS transistor is provided near a drain region than the semiconductor layer. The gist is a MOS transistor in which a highly impurity-containing diffusion layer is formed and a substrate bias is applied through the diffusion layer.

The second invention is to attach the first layer to the insulating layer by a wafer direct bonding method.
After forming a conductive type semiconductor layer and forming a gate oxide film on the semiconductor layer, a gate electrode material is placed in the gate formation region on the gate oxide film, and at the edge of the drain formation region. The second to place the gate electrode material
a second conductivity type source/drain region is formed using the gate electrode material as a mask, and a first conductivity type high impurity substrate bias diffusion region for obtaining a substrate bias is formed. MOS consisting of 3 steps
The gist of this article is a method for manufacturing a transistor.

[Function] In the first invention, a diffusion layer having an impurity concentration higher than that of the semiconductor layer is formed near the drain region, and a substrate bias is applied through the diffusion layer.

In the second invention, a semiconductor layer of the first conductivity type is formed on the insulating layer by a wafer direct bonding method in the first step, and a gate oxide film is formed on the semiconductor layer in the second step. A gate electrode material is disposed in the gate formation region on the oxide film, and a gate electrode material is disposed at the edge of the drain formation region. Then, in the third step, a second conductivity type source/drain region is formed using the gate electrode material as a mask, and a first conductivity type high impurity concentration substrate bias diffusion region for taking a substrate bias is formed. Ru. As a result, MOS1 to transistor of the first invention are manufactured.

[Example 1] An example embodying the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view of the MOS transistor of this embodiment, and FIG. 2 is a sectional view taken along line A-Δ in FIG.

Further, the manufacturing process is shown in FIGS. 3 to 11.

First, as shown in FIG. 3, the surface of an N-type single crystal silicon substrate 1 having a predetermined thickness is mirror polished. on the other hand,
As shown in FIG. 4, the surface of an N-type single crystal silicon substrate 2 is mirror-polished, and a thermal oxide film 3 as an insulating film is formed on the surface.

Then, as shown in FIG. 5, the mirror surface of the silicon substrate 1 and the mirror surface of the silicon substrate 2 are bonded together.
Heat treatment is performed for 1 hour at 0° C. under N2 atmosphere. The surface of the silicon substrate 1 is roughly polished until the thickness of the silicon substrate 1 is 1 to 6 μm. As a result, a semiconductor layer (silicon substrate 1) is formed on the thermal oxide film 3 by the wafer direct bonding method.
is placed.

Next, as shown in FIG. 6, the silicon substrate 1 is formed into a predetermined shape, and a thermal oxide film 4 is further formed on the surface of the silicon substrate 1. Then, boron is implanted into the silicon substrate 1 and heat treated (1170°C).

under N2 atmosphere for 5 hours) to make the silicon substrate 1 P type.

Subsequently, as shown in FIG. 7, a polysilicon film 5 serving as a gate electrode material is placed over the entire surface of the silicon substrate 1.degree. Further, as shown in FIGS. 8 and 1, unnecessary areas of the polysilicon film 5 are removed to form a ring. That is, a polysilicon film 5a is placed in the gate formation region, and a polysilicon film 5b is placed at the edge of the drain formation region to provide a substrate bias. Furthermore, a thermal oxide film 6 is formed on the surface of the polysilicon film 5.

Then, as shown in FIG. 9, a resist is placed on the silicon substrate 1°2 except for the source/drain formation regions.
P (phosphorus) ions are implanted. After roughly removing the resist 7, as shown in FIG.
A resist 8 is placed in the upper source/drain formation region, and boron ions are implanted. Thereafter, as shown in FIG. 11, heat treatment (1000° C., 30 minutes) is performed to
, P+ for drain region 10 and substrate bias
A diffusion region 11 is formed.

As shown in FIG. 2, source/substrate bias electrode material 13 is grounded through contact hole 12.
At the same time, a drain electrode material 15 to which a positive voltage is applied via the contact hole 14 is also arranged. or,
A positive voltage is applied to the polysilicon 1Ba5a serving as the gate electrode.

The MOS transistor manufactured in this way has a source
The bottoms of the drain regions 9 and 10 do not reach the thermal oxide film 3, and the bonding surface of the PN junction between the train region 10 and the silicon substrate 1 is wide, making it easy for holes to be generated in the active layer, which may cause the kink phenomenon. Become.

In addition, holes generated at the PN junction between the drain region 40 and the silicon substrate 1 are annihilated by moving through the silicon substrate 1 and reaching the P+ diffusion region 11, but if the resistance of the silicon substrate 1 is large, the holes is difficult to move and is likely to accumulate on the silicon substrate 1, leading to the occurrence of kink. Therefore, the P+ diffusion region 1 is placed in contact with the drain region 10.
1 leads to a decrease in the drain breakdown voltage of the MOS transistor.

Therefore, using the polysilicon film 5 as the gate electrode material, the source/drain regions 9 and 10 are formed in the Selfa line, and the drain region 10 is formed in the Selfa line.
By forming the P+ diffusion region 11 in the vicinity of the drain region 10 throughout the periphery, the drain breakdown voltage is prevented from decreasing and the resistance from the hole generation point to the P diffusion region 11 is made as low as possible.

As described above, in this embodiment, the M
In the OS transistor, a P+ diffusion region 11 having an impurity concentration higher than that of the silicon substrate 1 (active layer) is formed near the drain region 10, and a substrate bias is applied through the P+ diffusion region 11. As a result, JP-A-60-
In the device shown in Publication No. 241266, the semiconductor layer (active B) is formed by SIMOX, and although the semiconductor layer (active layer) can be made thinner, better crystals cannot be obtained, and the amount of ion implantation is large, increasing costs. However, in this embodiment, since a wafer direct bonding method is used without relying on SIMOX, a good crystalline semiconductor layer (active layer) can be obtained, and costs can be reduced. Roughly speaking, since the P diffusion region 11 for obtaining a substrate bias is formed near the drain region 10, the drain breakdown voltage is prevented from decreasing and the resistance from the hole generation point to the P+ diffusion region 11 is made as low as possible. Kink phenomenon can be suppressed.

Furthermore, its manufacturing is carried out by thermal oxidation using wafer direct bonding method.
After forming a semiconductor layer of the first conductivity type (P type) on the semiconductor layer 113 (insulating layer) and forming a thermal oxide film 4 (gate oxide film) on the semiconductor layer, A polysilicon film 5a (gate electrode material) is placed in the gate formation region, and a polysilicon film 5a (gate electrode material) is placed at the edge of the drain formation region.
b (gate electrode material) (second step), and use the polysilicon films 5a and 5b as masks to form an N-type source electrode! of.

In-regions 9 and 10 were formed, and a P type P+ diffusion region 11 (substrate bias diffusion region) with a high impurity concentration for obtaining a substrate bias was also formed (third step). As a result, it is possible to extremely easily arrange the P+ diffusion region 11 for providing a substrate bias near the train region 10 in the self-alignment.

Note that this invention is not limited to the above embodiments,
For example, as shown in FIGS. 12 and 13 (cross section B-8 in FIG. 12), the drain region 10 does not have to be completely surrounded by the P+ diffusion region 11.

Further, in addition to the N-channel MOS transistor, a P-channel MOS transistor may be used.

Furthermore, in addition to polysilicon gate MOS transistors, silicide gate MOS transistors have been implemented, and a diffusion layer with an impurity concentration of 8 degrees higher than that of the semiconductor layer is formed near the drain region 10 using a silicide gate electrode material to create a substrate bias. You can also take it.

[Effects of the Invention] As detailed above, according to the present invention, it is inexpensive and
It exhibits an excellent effect of being able to obtain a semiconductor layer with good crystallinity and suppressing the kink phenomenon.

[Brief explanation of drawings]

Figure 1 is a plan view of the MOS transistor of the example, Figure 2 is a sectional view taken along line AA in Figure 1, Figure 3 is a sectional view for explaining the manufacturing process, and Figure 4 is for explaining the manufacturing process. 5 is a sectional view for explaining the manufacturing process, FIG. 6 is a sectional view for explaining the manufacturing process, FIG. 7 is a sectional view for explaining the manufacturing process, and FIG. 8 is a sectional view for explaining the manufacturing process. is a sectional view for explaining the manufacturing process, FIG. 9 is a sectional view for explaining the manufacturing process, FIG. 10 is a sectional view for explaining the manufacturing process,
1 is a sectional view for explaining the manufacturing process, FIG. 12 is a plan view of another example of a MOS transistor, and FIG. 13 is a sectional view taken along the line B--B in FIG. 12. 3 is a thermal oxide film as an insulating layer, 4 is a thermal oxide film as a gate oxide film, 5a is a polysilicon film as a gate electrode material, 5b is a polysilicon film as a gate electrode material,
9 is a source region, 10 is a drain region, and 11 is a P+ diffusion region as a substrate bias diffusion region.

Claims (1)

[Claims] 1. In a MOS transistor provided in a semiconductor layer on an insulating layer formed by a wafer direct bonding method, a diffusion layer having a higher impurity concentration than the semiconductor layer is formed near the drain region. , a MOS transistor that takes a substrate bias through its diffusion layer. 2. A first step of forming a first conductivity type semiconductor layer on the insulating layer by a wafer direct bonding method, and after forming a gate oxide film on the semiconductor layer, a gate is formed in the gate formation region on the gate oxide film. A second step of arranging the electrode material and arranging the gate electrode material at the edge of the drain formation region, forming a second conductivity type source/drain region using the gate electrode material as a mask, and taking a substrate bias. a third step of forming a highly impurity-concentrated substrate bias diffusion region of the first conductivity type.