JPH0374725A - Information processor - Google Patents

Abstract

PURPOSE:To detect at a high speed a case where an overlap process is not required and to improve the performance of an MVC instruction by providing an overlap detecting circuit which detects the overlap between a memory operand and a memory area in the different methods. CONSTITUTION:One or plural 1st detecting circuits the discordance of one or plural bits whose source and destination addresses are previously decided. Meanwhile one or plural 2nd detecting circuits detects the coincidence of one or plural bits set previously. One or plural 3rd detecting circuits detects whether a bit whose source or destination address is previously decided is equal to 0 or 1. Then a deciding circuit decides a case where the correct result is obtained despite the shift carried out for each word at execution of a data shift instruction (MVC instruction) which shifts the operand data on a memory with the outputs of the 1st-3rd detecting circuits. These detecting circuits and deciding circuit form a high speed overlap detecting circuit 6. Thus it is possible to detect at a high speed an overlap state that breaks an operand and to improve the cost performance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to an information processing device that executes a data movement instruction (hereinafter referred to as an MVC instruction) to move operand data on a memory. .

[Conventional technology]

The MVC instruction uses the source address as the source address of the memory, and the destination address as the destination address.
Generally, the destination address is an instruction that can specify the length of the operand data to be moved, and usually from the source operand data area (hereinafter referred to as source operand) to the destination operand data (
It is required to move the operand data one byte at a time from the left or right to the destination operand (hereinafter referred to as destination operand).

Generally, data is read and written to and from a memory or cache memory in an information processing device in units of words of a fixed length, such as 4 bytes or 8 bytes.

Therefore, when executing an MVC instruction, data is not moved one byte at a time, but in food units such as 4 bytes or 8 bytes. This also improves the execution performance of MVC instructions compared to moving bytes one byte at a time.

Now, when moving an MVC instruction word by word, a problem occurs if the second Oherand and the destination operand overlap destructively. Destructive duplication is when the destination address is included in the source operand, and if there is destructive duplication, the result may be different between moving byte by byte and moving by word. Put it away.

Therefore, in the case of such duplication, it is necessary to change the method of executing the MVC instruction so that it is executed by moving byte by byte instead of by word. For this purpose, it is necessary to detect destructive duplication of operands, and conventionally, as disclosed in Japanese Patent Application Laid-Open No. 61-26134 and Japanese Patent Application Laid-open No. 61-216031, the source address, destination address and the length of the source operand, and then it is checked whether the following condition holds true: source address ≦ destination address ≦ (source address + source operand length).

[Problem to be solved by the invention]

However, in the conventional destructive duplication detection method described above, in order to detect destructive duplication, it is first necessary that the source address, destination address, and source operand length are equal. length calculation, source address ≦ destination address, destination address < (source address tenth overland length), or (destination address - source address) calculation, (destination address - source address) )<The source operand length must be compared.

Therefore, detecting destructive duplications takes a considerable amount of time and
For this reason, even when there is no destructive duplication, data movement begins after detecting that there is no destructive duplication, so even if data is moved in units of words, it is difficult to improve performance. .

[Means to solve the problem]

Therefore, in order to detect operand destructive duplication at high speed, the information processing apparatus of the present invention uses one or more predetermined bits for detecting a mismatch between one or more predetermined bits of the source address and the destination address. Like the first detection circuit, one predetermined one, or like the first detection circuit, one predetermined one,
or a number of second detection circuits and one or more third detection circuits for detecting whether a predetermined bit of the source address or destination address is 0 or 1;
a first detection circuit; Second. Based on the output of the third detection circuit, there is provided a high-speed duplication detection circuit including a determination circuit that determines whether the result is correct even if the movement is performed in units of words at least when executing an MVC instruction.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a duplication detection section of an information processing apparatus according to an embodiment of the present invention. 1 and 2.3 are the source address register, destination address register, and source operand length register, all of which are as follows.
The value is set by the instruction decoder. 6 is a high-speed duplication detection circuit according to the present invention, which outputs a duplicate processing unnecessary signal to the signal line 101 indicating that it is okay to execute the MVC instruction at least in word-by-word processing; e 7 is from the destination address; This is a subtraction circuit that subtracts the source address, and the result is set in the difference register 4. When the source operand length is greater than 16 bytes, the magnitude comparison circuit 8 outputs 1 when the value of the difference register 4 is less than 16, and when the source operand length is less than 16 bytes, it outputs 1.
Outputs 1 when the value of difference register 4 is smaller than the source operand length. 5 is a flip-flop (FF), which holds the output of the magnitude comparison circuit 8 for one machine cycle;
The output is output to the signal line 102 as a duplicate processing request signal.

Next, with reference to FIG. 2, a method of processing MVC instructions in units of words when there is no destructive duplication in this embodiment will be described.

In Figure 2, the source address is 8n+7, the source operand length is 16 bytes, and the destination address is 8m+.
1 is a diagram showing the state of operands on memory in the case of 1; FIG. In the information processing device of this embodiment, data is exchanged with the memory using 8 bytes as one word, so the source operand is read in units of 8 bytes three times.
W.I.

RW2. It is divided into three parts of RW3 and read out.

On the other hand, the destination operand is also written in 8-byte units three times, WWI, WW2, and WW3.
It is written in two parts.

One way to process MVC instructions is to read all the source operands and then write them to the destination address, but that would require too much hardware to store the read operand data, so we decided not to implement this method. In the example, reading and writing are performed almost in parallel.

In FIG. 2, to perform the first write WWl, RW
Data for WWl must be created from I and RW'2. Therefore, the source operand must be read at least twice before the first write.

Depending on the relationship between the source address and destination address, the first write data may be ready in one read, but for the sake of ease of control, if all source operands cannot be read in one read, The source operand is always read twice in succession, then writes and reads are repeated alternately, and when the source operand has been read, further writes are performed until the destination operand has been written. Process as follows.

Now, if the above processing method is adopted, as shown in Figure 3, even if the operands are destructively duplicated, the current address is 16 times larger than the source address.
If it is larger than a byte, word processing in 8-byte units will yield the same result as processing in 1-byte units.

Therefore, if word-based processing is not allowed, either source operand length > 16 bytes and 1 < (destination address - source address) < 16, or source operand length < 16 bytes and (destination address - source address) <
This is a case where the source operand length condition is satisfied.

The logic for detecting this condition is shown in subtraction circuit 7. in FIG. Difference register 4. Size comparison circuit 8. It is composed of FF5.

Next, the operation of the above logic will be explained with reference to FIG.

FIG. 4 is a time chart showing the operation of the above logic,
The source address and destination address are each set in machine cycle 1.2, and the source operand length is set in machine cycle 3. At the same time, the subtraction circuit 7 calculates (destination address -
source address) is set in the difference register 4. It is during machine cycle 4 that the output of magnitude comparison circuit 8 is set to FF5, and the duplication request signal is determined to be 0 or 1. Therefore, word-by-word or byte-by-byte processing actually starts when
This occurs after machine cycle 4. The above is the configuration and operation of the conventional technology as it is.

Next, the high speed duplication detection circuit 6 in FIG. 1 will be explained with reference to FIG.

FIG. 5 is a circuit diagram of the high speed duplication detection circuit 6.

In FIG. 5, 11 to 50 are comparison circuits,
The source address given via the signal line 103 and the destination address and fixed value given via the signal line 104 are compared. Both the source address and the destination address have 31 bits, and are assigned bit numbers from 1 to 31, respectively.

Now, if we write bit 27 of the source address as 827 degrees, and 7 bits from bits 20 to 26 of the destination address as D20-27, the comparator circuit 11 is a circuit that detects a match between S27 and D27. Comparison circuit 12 is a circuit that detects a mismatch between 820-26 and D20-26.

Further, the comparison circuit 13 is a circuit that detects whether S27 is O or not, and the comparison circuit 17 is a circuit that detects whether or not S27 is O.
This is a circuit that detects whether or not. 61 to 75 are AND gates, and the output of O7 game) 80 and signal line 101 are signals that do not require duplicate processing. The discrepancy between S27 and D27 is S27≠D27, 820-26 and D20-26
If we write the coincidence of 820-26=D20-26, the logic of the high-speed duplication detection circuit in FIG.
6≠D20-26)・(S27=D27)+(320
-26≠D20-26)・(S27=0)・(D27=
1) + (S26 = D26)・(S27=1)・(
D27=O)+(320-25≠D20-25)・(8
26-327=01)・(D26-27=10)+(S
25=D25)・(S26−27=11)・(D26−
27=OO)+(320-24≠D20-24)・(8
25-27=O1l)・(D25-27=100)
+ (324= D24)・(325-27= 111
)・(D25-27=000)+ (S20-23≠D
20-23)・(324-27=0111)・(D24
-27 = 1000) +(S23=D23)・(324-27=1111)・
(D24-27 = 0000) + (320-22≠D
20-22)・(323-27=01111)・(D2
3-27 = 10000) + (822= D22)・(823-27=1111
1)・(D23-27=00000)+(S20-21
=#D20-21)・(322-27=011111)
・(D22-27== 100000)+(S21=D
21)・(S22-27=111111)・(D22-
27=000000)+(320≠D20)・(321
-27=0111111)・(D21-27=100
0000)+(S20=020)・(321-27=1
11111)・(D21-27=000000).

This logic is obtained from the 8 bits of bits 20 to 27 of the source address and destination address, which satisfy the condition 1 ≦ (destination address - source address) (16) when word-based processing is not allowed. This is a negation of the smallest sufficient condition.

Therefore, if the output of the logic shown in FIG. 5 becomes 1, it is guaranteed that at least word-by-word processing can be performed.

Since this logic does not look at the source operand length, the output will not be 1 even if the operands are short and do not overlap.Also, since it looks at only 8 bits of the 31-bit address, the source operand length is 16 bytes. Even if it is larger and the source address and destination address are separated by 16 bytes or more, the output may not be 1, but assuming that the source address and destination address are distributed with equal probability, In 99.2% of all combinations of addresses, the redundant processing unnecessary signal on the signal line 101 becomes 1.

Next, a method for processing MVC instructions in this embodiment will be explained with reference to FIGS. 4 and 6.

FIG. 6 is a flowchart showing the processing of MVC instructions in this embodiment.

Now, in FIG. 4, in machine cycle 1.2, the source address and destination address are respectively set to source address register 1.2. When set in the destination address register 2, the high-speed duplication detection circuit 6 determines whether the duplication processing unnecessary signal is 0 or 1 in machine cycle 2. Further, in machine cycle 3, the source operand length is set in register 3, and as a result, in machine cycle 50, the duplicate processing request signal is determined to be 1 or 0. machine cycle 2
If the redundant processing unnecessary signal is determined to be 1 in , the redundant processing request signal will not become 1 in machine cycle 4, as a matter of course.

Therefore, as shown in FIG. 6, the MVC instruction processing first waits for machine cycle 2, and
If so, test the redundant processing unnecessary signal. If the redundant processing unnecessary signal becomes 1, it immediately starts moving processing in units of words, and if it becomes 0, it waits for machine cycle 4. At machine cycle 4, the duplicate processing request signal is tested, and if it is 0, movement processing is performed in units of words, and if it is 1, movement processing is performed in units of 1 byte.

In this case, 99.2% of the time, word-by-word processing starts in machine cycle 2, and only the remaining 0.8% starts word-by-word or 1-byte processing in machine cycle 4. Compared to the prior art in which processing was started in units of words or units of bytes in cycle 4, the performance of the MC instruction is improved by 1.984 machine cycles on average.

The high-speed duplicate processing detection circuit of this embodiment can be configured with a much smaller number of gates and gate stages than a subtraction circuit or a magnitude comparison circuit, so it is possible to achieve such performance improvement. By increasing or decreasing the bits of the address, it is possible to obtain any precision.

By the way, the comparison bit and accuracy and improved performance are, therefore,
The number of bits to be compared may be determined based on the required performance and the number of gates allocated to the high speed duplication detection circuit.

Furthermore, if the nature of the software to be executed on the information processing device that implements the present invention is known in advance, high-speed duplication can be performed in accordance with the distribution of source addresses and destination addresses of MVC instructions that appear in the software. For example, the logic of the detection circuit is determined by (S20-26≠D2
According to f, if a change is made to use (Sl-27≠Di-27) instead of (Sl-27≠Di-27), it is possible to create an information processing device with even better cost performance.

〔Effect of the invention〕

As explained above, the present invention quickly detects cases where duplicate processing is unnecessary by checking whether the bits in the source address and destination address match, do not match, or are 0 or 1, and determine the execution method of the MVC instruction. Control has the effect of improving the performance of MVC instructions.

In this embodiment, a conventional duplicate detection circuit is also used, but this is not essential; only a high-speed duplicate detection circuit is provided, and if the duplicate processing unnecessary signal does not become 1 in machine cycle 2, the It is also possible to configure the system to start processing in 1-byte units.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a duplication detection section according to an embodiment of the present invention;
Figures 2 and 3 are diagrams showing the arrangement of MVC instruction operands in memory, Figure 4 is a time chart showing the operation of the duplication detection section shown in Figure 1, and Figure 5 is the diagram shown in Figure 1. FIG. 6 is a circuit diagram of the high-speed duplication detection circuit 6, and is a flowchart showing the processing of MVC instructions. l...Source address register, 2...
・Destination address register, 3...
...Source operand length register, 4...Difference register, 5...Flip-flop, 6...
...High-speed duplication detection circuit, 7...Subtraction circuit, 8
......Size comparison circuit, 11-50...Comparison circuit, 61-75...AND gate, 80.
...or gate.

Claims (1)

[Scope of Claims] 1. In an information processing device that executes a data movement instruction to move memory operand data starting from a source address specified by the instruction to a memory area starting from a destination address also specified by the instruction, the source comprising a plurality of duplication detection circuits for detecting in different ways whether or not a memory operand starting from an address overlaps a memory area starting from the destination address, and based on the outputs of the plurality of duplication detection circuits,
An information processing device characterized by controlling an execution method of a data movement command. 2. In an information processing device that executes a data movement instruction that moves memory operand data starting from a source address specified by the instruction to a memory area starting from a destination address also specified by the instruction, the source address and the destination address one or more first detection circuits for detecting a mismatch of one or more predetermined bits; and one or more first detection circuits for detecting a match of one or more predetermined bits. a second detection circuit;
one or more third detection circuits for detecting whether a predetermined bit of the source address or the destination address is 0 or 1; An information processing device comprising a high-speed duplication detection circuit including a determination circuit that controls an execution method of a data movement command based on the output of the detection circuit.