JPH0374534B2 - - Google Patents
Info
- Publication number
- JPH0374534B2 JPH0374534B2 JP57149678A JP14967882A JPH0374534B2 JP H0374534 B2 JPH0374534 B2 JP H0374534B2 JP 57149678 A JP57149678 A JP 57149678A JP 14967882 A JP14967882 A JP 14967882A JP H0374534 B2 JPH0374534 B2 JP H0374534B2
- Authority
- JP
- Japan
- Prior art keywords
- fetq
- fet
- source
- gate
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005669 field effect Effects 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 4
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 2
- 230000005236 sound signal Effects 0.000 description 2
- 108091006146 Channels Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 210000005069 ears Anatomy 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
Landscapes
- Electronic Switches (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は接合型電界効果半導体装置を用いて構
成されるスイツチ回路に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a switch circuit constructed using a junction field effect semiconductor device.
従来例の構成とその問題点
接合型電界効果トランジスタ（以下、Ｊ−
FETと略称する）は、高入力インピーダンスの
回路素子として、増幅器などの信号変換回路の入
力部に広く用いられている。また、Ｊ−FETは
スイツチ回路にも用いられ、Ｊ−FETをスイツ
チ素子として使用したスイツチ回路は、高ダイナ
ミツクレンジ、低歪率、零オフセツトの諸特性を
もち、たとえば、オーデイオ信号の切換えを行な
うためのアナログスイツチとして有望である。Conventional structure and its problems Junction field effect transistor (hereinafter referred to as J-
FET (abbreviated as FET) is a high input impedance circuit element that is widely used in the input section of signal conversion circuits such as amplifiers. J-FETs are also used in switch circuits, and switch circuits that use J-FETs as switch elements have characteristics such as high dynamic range, low distortion, and zero offset. For example, they can be used to switch audio signals. It is promising as an analog switch for
第１図はＪ−FETを用いて構成された従来の
スイツチ回路の典型例である。第１図中、Q1が
スイツチ素子として動作するＪ−FETであり、
そのソース電極１に入力信号源ｅを与え、そのド
レイン電極２の負荷抵抗RLを通じて出力を取り
出すもので、そのゲート電極３には制御信号が加
えられる。なお、抵抗R1はＪ−FETQ1のソー
ス・ゲート間電圧を規定するためのバイアス抵抗
である。第１図示のスイツチ回路で、Ｊ−
FETQ1のゲート電極３をフローテイング状態に
すると、Ｊ−FETQ1のソース電極１とゲート電
極３との間が抵抗R1により零バイアスで結合さ
れ、Ｊ−FETQ1はオン状態になる。逆に、ゲー
ト電極３に所定の制御信号を与えて、抵抗R1の
両端の電圧降下が、Ｊ−FETQ1のピンチオフ電
圧VP以上の電圧になるようにすると、このＪ−
FETQ1はオフ状態になる。このようなＪ−FET
を用いたスイツチ回路は、ダイナミツクレンジが
高く、低歪率、オフセツトがないという優れた機
能を備えている反面、Ｊ−FETをオフに移行さ
せる時のスイツチング速度が高速であると、Ｊ−
FETQ1の電極間容量の変化がスイツチング速度
に追従できないで、抵抗R1を通して、Ｊ−
FETQ1のゲート電極３からソース電極１への電
流が生じ、これが直流変動の雑音として出力側に
現われる。したがつて、たとえばオーデイオ信号
の切換えのためにこのようなスイツチ回路が使用
されると、この雑音がその実装回路におけるシヨ
ツク雑音となつて現われるので耳障りであるとい
う問題点になつている。 FIG. 1 is a typical example of a conventional switch circuit constructed using J-FETs. In Figure 1, Q1 is a J-FET that operates as a switch element,
An input signal source e is applied to the source electrode 1, and an output is taken out through the load resistance R L of the drain electrode 2. A control signal is applied to the gate electrode 3. Note that the resistor R1 is a bias resistor for regulating the source-gate voltage of the J- FETQ1 . In the switch circuit shown in Figure 1, J-
When the gate electrode 3 of the FETQ 1 is placed in a floating state, the source electrode 1 and the gate electrode 3 of the J-FETQ 1 are coupled with zero bias through the resistor R 1 , and the J-FETQ 1 is turned on. Conversely, if a predetermined control signal is applied to the gate electrode 3 so that the voltage drop across the resistor R 1 becomes a voltage higher than the pinch-off voltage V P of the J-FET Q 1 , this J-
FETQ 1 will be in the off state. J-FET like this
Switch circuits using J-FETs have excellent functions such as high dynamic range, low distortion, and no offset, but on the other hand, the high switching speed when turning off the J-FET
The change in the interelectrode capacitance of FETQ 1 cannot follow the switching speed, and through the resistor R 1 , J-
A current is generated from the gate electrode 3 of FETQ 1 to the source electrode 1, and this appears on the output side as DC fluctuation noise. Therefore, when such a switch circuit is used, for example, to switch audio signals, this noise appears as a shock noise in the mounted circuit, causing a problem of being unpleasant to the ears.
発明の目的
本発明は、上述の問題点を解消するスイツチ回
路を提供せんとするものである。OBJECTS OF THE INVENTION The present invention seeks to provide a switch circuit that solves the above-mentioned problems.
発明の構成
本発明は、要約するに、第１のＪ−FETのソ
ース・ドレインを、それぞれ、入出力端子とし、
前記第１のＪ−FETのゲート・ソース間または
ゲート・ドレイン間に第２のＪ−FETのソース、
ドレインを接続するとともに、前記第２のＪ−
FETのソースを前記第２のＪ−FETの基板電極
に接続し、前記第１のＪ−FETのゲートを、抵
抗を介して、接地点に接続した構成のスイツチ回
路である。Configuration of the Invention To summarize, the present invention uses the source and drain of the first J-FET as input and output terminals, respectively, and
a source of a second J-FET between the gate and source of the first J-FET or between the gate and drain;
While connecting the drain, the second J-
This switch circuit has a configuration in which the source of the FET is connected to the substrate electrode of the second J-FET, and the gate of the first J-FET is connected to a ground point via a resistor.
実施例の説明
第２図は本発明のスイツチ回路の構成を第１、
第２の２個のＮチヤンネルＪ−FETQ1，Q2で実
現した実施例である。この回路図中で、端子４は
第１のＪ−FETQ1のゲート端子であり、抵抗R2
はこのＪ−FETQ1をオフにするために、そのゲ
ート端子４と接地点との間に挿入された抵抗であ
り、また、コンデンサＣは両Ｊ−FETQ1，Q2の
互いのゲート電極端子３，４間の容量である。DESCRIPTION OF EMBODIMENTS FIG. 2 shows the configuration of a switch circuit according to the present invention.
This is an embodiment realized by the second two N-channel J-FETs Q 1 and Q 2 . In this circuit diagram, terminal 4 is the gate terminal of the first J-FETQ 1 , and the resistor R 2
is a resistor inserted between the gate terminal 4 and the ground point in order to turn off this J-FETQ 1 , and a capacitor C is connected to the mutual gate electrode terminal of both J-FETQ 1 and Q 2 . The capacity is between 3 and 4.
第２のスイツチ回路で、第１のＪ−FETQ1を
オンにする条件は、第１図の例でも示したよう
に、第２のＪ−FETQ2がオンになつて、第１の
Ｊ−FETQ2のソース電極１とゲート電極４との
間が短絡された状態を保つことである。そこで、
第２のＪ−FETQ2がオンになる最良の状態をみ
ると、それは端子３をフローテイング状態になす
こと、つまり、端子３の制御信号電圧Ｖ＝０にな
して、同ゲートへの電流を零にすることである。
この状態になれば、第２のＪ−FETQ2はそのゲ
ート・ソース間に介在するコンデンサＣによりオ
ンになる。このとき、回路の抵抗R2を第２のＪ
−FETQ2のオン抵抗に比べて十分に大きくなる
ような値に選定することにより、第１のＪ−
FETQ1のゲート・ソース間は電位差のほとんど
ない状態、すなわち短絡状態にすることができ
る。逆に、第１のＪ−FETQ1をオフにするには、
端子３に所定の制御信号電圧Ｖを与えればよい。
この制御信号電圧Ｖは、第１のＪ−FETQ1のピ
ンチオフ電圧VPと、第２のＪ−FETQ2をそのソ
ースと基板とを接続したことによつて形成される
定電圧要素の降伏電圧VZとの和をこえる電圧、
すなわち、｜Ｖ｜＞｜VP＋VZ｜であれば、両Ｊ−
FETQ1，Q2が常に完全にオフになり、出力端子
２側に電圧を発生することはない。ここで、上述
の定電圧要素について詳述すると、第２のＪ−
FETQ2の接続は、第３図にＮチヤネルＪ−FET
の概要構成図で示したように、そのソース電極を
基板電極４ａに結線したものである。第３図示の
Ｊ−FETは、P+型シリコン基板５上にＰ型エピ
タキシヤル成長領域６、Ｎ型チヤネル領域７をそ
れぞれ有し、このＮ型チヤネル領域内にN+型ソ
ース電極領域８ａ、N+型ドレイン電極領域８ｂ
およびP+型ゲート電極領域９ａをそなえた典型
的構造であるから、そのゲート電極端子３ａと基
板電極端子４ａとの間にP+−Ｎ−Ｐ（P+）の縦方
向接合（以下単にPNP接合と略記する）も存在
する。このPNP接合が、すなわち、第２図にお
ける第２のＪ−FETQ2ゲート電極端子３とソー
ス電極端子４（ただし、この端子４は第１のＪ−
FETQ1のゲート電極と回路上では同一である）
との間に介在して定電圧要素となり得るのであ
る。 The conditions for turning on the first J-FETQ 1 in the second switch circuit are as shown in the example of FIG. The purpose is to maintain a short-circuited state between the source electrode 1 and gate electrode 4 of FETQ 2 . Therefore,
Looking at the best condition for turning on the second J-FETQ 2 , it is to put terminal 3 in a floating state, that is, to set the control signal voltage of terminal 3 to V = 0, and to reduce the current to the gate. The goal is to make it zero.
In this state, the second J-FETQ 2 is turned on by the capacitor C interposed between its gate and source. At this time, the resistance R 2 of the circuit is changed to the second J
- By selecting a value that is sufficiently large compared to the on-resistance of FETQ 2 , the first J-
The gate and source of FETQ 1 can be in a state where there is almost no potential difference, that is, a short-circuit state. Conversely, to turn off the first J-FETQ 1 ,
A predetermined control signal voltage V may be applied to the terminal 3.
This control signal voltage V is the breakdown voltage of a constant voltage element formed by connecting the pinch-off voltage V P of the first J-FETQ 1 and the source and substrate of the second J-FETQ 2 . A voltage exceeding the sum of V Z ,
That is, if |V|>|V P +V Z |, then both J−
FETQ 1 and Q 2 are always completely off, and no voltage is generated on the output terminal 2 side. Here, to explain in detail the above-mentioned constant voltage element, the second J-
The connection of FETQ 2 is shown in Figure 3 as an N-channel J-FET.
As shown in the schematic configuration diagram, the source electrode is connected to the substrate electrode 4a. The J-FET shown in FIG. 3 has a P type epitaxial growth region 6 and an N type channel region 7 on a P + type silicon substrate 5, and within this N type channel region, an N + type source electrode region 8a, N + type drain electrode region 8b
Since this structure has a typical structure including a P + -type gate electrode region 9a, a vertical junction of P + -N-P (P + ) (hereinafter simply PNP) is formed between the gate electrode terminal 3a and the substrate electrode terminal 4a. (abbreviated as “junction”) also exists. This PNP junction connects the second J-FETQ 2 gate electrode terminal 3 and the source electrode terminal 4 in FIG.
(It is the same on the circuit as the gate electrode of FETQ 1 )
It can become a constant voltage element by intervening between the two.
なお、第２図中のコンデンサＣは、第２のＪ−
FETQ2を確実にオンに保つために、第２のゲー
ト浮遊容量に依存するだけでなく、適当な外付け
容量を付加することが望ましい。また、Ｊ−
FETのソース・ドレインの各電極は、構造的に
は同じであるから、回路接続ではこれらを入れ替
えることもできる。 Note that the capacitor C in FIG. 2 is the second J-
In order to ensure that FETQ 2 remains on, it is desirable not only to rely on the second gate stray capacitance but also to add an appropriate external capacitance. Also, J-
Since the source and drain electrodes of the FET are structurally the same, they can be interchanged in circuit connection.
発明の効果
本発明によれば、第２のＪ−FETのソースと
基板電極とを接続して少なくとも二つのpn接合
が互いに逆方向に直列に接続された定電圧要素を
構成し、そのゲートに制御信号を印加することに
よつて入出力信号の断続が迅速、確実になされ、
オン状態からオフ状態へのスイツチ切換時の直流
変動がなく、したがつて高ダイナミツクレンジ、
低歪率、さらに零オフセツトというＪ−FETを
用いたスイツチ回路に特有の機能を充分に生かし
た電子機器が実現可能である。Effects of the Invention According to the present invention, the source of the second J-FET and the substrate electrode are connected to constitute a constant voltage element in which at least two pn junctions are connected in series in opposite directions, and the gate By applying a control signal, input/output signals can be quickly and reliably interrupted.
There is no DC fluctuation when switching from the on state to the off state, therefore high dynamic range,
It is possible to realize an electronic device that takes full advantage of low distortion and zero offset, features specific to switch circuits using J-FETs.
第１図はＪ−FETを用いて構成された従来の
スイツチ回路図、第２図は本発明の実施例スイツ
チ回路図、第３図は本発明実施例に用いたＪ−
FETの概要構造図である。
１……入力端子、２……出力端子、３……制御
信号端子、４……第１のＪ−FETのゲート電極
ならびに第２のＪ−FETのソース電極の共通端
子、Q1，Q2……ＮチヤネルＪ−FET、R1，R2…
…抵抗、RL……負荷、Ｃ……コンデンサ、ｅ…
…入力信号源。
Fig. 1 is a circuit diagram of a conventional switch configured using J-FET, Fig. 2 is a circuit diagram of a switch according to an embodiment of the present invention, and Fig. 3 is a circuit diagram of a switch constructed using J-FET.
It is a schematic structural diagram of FET. 1... Input terminal, 2... Output terminal, 3... Control signal terminal, 4... Common terminal of the gate electrode of the first J-FET and the source electrode of the second J-FET, Q 1 , Q 2 ...N channel J-FET, R 1 , R 2 ...
...Resistance, R L ...Load, C...Capacitor, e...
...Input signal source.
Claims (1)
ス・ドレインと、それぞれ、入出力端子とし、前
記第１の接合型電界効果トランジスタのゲート・
ソース間またはゲート・ドレイン間に第２の接合
型電界効果トランジスタのソース・ドレインをそ
れぞれ接続するとともに、前記第２の接合型電界
効果トランジスタのソースを前記第２の接合型電
界効果トランジスタの基板電極に接続し、前記第
１の接合型電界効果トランジスタのゲートを、抵
抗を介して接地点に接続したことを特徴とするス
イツチ回路。1 The source and drain of the first junction field effect transistor are used as input and output terminals, and the gate and drain of the first junction field effect transistor are respectively used as input and output terminals.
The source and drain of the second junction field effect transistor are connected between the sources or between the gate and the drain, and the source of the second junction field effect transistor is connected to the substrate electrode of the second junction field effect transistor. , and the gate of the first junction field effect transistor is connected to a ground point via a resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14967882A JPS5939122A (en) | 1982-08-27 | 1982-08-27 | Switch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14967882A JPS5939122A (en) | 1982-08-27 | 1982-08-27 | Switch circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5939122A JPS5939122A (en) | 1984-03-03 |
| JPH0374534B2 true JPH0374534B2 (en) | 1991-11-27 |
Family
ID=15480428
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14967882A Granted JPS5939122A (en) | 1982-08-27 | 1982-08-27 | Switch circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5939122A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5055723A (en) * | 1989-02-28 | 1991-10-08 | Precision Monolithics, Inc. | Jfet analog switch with gate current control |
| JP2010239466A (en) * | 2009-03-31 | 2010-10-21 | New Japan Radio Co Ltd | Semiconductor integrated circuit |
| JP2018098535A (en) * | 2016-12-08 | 2018-06-21 | 株式会社豊田自動織機 | Drive circuit for main switching element |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56137730A (en) * | 1980-03-29 | 1981-10-27 | Victor Co Of Japan Ltd | Fet switch circuit |
| JPS56141622A (en) * | 1980-04-04 | 1981-11-05 | Matsushita Electric Ind Co Ltd | Switching circuit |
-
1982
- 1982-08-27 JP JP14967882A patent/JPS5939122A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56137730A (en) * | 1980-03-29 | 1981-10-27 | Victor Co Of Japan Ltd | Fet switch circuit |
| JPS56141622A (en) * | 1980-04-04 | 1981-11-05 | Matsushita Electric Ind Co Ltd | Switching circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5939122A (en) | 1984-03-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4038607A (en) | Complementary field effect transistor amplifier | |
| US4739281A (en) | Analog buffer amplifier | |
| KR920001828A (en) | Integral circuit | |
| US4340867A (en) | Inverter amplifier | |
| GB2048598A (en) | Cmos class a amplifier | |
| US4672239A (en) | Sample-and-hold circuit arrangement | |
| JPH0374534B2 (en) | ||
| US3636378A (en) | Series-shunt-type semiconductor switching circuit | |
| CA1238694A (en) | Cmos differential amplifier stage with bulk isolation | |
| JPH07112133B2 (en) | Linear amplifier | |
| JP3217557B2 (en) | Voltage gain control circuit | |
| US4476448A (en) | Switched capacitor high-pass filter | |
| JPS59186411A (en) | Variable gain amplifying circuit | |
| JPH0363211B2 (en) | ||
| SU1676065A1 (en) | Operational amplifiers based on cmos transistors | |
| JPH06101650B2 (en) | Semiconductor integrated circuit device | |
| JPS6041812A (en) | Phase shifter | |
| JP2973654B2 (en) | Static auxiliary relay circuit | |
| JP2976439B2 (en) | Multi-gain amplifier | |
| US20030112077A1 (en) | Amplifier with a MOS output stage | |
| JPS6032416A (en) | Amplifier circuit | |
| JPS6022657Y2 (en) | Direct-coupled amplifier disturbance prevention circuit | |
| JPH04250709A (en) | Differential amplifier circuit | |
| JPH01188018A (en) | Dc clamping circuit | |
| JPS63246905A (en) | Field effect transistor circuit |