JPH0373050A - Serial write data transfer system - Google Patents

Abstract

PURPOSE:To improve speed for transfer end processing by executing the transfer end processing without waiting for the checked result of a data transfer end frame according to the detection of a link end command when it is confirmed that a response command corresponding to a chain data boundary command is received. CONSTITUTION:An in-device channel 11 and a remote channel 13 are connected by a serial data interface. In the in-device channel 11, a transfer end control means 15 is provided to execute the transfer end processing without waiting for the checked result of the frame after the link end command is received when it is confirmed that the response command corresponding to the chain data boundary command sent to the remote channel 13 is received. When it is confirmed that the response command corresponding to the chain data boundary command set to the remote channel 13 is received, the transfer end processing is executed without waiting for the checked result of the frame after the link end command is received. Thus, end processing time can be shortened.

Description

[Detailed Description of the Invention] [Summary] Regarding a serial write data transfer method for a serial data interface that connects an internal channel and a remote channel, the purpose of this invention is to speed up the transfer termination process by using a serial data interface to connect an internal channel and a remote channel. In a serial write data transfer method between an internal device channel and a remote channel, the internal channel receives a connection end command when it confirms that it has received a response command corresponding to the chain data boundary command sent to the remote channel. The frame is configured to include a transfer termination control means for executing transfer termination processing without waiting for the check result of the frame after reception.

[Industrial Application Field] The present invention relates to a serial write data transfer method for a serial data interface that connects an internal channel and a remote channel, and is particularly applied to transfer termination processing in serial write data transfer.

[Conventional technology]

FIG. 7 is a diagram showing a connection relationship between an intra-device channel and a remote channel.

In the figure, an internal channel (CH) 71 is connected to a remote channel (RCH) 73 via a serial data interface.
A connection is being made. Remote channel (RCH)
For example, a human output control device 75 is connected to 73, and write data from an internal channel (CH) 71 is sent thereto.

FIG. 8 is a diagram showing a frame structure at the end of the combination of chain data transfer in write data transfer. In addition,
The frames shown here are transferred from the remote channel to the internal channel, and each shows the data transfer end frame and the previous frame.

FIG. 8(a) shows the case where the CDG command does not exist in the data transfer end frame, and FIG. 8('b) shows the case where the CDG command exists in the data transfer end frame.

Here, FM (Frame Reader) is a frame synchronization signal and indicates the beginning of a frame.

The CD G (Chain Data Go) command is used to send a CD B (Chain Data Boundary
ry) This is a response from the remote channel 73 to the command, indicating that the data up to the CDB command has been sent to the human output control device 75. CRC (Cyclic
RedundancyCheck) indicates the check code of the frame. SS T (Send 5tat
us) D cloak indicates exit status. U.S.B.
(Llnit 5 status Byte) is the transfer end status from the human output control device 75, and is data accompanying the SST command. The END command indicates the end of the connection between the channel and the remote channel.

In such a frame configuration, the intra-device channel 71
sends a CDB command, the remote channel 73 responds by returning a CDG command, and further sends an SST command and an END command to the internal channel 71, the internal channel 71 that received the data transfer end frame In any frame configuration, the transfer end processing is performed after the detection of the END command.
This is done after confirming that the check results are normal. This means that even if the SST command and END command are recognized correctly, if the CRC check result is abnormal, a bit error may have occurred in the CDG command on the transmission path, indicating that there was an abnormality in the frame. This is because it is necessary to notify the control device (program).

[Problem to be solved by the invention]

By the way, in the internal channel 71 that receives the data transfer end frame and performs the transfer end processing, in any frame configuration, if the CDG command is recognized or if the CDB command is not sent to the remote channel 73, executes the SST command and END without waiting for the CRC check result of the data transfer end frame.
There is no particular problem even if the transfer end processing is performed at the moment the command is recognized, and the speed can be increased accordingly.

An object of the present invention is to provide a serial write data transfer method that enables such control and speeds up transfer termination processing.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, internal channel 11 and remote channel 1
3 are connected by a serial data interface.

When the internal channel 11 confirms that the response command corresponding to the chain data boundary command sent to the remote channel 13 has been received, the transfer end processing is performed without waiting for the check result of the frame after receiving the connection end command. A transfer termination control means 15 is provided for executing the transfer.

(Function) According to the present invention, when the reception of the response command corresponding to the chain data boundary command sent to the remote channel device 3 is confirmed, the transfer ends without waiting for the check result of the frame after receiving the connection end command. By executing the process, it is possible to shorten the termination process time.

Note that the same applies when the intra-device channel 11 does not send out the chain data boundary command.

Furthermore, if reception of the response command corresponding to the chain data boundary command is not confirmed, the transfer end process is performed after checking the frame as in the conventional case.

[Example] Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment of a device that implements the method of the present invention.

In the figure, the CDBD memory 21 is constituted by a flip-flop circuit that is set by sending a CDBD command and reset by receiving a CDGD command. The AND circuit 23 receives a detection signal E which is output before the inverted output of the CDBD memory 21 and in response to the detection of the END command.
is input.

The output of the CRC check signal bundling AND circuit 23, which turns on at the time of CRC check, is input to the OR circuit 24.

The AND circuit 25 includes the non-inverted output D of the CDBD memory 21.
, a transfer signal T that becomes "on" after the start of data transfer and turns "off" after receiving the SST command, a write signal W that becomes "on" during write control, and the output of the OR circuit 24 are inputted via the inverting circuit 26, respectively. be done.

The flip-flop circuit 27 is set by the output of the AND circuit 25 and reset by the output of the OR circuit 24, and its inverted (Q) output, the data transfer end control signal P-OK, is turned on. ”, the transfer end process according to the SST command and the END command is started.

FIG. 3 is a time chart illustrating the operation when the CDGD command is correctly recognized in the previous frame in the configuration where the CDGD command does not exist in the data transfer end frame (FIG. 8(a)).

In other words, the internal channel CH is the remote channel RC.
This is a case where a CDBD command is sent to H, the remote channel RCH responds with a CDGD command, and the intra-device channel CH correctly recognizes it.

The non-inverting output of the CDBD memory 21 remains "on" after sending out the CDBD command until receiving the corresponding CDGD command. Transfer signal T turns "off" when receiving the SST command and USB.

CRC check signal signal bundle Turns on for each CRC check.

Therefore, when internal channel CH is used for write control, CD
When the GD command is correctly recognized, the data transfer end control signal P-0 is set to "on" by the CRC check of the frame before the data transfer end frame and this state is maintained. When a command is received, the CR of the data transfer end frame is
Transfer termination processing can be executed immediately without waiting for the result of the C check.

FIG. 4 is a time chart illustrating the operation when the CDGD command cannot be recognized in the previous frame in the configuration where the CDGD command does not exist in the data transfer end frame (FIG. 8(a)).

In other words, the internal channel CH is the remote channel RC.
A CDBD command is sent to H, and the remote channel RCH responds with a CDGD command, but an error occurs on the transmission path and the internal channel CH cannot recognize it, or the remote channel RCH
This is a case where the CDGD command is not returned when the CH has not sent the data up to the CDBD command to the input/output control device.

The non-inverted output of the CDBD memory 21 is turned on by sending the CDBD command, but this state is maintained since the CDGD command is not detected.

Therefore, in the internal channel CH, the data transfer end control signal P-OK turns "on" in response to the CRC check of the frame before the data transfer end frame.
Since the non-inverting output of the BD memory 21 is "on", it becomes "off" again. i.e. SST command and EN
When the D command is received, the inverted output page of the CDB memory 2I is 1 off, so the data transfer end control signal P-OK remains off, and is turned on again by the CRC check of the data transfer end frame. ”, it becomes possible to execute the transfer end process as in the conventional case.

Figure 5 shows that in a structure where a CDG command exists in the data transfer end frame (tc<Figure 8(b)), the CDG
5 is a time chart illustrating an operation when a command is correctly recognized.

In other words, the internal channel CH is the remote channel RC.
This is a case where a CDB command is sent to H, the remote channel RCH responds with a CDG command, and the intra-device channel CH correctly recognizes it.

The non-inverting output of the CDB memory 21 remains "on" after sending the CDB command until receiving the corresponding CDG command. The transfer signal T turns "off" when the SST command and USB are received.

The CRC check signal C turns "on" every time a CRC check is performed.

Therefore, the data transfer end control signal P-OK is turned "on" by the CRC check of the frame before the data transfer end frame, and since the non-inverted output of the CDB memory 21 is "on", it is turned "off" again. Become. On the other hand, CDB
For the non-inverted output of the memory 21, the internal channel of the device is CDG.
If the command is recognized correctly, it will turn off. That is, when the SST command and the END command are received, the data transfer end control signal P-OK is "off", but since the non-inverted output of the CDB damory 21 is also "off", the detection signal of the END command is As a result, it becomes "on", and the transfer end process can be executed immediately without waiting for the result of the CRC check of the data transfer end frame.

FIG. 6 is a time chart illustrating the operation when the CDG command is not recognized in the configuration in which the CDG command is present in the data transfer end frame (FIG. 8 (b)).

The non-inverted output of the CDB memory 2I is turned on by sending the CDB command, but this state is maintained since no CDG command is detected.

Therefore, in the device internal channel, the data transfer end control signal P-OK is turned "on" in response to the CRC check of the frame before the data transfer end frame, but the non-inverted output of the CDB memory 21 is "on". Therefore, it becomes "off" again. That is, when the SST command and the END command are received, the inverted output of the CDB memory 210 is "off", so the data transfer end control signal P is
-OK remains "off", and after it is turned "on" again by the CRC check of the data transfer end frame, it becomes possible to execute the transfer end process as in the conventional case.

In this way, in any frame configuration, CDG
If the command is recognized correctly, or if the CDB command has not been sent to the remote channel, the transfer ends when the SST command and END command are recognized, without waiting for the CRC check result of the data transfer end frame. This makes it possible to reduce the termination processing time accordingly.

〔Effect of the invention〕

As described above, according to the present invention, the response command (
CDG command) is confirmed, and if no chain data boundary command is sent to the remote channel, the connection end command (END command) is detected and the data transfer end frame is checked without waiting. Since the transfer end process can be performed, it is possible to speed up the transfer end process.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram showing the configuration of an embodiment of a device that implements the method of the present invention, Figs. 3 to 6 are time charts of the embodiment, and Fig. 7 is an internal diagram of the device. FIG. 8 is a diagram showing the connection relationship between a channel (CH) and a remote channel (RCH). FIG. 8 is a diagram showing a frame structure at the end of coupling of chain data transfer in write data transfer. In the figure, 1 is an internal channel, 3 is a remote channel, 5 is a transfer end control means, 1 is a CDB memory, 3.25 is an AND circuit, 4 is an OR circuit, 6 is an inversion circuit, and 7 is a flip-flop circuit. , 1 is an internal channel (CH), 3 is a remote channel (RCH), and 5 is an input/output control device. Figure 2 between blocks showing the configuration of an embodiment of a device that implements the method of the present invention. Figure 1 shows the connection relationship between channels within the device and remote channels. Figure 8 showing the frame structure

Claims (1)

[Claims] (1) In a serial write data transfer method between an internal device channel (11) and a remote channel (13) connected by a serial data interface, the internal device channel (11) has data sent to the remote channel (13). The transfer end control means (15) is provided for executing transfer end processing without waiting for the check result of the frame after receiving the link end command when reception of the response command corresponding to the chain data boundary command is confirmed. A serial write data transfer method featuring