JPH036990A - Picture processing circuit - Google Patents

Abstract

PURPOSE:To save a line memory for a vertical digital filter by providing a memory means able to read continuously at least twice a stored data, reading a prescribed storage data of plural memory blocks simultaneously so as to supply the data to a circuit of the vertical digital filter processing. CONSTITUTION:A switch 30 is thrown for each line to distribute a switch Y signal cyclicly to FIFO memories 31, 32, 33 for each line. Then the signal is read simultaneously and switched by using a matrix switch 34 to extract 3 consecutive line signals. Thus, a signal from 3 adjacent lines of an image pickup device 12 and a signal read decreasing the readout line one by one simultaneously are obtained from three taps 34a, 34b and 34c. Thus, 3 output signals of the switch 34 are inputted to a finite impulse response(FIR) type vertical filter 36 to apply aperture correction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing circuit, and more specifically to an image processing circuit used in an electronic still camera or the like.

[Prior Art] In recent years, with the increase in the capacity of semiconductor memories, electronic still cameras that make extensive use of semiconductor memories have been attracting attention. In such electronic still cameras, the image sensor, for example, RGB
The switch Y signal obtained by switching the output is
input to a FO (first-in first-out) type memory, and from the output of the FIFO memory, two I
An IH delay signal and a 2H delay signal are formed by an H line memory, and the FIFO memory output, IH delay signal, and 2H delay signal are input to a vertical FIR (finite impulse response) type filter to perform vertical aperture correction. A luminance signal is thereby obtained.

Further, after extracting each of the R, G, and B signals from the IH delay signal and performing horizontal FIR filter processing on each,
It is converted into color difference signals R-Y and B-Y, and the color difference signals are sequentialized.

The luminance signal and line-sequential color difference signal obtained in this way are clamped and blanked, a composite synchronization signal is added to the luminance signal, and a known magnetic recording/reproducing device is used to magnetically record the signal onto a video floppy. do.

[Problems to be Solved by the Invention] In the conventional example described above, in addition to the FIFO memory having a predetermined capacity, two IH line memories are required for vertical aperture correction. This leads to an increase in the manufacturing cost due to the enlargement of the circuit scale.

Therefore, it is an object of the present invention to provide an image processing circuit that solves these problems.

[Means for Solving the Problems] The image processing circuit according to the present invention includes a memory means capable of reading out the same stored data at least twice in succession in units of a predetermined amount, and divides the storage area of the memory means. The video signal is distributed to a plurality of memory blocks in a predetermined order, and predetermined stored data of the plurality of memory blocks is simultaneously read out and supplied to a vertical digital filter processing circuit.

[Operation] With the above means, it is possible to effectively utilize the data stored in the memory means, and the line memory for the vertical digital filter can be saved.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of an electronic still camera to which the present invention is applied. Note that, in order to facilitate understanding of the drawings, illustrations of clock signal lines and clock signal generation circuits to each circuit are omitted. 10 is a photographing lens, and 12 is an image sensor equipped with an RGB stripe filter. The image sensor 12 converts a subject image formed by the photographic lens 10 into an electrical signal. Sample hold (S/
H) Circuit 1-2 is RlG output from the image sensor 12,
Each H signal is sampled and held. As a result, only the video portion is extracted. The level adjustment circuit 16 controls the S/H according to a control signal from the system rM control circuit 18.
The levels of the R, G, and H output signals of the circuit 14 are adjusted.

Specifically, according to the output of the exposure sensor 20, the level of each of the R, G, and B outputs of the S/H circuit 14 is adjusted to obtain proper exposure, and the color is adjusted according to the outputs of the R sensor 22 and the B sensor 24. For balance adjustment, for example, R signal and B
Adjust the signal level.

The A/D converter 26 digitizes each of the RlG and H outputs of the level adjustment circuit 16. Note that the A/D converter 26 clamps the signal of the optical black portion of the image sensor, and outputs a signal that has been gamma-converted using the gamma characteristic of the resistance ladder for A/D conversion. The switch 28 is switched at 3x speed, thereby causing the A/D converter 26
A so-called switch Y signal is formed from the R2O and B outputs.

That is, the switch Y signal is a three-times-speed sequential signal of R, G, and B. Then, the switch 30 is switched for each line, and the switch Y signal is cyclically distributed to the FIFO memories 31, 32, and 33 for each line. That is, if the top line of the image captured by the image sensor 12 is the first line, and m is an integer, then the memory 31 stores the first line. 4th. 7th. ..., the signal of the (3m+1)th line is written into the memory 32, and the signals of the 2nd, 5th, . The signals of the 8th, . . . (3m+2)th lines are stored in the memory 33. 6th. ..., No. (3m+3
) line signal is written.

Basically, the FIFO memories 31, 32, and 33 may be of any type as long as they can read out the same line of stored data repeatedly or that can read out the stored data of a designated line. For the former, for example, the increment pulse from the horizontal readout counter may be masked by an external control signal, and for the latter, the horizontal successive counter and vertical readout counter may be changed to specified values. .

Next, the signals in the FIFO memories 31, 32, and 33 are simultaneously read out, and the matrix switch 34 switches the signals to take out three consecutive lines of signals. For example, first, the signals of the first line from the memory 31, the second line from the memory 32, and the third line from the memory 33 are taken out and passed through the matrix switch 34 as they are. Next, the second line signal is read out from the memory 32, the third line signal is read out from the memory 33, the fourth line signal is read out from the memory 31, these are rearranged by the matrix switch 34, and the tap 34a is read out again. The signals of the second line, the third line from the intermediate tap 34b, and the fourth line from the tap 34c are output. Similarly, at the next timing,
The matrix switch 34 includes an eighth line from the tap 34a, a fourth line from the intermediate tap 34b, and a tap 34c.
outputs the signal of the fifth line.

In this way, from the three taps 34a, 34b, and 34c of the matrix switch 34, signals from three adjacent lines of the image sensor 12 are simultaneously transmitted, and the readout line is lowered one line at a time. A signal read out is obtained. Therefore, the three output signals of the matrix switch 34 can be manually input to the finite impulse response (FIR) type vertical filter 36 to perform aperture correction. The output of the vertical filter 36 is converted back to an analog signal by a D/A converter 38 and becomes a pseudo Y signal.

On the other hand, the signal at the intermediate tap (corresponding to the phase center of the vertical filter 36) 34b of the matrix switch 34 is changed to R and G again by the switch 40.

B signals, each passed through a horizontal filter 44.4
6.48, the signal is input to the color difference matrix circuits 48 and 50, and is converted by the color difference matrix circuit 48 into a color difference signal R-Y and by the color difference matrix circuit 50 into a color difference signal B-Y. By switching the switch 52 for each line, the color difference matrix circuit 48.5
The output of 0 is line-sequentialized and converted into an analog signal by a D/A converter 54.

The pseudo luminance signal output from the D/A converter 38 and the D/A converter 38
The line sequential color difference signals output from the A converter 54 are band-limited by LPFs 56 and 58, clamped by clamp circuits 60 and 62, and then passed through the blanking circuit 64.
．． 66 for blanking. Blanking circuit 6
A synchronizing signal is superimposed on the output of 4 by an adder 68.

Then, the output of the blanking circuit 62 is output to the recording/playback device 7.
The output of the adder 68 is applied to the luminance input of the recording and reproducing device 70, and is recorded on a recording medium such as a magnetic disk or a solid-state memory device.

In the embodiment shown in Fig. 1, the luminance signal for recording is formed from the switch Y signal, but the high-frequency component is extracted from the switch Y signal and used as the Y signal, the YL times signal is formed from the RGB signal, and both are combined. Alternatively, a luminance signal for recording may be formed.

Also, create a correction signal for the switch Y signal from the color difference signal,
It may be added to the switch Y signal to form a luminance signal for recording. Furthermore, this embodiment is not limited to the RGB stripe filter, and the pixel arrangement of the image sensor 12 may also be
It can be applied to various arrangements, such as square ones and two-dimensionally offset ones.

FIG. 2 shows a block diagram of another embodiment of the present invention.

Note that the system control circuit that controls the entire system, the exposure sensor, and the colorimetric sensor are not directly related to this embodiment, and are therefore not shown. The optical image taken by the photographing lens 110 is captured by the image sensor 11
2, the R, G, and B signals output from the image sensor 112 are sampled and sampled by the S/H circuit 114.
The level adjustment circuit 116 performs exposure adjustment and color balance adjustment. RlG of the level adjustment circuit 116,
Each output of B is connected to a switch 118 and a clamp circuit 120.
The signal is input to the A/D converter 122 via the A/D converter 122, where it is converted into a digital value with gamma characteristics taken into consideration. Note that the switch 118 is connected to the still/video recording/playback device 12, which will be described later.
The circuits after the clamp circuit 120 are used to process the reproduction signal from the clamp circuit 12, and the R, G, and B outputs of the converter 122 of the clamp circuit 12 are sequentially converted into R, G, and B outputs by a switch 126 that switches at 3 times the speed. signal (switch Y signal), and as shown in FIG. 3, the switch 128
, 130, the signals of the FIFO type field 132-in and the signals of the even lines are distributed to the FIFO field memory 134. The signals written to the memories 132 and 134 are read out twice on a line-by-line basis alternately. The outputs of memories 132 and 134 are switched by switches 136 and 138. This causes switch 136,1
From 38 onwards, the signals from the second line onwards appear twice in succession, such as the first line, second line, second line, third line, third line, fourth line, etc. is obtained.

The output of the switch 136 is sent to two line memories 1 through an offset removal circuit 140 that does nothing during recording.
42,144 series circuits are applied. Since the line memories 142 and 144 each function as a 0.5H line memory during recording, the output of the line memory 144 is delayed by IH with respect to the input of the line memory 142. The output of the switch 138, the output of the switch 136 (signal passed through the offset removal circuit 140), and a signal delayed by IH are applied to the vertical filter 146.

Since the output of the switch 136 is delayed by IH with respect to the output of the switch 138, the vertical filter 146 has an OH
(no delay), IH delayed and 2H delayed signals are input, and vertical aperture correction is performed.

The HPF 148 extracts high-frequency components from the output of the vertical filter 146, and the adder 150 adds a low-frequency luminance signal formed by color signal processing to be described later to the output of the HPF 148.
The blanking circuit 152 performs blanking processing, recording and
The signal is applied to the D/A converter 156 through a switch 154 that is switched during playback and converted into an analog signal, and then applied to the synchronous adder 16 through a switch 158 and an LPF 160.
2, a synchronizing signal is added, and the signal is input to the still video recording/playback device 124.

On the other hand, regarding the color signal, the RGB separation circuit 164 separates the RGB sequential signals from the middle tap of the vertical filter 146 into 1
Separates into R, G, and H signals of /3 period. The R, G, and B outputs of the RGB separation circuit 164 are LPF166.1.
68 and 170, the signal is band-limited and supplied to the color difference matrix circuit 172, where it is converted into the color difference signal RY and the same B-Y. At the same time, a low band luminance signal is formed and provided to adder 150. The color difference signals R-Y and B-Y are line-sequentialized by a switch 174 and sent to a blanking circuit 176.
blanking, switch 154, D/A converter 1
56, a switch 158, and an LPF 178 to the still video recording/playback device 124.

Regarding the signals reproduced from the still video recording/reproducing device 124, the DC level of the luminance signal and the line-sequential color difference signal is individually fixed by the clamp circuit 120, and the DC level is fixed by the A/D converter 122 as shown in FIG. The sampled digital signal is sent to switch 128 as shown in FIG.
, 130 to memories 132, 134. As for the signals read out from the memories 132 and 134, the luminance signal is sent to the switch 154 by the switch 138, and the line-sequential color difference signal is sent to the offset removal circuit 140 by the switch 136.

The offset removal circuit 140 adjusts the pedestal levels of the R-Y component and the B-Y component to be the same, and the line memories 142 and 144 and the adder 180 form a color difference line sequential interpolation signal, and the line switch 182 The line-to-line color difference signals R-Y and B-Y are formed by the encoder 184, which is converted into an NTSC video signal, and the blanking circuit 186 inserts blanking. Note that during playback, each of the line memories 142 and 144 functions as an IH line memory depending on its clock cycle. The output of blanking circuit 186 is applied to switch 154.

In this way, the brightness signal and the color difference signal of the reproduced signal are supplied to the switch 154, and thereafter the D/A converter 15
6, it is converted into an analog signal by a switch 158, a band-limiting LPF 187 188, and an output amplifier 189,
It is output from the output terminal via 190.

In the embodiment shown in FIG. 2, the number of block divisions of the FIFO memory elements constituting the memories 132 and 134 is smaller than in the embodiment shown in FIG. 1, so there is an advantage that the number of pins when integrated into an IC is reduced. . In addition, line memory 142
, 144 are used both during recording and reproduction, so that a circuit configuration with no waste can be constructed as a whole.

[Effects of the Invention] As can be easily understood from the above explanation, according to the present invention, the number of memory elements can be reduced as a whole by effectively utilizing FIFO memory, and miniaturization and cost reduction can be achieved. .

[Brief explanation of drawings]

FIG. 1 is a block diagram of the configuration of one embodiment of the present invention, FIG. 2 is a block diagram of the configuration of the second embodiment, and FIG. 3 is an explanatory diagram of how the memories 132 and 134 are used during recording (during photographing). , 4th
Figure 2 is an explanatory diagram of the sampling points of the reproduced signal, and Figure 5 is an explanatory diagram of sampling points of the reproduced signal.
The figure is an explanatory diagram of how the memories 132 and 134 are used during playback in FIG. 2.

Claims (1)

[Claims] A memory means capable of successively reading out the same stored data at least twice in units of a predetermined amount is provided, and a video signal is distributed in a predetermined order to a plurality of memory blocks obtained by dividing the storage area of the memory means, An image processing circuit characterized in that predetermined stored data of the memory blocks are simultaneously read out and supplied to a circuit for vertical digital filter processing.