JPH0369131A - Probe for semiconductor integrated circuit test use; manufacture of semiconductor device including test process using same probe - Google Patents

Abstract

PURPOSE:To ensure a high-reliability contact with pads which are arranged in a pitch of 10mum order on a high-density integrated circuit chip by providing the following: a semiconductor substrate; a plurality of needle-shaped protrusions formed by selectively etching one surface of the substrate; a means to electrically separate the individual needle-shaped protrusions from each other; and a connection means. CONSTITUTION:The following are provided: a semiconductor substrate 10; a plurality of needle-shaped protrusions 11 formed on the semiconductor substrate 10 by selectively etching one surface of the semiconductor substrate 10; a separation means used to electrically separate the individual needle-shaped protrusions 11 from each other; and connections means 12, of a beam lead structure, used to connect the needle-shaped protrusions 11 to an external circuit. For example, a plurality of contactors 11 formed by etching a silicon chip 10 are arranged on one surface of the silicon chip 10 whose size is about the same as that of an integrated circuit chip to be inspected. The individual contactor 11 is provided with needle-shaped protrusions at their tip; they are installed so as to correspond, in a one-to-one manner, to pads on the integrated circuit chip to be inspected; the individual contactor 11 is separated electrically by a means of a P-N junction or the like. A window 14 for visual observation use is formed in the chip 10.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a probe used for testing semiconductor integrated circuits in the form of wafers or chips.

The purpose is to ensure highly reliable contact with pads arranged on the order of 10 um on a high-density integrated circuit chip.

A semiconductor substrate, a plurality of needle-like protrusions formed on the semiconductor substrate by selectively etching one surface of the semiconductor substrate, and a separating means for electrically separating each of the needle-like protrusions from each other; A device comprising a connecting means having a beam lead structure for connecting a needle-like protrusion to an external circuit. related to test probes.

[Conventional technology]

The manufacturing process of semiconductor integrated circuits consists of a pre-process to complete the semiconductor integrated circuit in the chip area on the wafer, and a process to separate the wafer after the pre-process into chips and complete the packaging of each individual chip. It is broadly divided into post-processing.

Static and dynamic characteristic tests are performed on integrated circuits in a wafer state at the stage where the pre-process has been completed, and integrated circuit chips to be subjected to the post-process are selected. In the characteristic test described above, a probe having a plurality of needle-shaped metal contact terminals is used as a means for temporarily electrically connecting an external circuit such as a signal source or a power source to the integrated circuit under test.

The structure of the conventional probe used for the above purpose was changed to the sixth
As shown in the figure. As shown in the same figure (a), the center part has a diameter of 30 mm.
A plurality of contacts 3 made of tungsten and having needle-like tips are fixed to the upper surface of a printed wiring board 1 in which a through hole 2 of approximately mm size is provided. Palladium (Pd) and beryllium ffiM (Be-C) are used as the contactor 3.
u) etc. may also be used. The tips of the contacts 3 are curved so as to protrude from the two through holes 2 to the bottom surface of the printed wiring board 1, as shown in FIG. They are arranged on the sides of a quadrilateral at a pitch of 9, for example, 200 μm, corresponding to the pads provided on the chip. The other end of the contactor 3 is connected to a connector connecting terminal 5 of the printed wiring board 1 through a wiring 4 on the printed wiring board 1.

In the test, the wafer was aligned so that one of the integrated circuit chip areas was exposed in the through hole 2.

The tip of the contactor 3 is pressed into contact with each pad provided on the periphery of the integrated circuit chip, and a test signal and power supply voltage are supplied from the connector connection terminal 5.

[Problem to be solved by the invention]

The main problems with the above conventional test probes are as follows.

The following two points can be mentioned.

■Probe contact 3 is attached to the pad on the integrated circuit chip 10.
When the tip of the contactor 3 of the conventional structure is pressed into contact with the pad 11, the tip of the contactor 3 of the conventional structure is displaced in the lateral direction so as to rub against the pad 11, as shown in FIG. The dotted line shows the contact 3 before movement occurs. For this.

Pad 11 made of a metal layer such as At is easily damaged. If the pad 11 is severely damaged, bonding in a subsequent process may be hindered.

(Integrated circuit chip 1 is connected using bump type wiring method.)
When trying to connect 0 to an external circuit.

Bonding may become impossible.

■The contactor 3 is made by arranging the tips of multiple tungsten wires, etc., each several centimeters long with one end fixed, at a pitch of about 200 μm, so that it can be positioned relative to the pad on the integrated circuit chip to be tested. It is difficult to ensure accuracy. In addition, 1) the mechanical strength is not sufficient, and 2) it is easily deformed when subjected to mechanical shock or caught on the tip of the contactor 3.

Moreover, as the scale of semiconductor integrated circuits increases, the number of connections to external circuits increases, and as a result, the number of pads on integrated circuit chips also tends to increase.

As a result, the area occupied by the pads on the integrated circuit chip increases. In order not to increase the pad occupancy rate, it is necessary to reduce the pad area and arrangement pitch by %.

In response to this requirement, on the integrated circuit chip side, it is relatively easy to reduce the pad area and array pitch, and it is also possible to control the dimensions on the μm order. With the probe, it is difficult to maintain the array pitch and positional accuracy of the tip of the contactor 3 to meet the above requirements, making it difficult to conduct operation tests at the pre-process stage as in the past. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a test probe capable of solving the above-mentioned conventional problems, and to make it possible to test the operation of large-scale integrated circuit chips in the pre-processing stage by using this probe.

[Means to solve the problem]

The above object is to electrically isolate a semiconductor substrate, a plurality of needle-like protrusions formed on the semiconductor substrate by selectively etching one surface of the semiconductor substrate, and each of the needle-like protrusions from each other. A probe for testing a semiconductor integrated circuit according to the present invention, comprising a separation means and a connection means having a beam lead structure for connecting the needle-shaped protrusion to an external circuit, and a semiconductor integrated circuit in the form of a wafer or chip. It is distantly related to the method for manufacturing a semiconductor device according to the present invention, which includes a step of performing a test by bringing the needle-like protrusion of the probe into contact with a pad formed in the probe.

[For production]

The contacts in the test probe of the present invention are formed by integrating a plurality of fine acicular protrusion-like contacts at a minute arrangement pitch using microfabrication technology established in the manufacturing of semiconductor integrated circuits. It is something. in particular.

■Using the side-etching effect of the semiconductor substrate or the difference in etching speed due to the plane orientation of the semiconductor crystal, a needle-shaped contact is formed.■Each contact is separated from each other by using element isolation technology in semiconductor integrated circuits. (1) Each electrically isolated contactor is connected to an external circuit using the beam lead method, which is a type of bonding technology for semiconductor integrated circuits.

Therefore, contacts that correspond to the reduced pad and arrangement pitch of the integrated circuit chip to be tested can be formed with high precision, and even large-scale integrated circuits in the wafer state can be operated using probes in the same way as in the past. Tests can now be conducted. Furthermore, because the tips of all contacts are maintained in the same plane, there is no need to apply extra pressure to the pads on the integrated circuit chip under test. Moreover, since no lateral displacement occurs during pressing unlike in conventional probes, damage to pads on the chip is reduced.

Product yield and reliability are improved.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a perspective view of a main part of a probe for testing semiconductor integrated circuits according to the present invention, in which a silicon chip 10 is etched on one surface of a silicon chip 10 of approximately the same size as the integrated circuit chip to be tested. A plurality of contacts 1 formed by
1 are arranged. Each contact 11 has a needle-like protrusion at its tip, and is provided in one-to-one correspondence with the pads formed on the integrated circuit chip to be tested.

The respective contacts 11 are electrically isolated from each other by means described later.

On the silicon chip 10, electrodes 12 of a well-known beam lead structure are provided as connection means for connecting each contactor 11 to an external circuit. Further, a visual observation window 14 is provided in the center of the silicon chip 10. The visual observation window 14 is.

It is used as a window when aligning the integrated circuit chip to be tested and the probe of the present invention.

The contact 11 has an eight-conical shape unless special measures are taken in the etching process during its formation. and,
When these are pressed against pads on the integrated circuit chip under test, they bite into pads made of metal such as aluminum.

Therefore, if the pressing force is excessive, the pad may break through the metal layer forming the bottom of the tank, damaging the underlying insulating layer or impurity diffusion layer formed on the semiconductor substrate.

In order to avoid such dangers and facilitate operations during testing, the structure of the contactor 20 as shown in FIG. 2(a) is effective.

That is, the contact 20 shown in FIG. 2(a) has a structure in which needle-like protrusions 22 are formed on a plurality of protrusions 21 having flat surfaces formed by selectively etching the silicon chip 10. . The contactor 20 in FIG. 2(a) is shown in FIG.
As shown in b), when the flat surface of the protrusion 21 is pressed against the pad 25 formed on the integrated circuit chip 24 under test, when the flat surface of the protrusion 21 abuts against the upper surface of the pad 25, the needle-like protrusion 22 will no longer touch the pad. 25 is prevented from digging into the inside.

The method for manufacturing the probe of the present invention will be explained with reference to FIG.

For example, one surface of a silicon wafer is oxidized to form a SiO□ film, and then this S
By etching the iO□ film, as shown in FIG. 3(a),
5i0 with a diameter of about 20 μm on the surface of the silicon wafer 30.
2 masks 1331 are formed. Figure 3(b) is
) is shown. The arrangement pitch of the 5in2 mask layer 31 is the same as the arrangement pitch of pads on an integrated circuit chip to be tested (not shown), and is, for example, 40 μm.

It then consists of a mixed solution of IP (for example with HNO3).

5 using a well-known isotropic etching solution for silicon.
Silicon wafer 3 exposed from iOz mask layer 31
0 is etched to a depth of about 10 μm from its surface. In this etching, the silicon wafer 30 is etched not only in the vertical direction, but also in the horizontal direction due to the side etching effect under the Sing mask layer 31. The amount of etching in the lateral direction increases as it approaches the surface of the silicon wafer 30, so when etching is performed to a depth of 10 μm from the surface of the silicon wafer 30, the SiO□ mask layer 3
As shown in Fig. 3 (C), below 1 there is a conical protrusion,
That is, the needle-like protrusion 32 remains. The height of the needle-like protrusion 32 is approximately 10 μm.

Note that similar needle-like protrusions 32 can also be formed by using a silicon wafer 30 with an exposed (100) plane and using an etching solution such as KOH whose etching rate depends on the plane index of the silicon wafer. . In this case, the needle-like protrusion 32 does not necessarily have a conical shape, but has a pyramidal shape, for example. Moreover, if a surface layer with a thickness of 10 μm containing an impurity species different from that of the base layer is previously formed on the surface of the silicon wafer 30.

The amount of etching for forming the needle-like protrusions 32 can be easily controlled. Such a surface layer is formed on the silicon wafer 30.
It is formed by epitaxial growth on the surface.

Note that the contact 20 having the structure shown in FIG. 2 is formed as follows.

This can be achieved by forming the needle-like projections 22, then providing a resist layer to mask the area of the projections 21 including the needle-like projections 22, and anisotropically etching the exposed silicon wafer surface.

After removing the SiO□ mask layer 31, the surface of the silicon wafer 30 is thermally oxidized to form a 5i02 film, and a resist is applied thereon. Then, this resist layer is exposed and developed to form a resist mask 35 having openings corresponding to the needle-shaped projections 32 and the contact regions 34 adjacent thereto, as shown in FIG. 3(d).

The SiOg film exposed within this opening is removed by etching. FIG. 3(e) shows the YY cross section of FIG. 3(d).

Reference numeral 36 is the 5in2 film. resist mask 35
The patterning is performed in a region having a step of about 10 μm including the needle-like protrusions 32.
This is easily possible using an exposure method or a reduction projection exposure method.

Next, the resist mask 35 is removed and the SiO□ film 3 is removed.
The surface of a silicon wafer 30 where 3 is exposed using 6 as a mask.

That is, impurities are diffused into the surfaces of the needle-like protrusions 32 and the contact regions 34. This impurity is removed from the silicon wafer 3.
If 0 is p-type, it is n-type. As a result, the third
As shown in Figure (f), an n-type region 38 is formed on the surface of the needle-like protrusion 32 and the contact region 34.

After the above, as shown in the plan view of FIG. 3(8) and the cross-sectional view of FIG. 3(b), an electrode 39 connected to the contact region 34 is formed. The electrode 39 is made of, for example, an Au thin film, and is used for connection to an external circuit based on a well-known beam lead technique, as will be described later. In addition.

In order to prevent the electrode 39 made of Au and the silicon wafer 30 from forming a eutectic alloy, the electrode 39 and the silicon wafer 30 are
Providing a well-known barrier layer (not shown) in between is similar to a typical integrated circuit. The electrode 39 should not come into contact with the integrated circuit chip to be tested during testing.

It is necessary that the height is sufficiently lower than the height of the needle-like projection 32.

Next, the silicon wafer 30 is separated into individual probes. This separation is carried out by masking the entire surface of the silicon wafer 30 on which the needle-like protrusions 32 and the like are formed with a resist layer, and forming a resist mask in the area corresponding to the probe on the 1M surface side to expose the silicon wafer 30. It is appropriate to use a method of etching away. At this time, the visual observation window 14 (first
By providing an opening corresponding to the window (see figure), the visual observation window 14 is formed at the same time.

In the manner described above, one probe of the present invention is formed as shown in FIG. 3(i). The electrode 39 has a beam lead structure that protrudes laterally from the silicon chip 10 that is the base of the probe.

The probe of the present invention is adhesively fixed to the printed wiring board Fi1 in the conventional test probe shown in FIG.
The electrode 39 may be bonded to the wiring 4, or as shown in FIG. Substrate 40
The wiring 41 and the electrode 39 formed above are bonded. The ceramic substrate 40 has superior rigidity compared to a standard printed wiring board, and makes it easy to ensure positional accuracy and parallelism with the wafer when setting the probe.

In the probe of the above embodiment, the needle-like protrusion 32 and the contact region 34 are connected by an n-type region 38 formed on their surfaces. Therefore.

If a voltage lower than the measurement voltage range (including negative potential and ground potential) is applied to the silicon chip 10,
This is because a reverse bias voltage is applied between the silicon chip 10 and the n-type region 38.

Each needle-like projection 32 can be electrically isolated from each other. Note that the surface of the needle-like protrusion 32 is covered.

For example, by forming a metal thin film such as tungsten or a metal silicide thin film such as tungsten silicide, the contact resistance of the needle-like projections 32 can be lowered.

An insulating isolation structure may be used as a method for electrically isolating the needle-like protrusions 32 from each other. For example, the well-known 5ol (Silicon on In-
It is convenient to use the 5ulator technique. That is, an SOI substrate 50 as shown in FIG. 5(a), which is formed by a well-known silicon wafer bonding technique, is prepared. SO■ based Fi50 is 1 normal thickness silicon wafer 5
1 and a SiO□ film 52 formed by thermally oxidizing its surface.
The silicon layer 5 is bonded by thermocompression with a high voltage applied to the silicon wafer 51 via the 5iOz film 52.
It is composed of 3. The silicon layer 53 is finished to a thickness of about 12 μm, for example, by mechanical polishing.
Either the surface is made n-type in advance, or at least the surface is made n-type by diffusing impurities after the polishing.

Using the same method as explained in FIG. 3, a StO□ mask layer 54 is formed on the surface of the silicon JW 53 as shown in FIG. form. Next, the remaining silicon layer 5
3 is selectively etched to separate one individual needle-like protrusion 55 as shown in FIG. 5(C). A contact region 56 made of silicon layer 53 is provided corresponding to needle-like protrusion 55 . After forming electrodes (not shown) having a beam lead structure in the contact region 56 in the same manner as in the previous embodiment, the silicon wafer 51 is separated into individual probes. According to the structure shown in FIG. 5, the protrusion 55 has Sin,
They are insulated from each other by the film 52, and there are no special restrictions on the voltage applied to the probe substrate made of the silicon wafer 51.

[Effects of the Invention] According to the present invention, a test probe having contacts with an array pitch corresponding to pads on a high-density integrated circuit chip can be easily manufactured, and compared to conventional probes, the test probe has It not only has excellent positional accuracy and flatness, it also provides a probe that is resistant to m1tt impact. It also reduces damage to the pads on the integrated circuit chip under test, improving the yield of high-density integrated circuit products. This has the effect of improving reliability.

[Brief explanation of drawings]

FIG. 1 is a perspective view of a main part of a probe for testing a semiconductor integrated circuit according to the present invention. FIG. 2 shows a modification of the structure of the contact in the probe of the present invention. FIG. 3 is an embodiment of the probe manufacturing method of the present invention. FIG. 5 is an explanatory diagram of another method for separating the contact in the probe of the present invention. FIG. 6 is a structural explanatory diagram of a conventional semiconductor integrated circuit testing probe. FIG. 7 is a diagram illustrating problems with a conventional probe. It is. In fig. 1 is a printed wiring board, 2 is a through hole. 3 is a contact, 4 and 41 are wiring. 5 is a connector connection terminal, and IO is a silicon chip. 11 and 20 are contacts, and 12 and 39 are electrodes. 14 is a window for visual observation; 21 is a projection 22, 32 and 55 is a needle-like projection. 24 is an integrated circuit chip to be tested, and 25 is a pad. 30 and 51 are silicon wafers. 31 and 54 are SiO□ mask layers. 34 and 56 are contact areas. 35 is a resist mask, and 36 and 52 are 5in2 films. 38 is an n-type region, and 40 is a ceramic substrate. 50 is a SOR substrate, and 53 is a silicon layer. It is. (0-) (b) Mogaki Jinmei's 4-Tan body medicine horizontal circulation message formation book H-Phi main part squinting national policy 1 has not been released Fig. 2 Example of how to make the arrow 7' of the structure Fig. 3 (1,000 1
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Claims (3)

[Claims] (1) A semiconductor substrate, a plurality of needle-like protrusions formed on the semiconductor substrate by selectively etching one surface of the semiconductor substrate, and separation for electrically separating each of the needle-like protrusions from each other. 1. A probe for testing a semiconductor integrated circuit, comprising: a connecting means having a beam lead structure for connecting the needle-like protrusion to an external circuit. (2) Claim 1 characterized in that the needle-like protrusion is formed on the flat surface of a plurality of protrusions each having a flat surface formed by selectively etching the surface of the semiconductor substrate.
probe for testing semiconductor integrated circuits. (3) A semiconductor device characterized by comprising the step of performing a test by bringing the needle-like protrusion of the probe according to claim 1 or 2 into contact with a pad formed on a semiconductor integrated circuit in the form of a wafer or chip. Production method.