JPH0368580B2 - - Google Patents

Description

Detailed description of the invention (Technical field to which the invention pertains) The present invention provides synchronization correction for diversity reception when a fixed station and a plurality of mobile stations or mobile stations perform data transmission over an HF (short wave) line. This relates to a method of detecting received data on a bit-by-bit basis.

(Prior technology) A fixed station and multiple mobile stations or between mobile stations are HF
When transmitting data over a line, conventionally, the receiving side of the diversity reception system required time and
After monitoring the location and selecting the optimal receiving system, reception is performed, but synchronization may be lost due to noise such as fading and multi-pulse peculiar to HF lines, and the synchronization phase must be corrected. However, since there is no effective method to follow the synchronization deviation, there is a lot of erroneous data, and the code distortion is large, making it difficult to receive high-quality data in series.

(Object of the Invention) An object of the present invention is to automatically select a receiving system with good S/N and to eliminate the above-mentioned drawbacks.
It is an object of the present invention to provide a received data detection method that continuously ensures good line quality by tracking and correcting synchronization deviations and disturbances in synchronization correction due to noise such as fading and multi-pulse peculiar to the line.

(Structure and operation of the invention) When transmitting data via an HF line, the present invention selects an optimal wave from among multiple waves, no matter how geographically scattered mobile stations on the receiving side are. With the polarization plane incidence angle/space diversity reception method, the S/N of multiple reception systems is always compared bit by bit, the better reception system is selected and the data is output, and the bit synchronization on the reception system side is also ensured. It enables tracking correction, improves the bit error rate, and prevents noise disturbances caused by fading, multipulse, etc. that occur on HF lines, but also provides bit-synchronized received data that is effective even against short-term noise occurrences. It is characterized by detection. Moreover, this method can be applied to any modulation/demodulation method receiving apparatus, and in particular, it has been realized that data reception can be performed by securing a continuous high-quality line for a plurality of mobile stations in a wide area.

The present invention will be explained in detail below with reference to the drawings.

FIG. 1 shows a fixed station A to which the present invention is applied.
and mobile stations B ₁ , B ₂ , B ₂ ...B _o receive radio frequency f ₁ in the HF band,
When transmitting and receiving digital data using f ₂ … f _o ,
FIG. 2 is a system diagram of a communication system when mobile stations B ₁ , B ₁ , B ₁ , B ₄ . . . _Bo perform similar transmission and reception.

FIG. 3 shows an example of the hardware configuration on the transmitting side of a fixed station or mobile station, where 31 is a transmitting terminal such as a computer or a teletypewriter, and 32 is a modulator for transmitting the digital code from the transmitting terminal 31 at radio frequency. MOD), transmitter TX, antenna 33
Sent by Usually FSK (frequency deviation) or
The PSK (phase shift) modulation method is adopted, and in order to avoid the effects of interference, multipath, fading, etc. in the transmission path, the modulation rate per channel is 100 to 150 bps (bit) within the transmission band. /s).

FIG. 4 is a system diagram of the receiving system, where 1 is a case where reception is performed using one antenna 41 and a receiver RX, and 2 is a system diagram of two systems of antennas 44, 45 and a receiver to which the present invention is applied.
FIG. ₂ is a block diagram of a polarization plane incidence angle/space diversity receiving system in which RX 1 and RX ₂ are provided. 1
42 is a demodulator (DEM) for demodulating and detecting the received signal, and 43 is a receiving terminal such as a computer or printer. 2 is the output of receiver RX ₁ and RX ₂ ,
The signal is input to a demodulator (DEM) 46. in this case,
It detects whether the receiving system of RX ₁ or RX ₂ is good by comparing the S/N of the received data bit by bit, switches the receiving system, and outputs it to the receiving terminal 47. There are various modulation and demodulation methods for data transmission, but the following
The case of the FSK method will be explained.

FIG. 5 shows details of the demodulator 46 of FIG. 42 as a first embodiment of the present invention.
The figure shows an example of the configuration of a reception demodulation/detection circuit for FSK modulated waves using the diversity reception method when only one subchannel is assigned to each transmission band of f ₁ , f _{2 .} . . _fo . A demodulator for subchannel CH1 connected to antenna 51 and receiver RX ₁ , a demodulator for subchannel CH21 connected to antenna 52 and receiver RX ₂ , and two receiving systems.
It consists of a synchronous circuit section that is common to RX ₁ and RX ₂ .

FIG. 7 shows details of the demodulator 46 of FIG. 4 2 as a second embodiment of the present invention, in which a plurality of subchannels CH1 in the transmission band Δf shown in FIG.
(f ₁₀ ) to CHn (f _1o ) are arranged and is a configuration example diagram of a reception demodulation/detection circuit for receiving and demodulating multi-channel data subjected to FSK modulation of 100 to 150 bps for each subchannel.

Figure 8 shows the signal spectrum per subchannel of the FSK modulated wave, and the vertical axis shows the level height.
f _p1n is the mark frequency, and f _p1s is the space frequency. The modulator converts the input binary digital signal into mark and space frequencies to produce a modulated signal. f ₀₁ is the center frequency of f _01n and f _p1s ,
If the S/N on the receiving side deteriorates, the f ₀₁ component in the common noise region of f _p1n and f _p1s increases, and the spectrum changes as shown from 1 to 2 in FIG. 8. Therefore, on the receiving side, the signal components (S) of f _p1n and f _p1s are used to determine the S/N.
The difference in the noise component (N) of f ₀₁ is integrated and used as an S/N signal. This S/N signal performs synchronization control on whether or not to perform diversity switching and bit synchronization correction on a bit-by-bit basis. However, in order to prevent malfunctions due to noise, bit synchronization correction is performed only when the value of the S/N signal is above a certain value.

As a first embodiment of the present invention, the configuration and operation of a receiving apparatus for low-speed FSK data transmission in which only one subchannel is set in the transmission band Δf will be explained in detail with reference to FIG.

In Fig. 5, the receiver RX ₁ is connected to the demodulation/detection circuit for one channel of CH1, and the other receiver RX ₂ for diversity reception is connected to the demodulation/detection circuit for one channel of CH21. . CH2
Since the demodulation/detection circuit No. 1 has the same circuit configuration as CH1, a detailed diagram thereof will be omitted. In the RX ₁ receiving system, 53 is a common amplifier, and 54, 55, and 56 are mark frequency f _p1n , center frequency f ₀₁ , and space frequency f _p1s, respectively.
This is a bandpass filter that extracts each component of . In the case of low-rate data transmission with only one channel in the transmission band Δf, the mark frequency f _p1n and the space frequency f _p1s can be adjusted by taking into account the fading width of the HF line and shifting the center frequency f ₀₁ by, for example, ±200 Hz. Set. In this case, the mark frequency f _p1n and the bandwidth Δfm, Δfs of the band filter that extracts the space frequency f _p1s
are set at approximately 50 to 75 Hz, respectively. 57,5
Reference numerals 8 and 59 are amplifiers, and 501, 502, and 503 are diode detectors, where the input is converted into a DC component, and detection outputs of a mark signal, a center frequency component, and a space signal are obtained, respectively. A differential amplifier 504 extracts mark and space signal components and sends them via an amplifier 505 to an integrator 506, where the signal components are integrated bit by bit. 507 is a sampling circuit which has the role of detecting the signal from the integrator 506. Also, 508 is a mark,
In the adder for both space signals f _p1n and f _p1s , the adder 509 takes the difference between the output (signal component) of this adder 508 and the output (noise component) of the diode detector 502 with the center frequency f ₀₁ . is amplified by an amplifier 510 as an S/N signal component, an integrator 511 integrates the S/N signal bit by bit, and a sampling circuit 512 extracts the S/N signal. 5
13 is a comparison circuit that compares the S/N signal of RX ₁ reception system CH1 from the sampling circuit 512 and the RX ₂ reception system CH1 signal.
The S/N signals of CH 21 are compared to select the better receiving system, and the data output of the receiving system with the better S/N is output to the switch 514 as a switching signal bit by bit. In this way, a diversity receiving system can be realized in which the receiving system is switched by comparing S/N signals in bit units.

One synchronization circuit provided in common for both RX ₁ and RX ₂ receiving systems includes a crystal oscillator 516 and a frequency divider 51.
7. Timing pulse generator 518, differentiation circuit 515 that receives and differentiates the output of CH1 sampling circuit 507 of RX ₁ reception system, CH of RX ₂ reception system
A differentiation circuit 520 that receives and differentiates the outputs of 21 similar sampling circuits, and conversion point pulses 1 and 2 obtained from the respective differentiation circuits 515 and 520.
There is a switch 519 for selecting one of the two, and the selected conversion point pulse operates the timing pulse generator 518 to take out the quench pulses CK1, CK21 and the sampling pulses CK2, CK22. These quench pulses CK2 and CK21 and sampling pulses CK2 and CK22 are CH1 and CH1, respectively.
21 integrator and sampling circuit.

Next, as a second embodiment of the present invention, a plurality of subchannels CH1 (f ₀₁ ) in the transmission band Δf in FIG.
A receiving apparatus for low-speed FSK data transmission in which CHn (f _1o ) is arranged and has a demodulation/detection circuit for each subchannel will be explained in detail with reference to FIG. Figure 7 receiver
Demodulation and detection circuits for each subchannel of CH1 to CHn are branch-connected to RX ₁ via a distributor 721 that distributes received data to each subchannel, and similarly to RX ₂ , the other receiver for diversity reception. The demodulation/detection circuits of each subchannel of CH21 to CH2n are branch-connected via a distributor 722. The configuration and _operation of the demodulation/detection circuit for each subchannel are the same as in the first embodiment shown in _FIG . One of the subchannels of the receiving system, for example, CH1 and
Select CH21 and check the S/N in bit units of the received data.
The signals are compared by a comparison circuit 713, a better receiving system is selected, and a switch 714 switches the received system to take out the output signal. For example, when setting up 16 subchannels (n=15) at 110Hz intervals in the transmission band Δf=3kHz, the setting of the subchannels is ±45.5 with respect to the center frequency f _1o (n=0 to 15) of each subchannel. The mark and space frequencies are determined by the shift width of Hz, and these band filters 74, 7
The bandwidths of 5 and 76 are each about f _1o ±10 Hz.

Quench pulses CK1, CK21 and sampling pulses CK2, CK22 supplied to the integrators and sampling circuits of CH1 and CH21 are supplied to the differentiating circuits 715, 720 and the switch 71 as in the case of FIG.
9, a crystal oscillator 716, a frequency divider 717, and a timing pulse generator 718. 723,724 are CH1~CHn
This is a code processing circuit for converting digital signals demodulated and detected for each subchannel of CH21 to CH2n into parallel to serial and outputting the converted signals to the switch 714.

FIG. 9 is a time chart of received data for the embodiments shown in FIGS. 5 and 7, but since the operation is the same in both embodiments, the case in FIG. 5 will be described. 1 and 2 in the diagram are two receiving systems
In the demodulation and detection output waveforms of the subchannels simultaneously received by RX1 and _RX2 , 1 is the output of the differential amplifier 504 of the RX ₁ receiving system, 2 is the output of a similar circuit of the RX ₂ receiving system, and if 1 bit length is T, then If the symbol rate per subchannel is 75bps, T = 1/75
13.3ms (20ms at 50bps). 3 is a waveform obtained by integrating the received data of the RX ₁ receiving system by the integrator 506, and 4 is a waveform obtained by integrating the S/N signal by the integrator 511. Further, 7 and 8 are output waveforms of the same integrator in the RX ₂ receiving system. An important feature of the present invention is that the clocks that trigger sampling of data "1" and "0" from this integration time and the integration result of step 3 are synchronized bit by bit for each receiving system of RX ₁ and RX ₂ . one of. In other words, 5 is the quench pulse CK for determining the integration time per bit.
1, and 6 is a sampling pulse CK2 used for detecting the sign of "1" or "0" or determining the S/N for each bit. In addition, in the RX ₂ receiving system, CK1
corresponds to CK21, and CK2 corresponds to CK22.

9 was taken out from the sampling circuit 507
This is the data signal waveform of CK1 of the RX ₁ receiving system, and is input to the switch 514 as output data, and at the same time is input to the differentiating circuit 515 for use in synchronization correction. 10 is the waveform of the conversion point pulse 1 obtained from the differentiating circuit 515 and is input to the switch 519.
Similarly to the RX ₁ receiving system, in the RX ₂ receiving system, when the integrator output waveform 7 of the CH21 data signal passes through the sampling circuit and becomes a waveform corresponding to 9, which is input to the switch 514 as CH21 data, it is differentiated at that time. It is also input to the circuit 520, and the conversion point pulse 2 corresponding to the waveform of 10 is extracted and input to the switch 519. The conversion point pulse with a better S/N selected by the switch 519 activates the timing pulse generator 518 of the synchronous circuit as described above, and generates the quench pulses CK1 and CK21 and the sampling pulse CK.
2. Create CK22. That is, extracting the bit conversion point from the received detection output data signal 9,
The phase correction of the quench pulse CK1 in Fig. 5 and the sampling pulse CK2 in Fig. 6 is always performed for each receiving system of RX ₁ and RX ₂ .
2, CK21, and CK22 correspond to this. RX ₁ and
Which bit of RX ₂ is to be adopted is determined by determining the S/N signals of both receiving systems in the comparison circuit 513 as described above, and operating the switch 514 for each bit using the resulting switching selection signal. Output the data signal of either receiving system. These will be explained in more detail below.

A sampling circuit 512 samples and outputs the S/N integrated outputs of each receiving system shown at 4 and 8 in FIG. A switching signal for making the output of the receiving system the selected output is sent to the switching device 514. On the other hand, the differentiating circuit 51
The phase correction of the clock system by the conversion point pulse from 5,520 is also performed by the switch 519 so that bit synchronization is performed by a system with a good S/N ratio for each bit.
Then, bit phase correction is performed by selectively outputting a conversion point pulse of a system with a good S/N ratio. in this way
Even if one common bit synchronization circuit is provided for both RX ₁ and RX ₂ receiving systems and the output is switched bit by bit using diversity reception, the difference in bit width is small and the sign distortion is small, so the circuit configuration Extremely economical.

Next, bit synchronization correction, which is a major feature of the present invention, will be explained.

In the bit synchronization correction of the present invention, data changes from "1" to "0" or "0" by passing the data code after demodulating and detecting the received input signal through a differentiation circuit.
This method provides a method of extracting the conversion point (bit separation) pulse when the signal changes from 1 to 1, and correcting the phase of the clock pulse on the receiving side using the conversion point pulse as a reference.

The clock pulse on the receiving side is the original crystal oscillator 5.
16 is frequency-divided by a frequency divider 517.
For example, when the subchannel transmission speed is 75 bps, it is 75 Hz (period T=1/75=13.3 ms), and when it is 50 bps, it is 50 Hz (T=20 ms). This clock pulse is connected to the quench pulses CK1 and CK21, which ultimately determine the integration time mentioned above, and the data and S/N.
The sampling pulses CK2 and CK22 are used to sample and detect the signal (determine whether it is 1 or 0), and the phase timing thereof is corrected bit by bit by the conversion point pulse.

In addition, there are cases where the phase relationship between the conversion point pulse and the synchronization clock on the receiving side is largely or slightly out of phase, but in the former case, coarse adjustment correction,
In other words, the pull-in width (or correction width) of the synchronization clock on the receiving side is increased (in the present invention, as an example, when one conversion point pulse is 75 bps, it is 0.833 ms, and when it is 50 bps, it is 0.833 ms).
1.25ms correction), and in the latter case, conversely, make fine adjustment, that is, make the correction width smaller (1/2 ⁴ of coarse adjustment, i.e.
The correction width is 0.052ms at 75bps and 0.078ms at 50bps). Therefore, it is possible to determine whether the phase of the conversion point pulse extracted from the received data code is ahead or behind the receiving side synchronization clock (75 Hz for 75 bps, 50 Hz for 50 bps), and at the same time determine whether the phase is ahead or behind. The subsequent phase correction process is performed depending on the width (coarse adjustment area or fine adjustment area).

FIG. 10 summarizes the processing method of the synchronization clock for phase correction depending on the conditions of the conversion point pulse with respect to the synchronization clock. In this way, when switching between coarse adjustment and fine adjustment, the correction speed is increased at times, and at other times the correction speed is decreased to perform phase delay/advance correction, thereby always detecting received data quickly and at accurate timing. be able to.

In addition, in order to prevent a malfunction in which the noise conversion point is extracted and phase correction is performed when the S/N is poor and the noise component is large, the setting is set so that phase correction is not performed when the S/N is less than a specified value. has been done.

Normally, when reception data is first input, phase correction is performed quickly by coarse adjustment operation, and once synchronization pull-in is performed to some extent, stable synchronization correction is performed thereafter by fine adjustment operation. In addition, in order to perform stable phase correction in this way, for coarse adjustment synchronization correction, even if one or two conversion point pulses from the received data arrive, the fine adjustment operation is performed without immediately switching from fine adjustment to coarse adjustment operation. Then, the coarse adjustment operation is started only when several conversion point pulses for coarse adjustment come in succession, and it is considered that the coarse adjustment operation is carried out to reach the fine adjustment range.
The case where the received data transmission rate is 75 bps will be explained below. However, the numbers in parentheses are for 50 bps.

FIG. 11 shows a time chart for explaining the phase shift and correction between the received data code and the synchronization clock on the receiving side. 11 is the output of the sampling circuit 507 or 707, and is a code arrangement when the incoming received data code is [01011010...]. Reference numeral 12 indicates the bit conversion point pulses P ₁ to _{P 6} after being differentiated by the differentiating circuits 515, 520 or 715, 720. 13, 14, and 15 are relative to the synchronization clock frequency. 13 is when the conversion point pulse is ahead by t ₁ , 14 is when the phase delay and lead are ideally 0, and 15 is when the conversion point pulse is t. This shows that it is behind by ₂ . Also, A,
B and C indicate in which slit (region) the phase shift of the synchronization clock is located with respect to the conversion point pulse P _3.B is determined to be the fine adjustment region, and A and C are determined to be the coarse adjustment region. Subsequent phase correction is performed. 11th
In the illustrated example, 13 is fine adjustment pull-in, and 15 is coarse adjustment pull-in.

FIG. 12 is a more detailed block diagram of the timing pulse generators 518 and 718 of FIGS. 5 and 7, and is a circuit block diagram for explaining the operation of phase correction according to the present invention.

121 in FIG. 12 is the original crystal oscillator for producing timing pulses (516 in FIG. 5,
(equivalent to 716 in Figure 7) 2457.6kHz (1638.4kHz)
The frequency divider 122 generates a timing pulse to ensure the stability of final bit synchronization. The frequency divider 122 divides the frequency by ^1/27 = 1/128, and the clock frequency is 2457.6 x ^1/27 = 19.2kHz.
(12.8kHz). When the repeated clock pulse of 1 is input to the next frequency divider 125, the switch 124 controls to add one clock pulse in the case of detecting the advance of fine adjustment correction, and adds one clock pulse in the case of detecting the delay of fine adjustment correction. It controls to erase one clock pulse and outputs it. In this way, the phase of the clock pulse after the next frequency divider 125 will be advanced in the former case, and delayed in the latter case. (This is the first
125 is a 1/2 ⁴ frequency divider, and is 19.2kHz x 1/2.
2 ⁴ = 1.2kHz (800Hz) repetition frequency.
The switch 126, like the switch 124, is a coarse adjustment circuit that has the function of adding or erasing one clock pulse.

In other words, the width of the final synchronization clock phase correction is different depending on whether pulse addition or deletion is performed in a high repetition frequency region or in a low repetition frequency region. is coarse adjustment correction with a large correction width. 12
7 is a frequency divider to create the final 75bps (50bps) bit timing pulse, which is divided by 1/2 by ⁴ ,
There is a synchronization clock 75 for bit synchronization correction.
Hz (50Hz) is output.

On the other hand, after the S/N is detected from the line, a conversion point pulse arrives only when the S/N is better than the specified value, and is input to the lead detection circuit 128 and the delay detection circuit 129, and the phase with the synchronization clock input from the line. Determine the relationship. In other words, it is determined whether the phase is advanced or delayed as shown in FIG. to advance the phase of subsequent clock pulses of the frequency divider. Further, under the conditions shown in FIG. 11 and 15, the delay detection circuit 129 operates, the pulse cancellation circuit 1202 cancels one pulse, and delays the phase of the subsequent clock frequency of the frequency divider. The outputs of the addition circuit 1201 and the erasure circuit 1202 are connected to the switch 12
3, the control signal input through the line from the coarse/fine adjustment judgment circuit 1208 causes the frequency divider 125 to pass through the switch 124 in the case of fine adjustment, and the switch 126 in the case of coarse adjustment. The signal is then input to the frequency divider 127.

Next, the determination of coarse adjustment/fine adjustment will be explained. 12
03 to 1208 are circuit configurations for making the determination, and the conversion point pulse is input to an all counter 1205, a coarse adjustment slit 1203, and a coarse adjustment slit 1204 via a line. At the same time, a synchronization clock of 75Hz (50Hz) is input via the line.
Hz), and as explained in FIG. 11, when the conversion point pulse _P3 is in the slit A, it passes through the coarse adjustment slit 1203, and when it is in the slit C, it passes through the coarse adjustment slit 1204. The signals are input to slit counters 1206 and 1207, respectively. When the all counter 1205 and the slit counters 1206 and 1207 count up to a preset number, they are output as a control signal to the coarse/fine adjustment judgment circuit 1208 via the line , and the coarse/fine adjustment is performed. Determine which of the following applies.

Therefore, no matter where the conversion point pulse P ₃ is with respect to the synchronization clock 75 Hz (50 Hz), the all counter 1205 performs a counting operation, and if the conversion point pulse P ₃ is at the position shown in FIG. When the slit counter 1206 is at position C, the slit counter 1207 operates to count. These two slit counters 1206 or 120
If the number of counts of 7 is large, it will be judged as rough adjustment, and the reception clock will be 75Hz (50Hz) for the received conversion point pulse.
Hz) to significantly advance or delay the phase. When the two slit counters count the same number of conversion point pulses, a control signal is immediately output to reset all counters, so fine adjustment will not occur unless the conversion point pulses are concentrated at position B. Further, when there are about one or two conversion point pulses in the slits A and C, the two slit counters are set so as not to output control signals. That is, once entering the fine adjustment region, only the outputs of all counters are set, and thereby the coarse adjustment/fine adjustment judgment circuit 1208 sets the output of the three counters 1205.
1207 is reset again, the phase is corrected only by fine adjustment lead/lag judgment and enters the stable region.

If the phase correction described above is performed, synchronization can be quickly achieved at the start of data reception, and when the conversion point pulse of received data is erroneous by 1 or 2 bits due to interference, etc., the synchronization can be easily corrected by coarse adjustment. I will never do that. In addition, in the state of continuous data reception, the fine adjustment operation performs fine adjustment lead/lag correction within the stable region, so that correct data can always be output. Quench pulses CK1, CK21 and sampling pulse CK with synchronization correction of these operations
2. Executed at the correct timing by CK22.

Next, a specific bit synchronization correction method will be explained.

FIG. 13 is a time chart illustrating the operation of adjusting the phase correction when the delay detection shown in FIG. 11 and FIG. 15 is performed, and only one bit is shown enlarged. In other words, the conversion point pulse of the received data code is applied to the synchronization clock 15 on the receiving side in FIG.
The rough adjustment correction by synchronization pull-in when _P3 is delayed will be explained. 21-1 in FIG. 13 shows a synchronizing clock pulse of 75 Hz (50 Hz) before correction, and the repetition period T is 13.3 ms (20 ms). 21-2
is 75Hz (50
Hz), and the period T is equal to 21-1, which is 13.3 ms. In the circuit block diagram of FIG. 12, this is the output of the final frequency divider 127. The lines in FIG. 12 are connected so that both clock pulses 21-1 and 21-2 are input to the lead detection circuit 128 and the delay detection circuit 129, and the conversion point obtained by differential waveform shaping of the received data code. pulse 2
Proceed by determining the phase relationship with A of No. 2, and decide which one to detect the delay. In the example of FIG. 13, the delay detection circuit 12
9 stands up.

FIG. 14 shows the delay detection circuit 129 of FIG.
In the circuit configuration diagram for explaining the operation of the erasing circuit 1202, an output waveform 23 is obtained by the delay detector 141 from the conversion point pulse 22 and the synchronizing clock pulses 21-1 and 21-2, and 24 On the output line of the NAND circuit 142, the output of that NAND (“0” between “1” and “1”) is D.
type 1 pulse generator 143. Here, FIG. 13, 24 shows the same 75 Hz (50 Hz) clock pulse as 21-1 shown for ease of explanation.

On the other hand, the crystal oscillator 121 and frequency divider 1 in FIG.
When the clock pulse 600Hz (400Hz) - π/2 of Fig. 13, which is obtained by delaying the timing clock pulse 600Hz (400Hz) generated by 22 and 125 by π/2 radians, is input to the line C. 13 As shown in the time chart of FIG. 26, one pulse is generated and output to the second line. This pulse width is equal to 25 clock pulse widths,
1/600≒1.67ms (1/400≒2.5ms). This one
The pulse passes through the line 2' to the delay detector 141.
is input and reset.

The timing clock pulse 27-1 generated by frequency division by the frequency divider 125 is input to the line E, and this is input to the 1 pulse of 26 and the AND circuit 144.
27-2 as shown in 27-2.
The clock pulse 27-1 of 1200 Hz (800 Hz) obtained by erasing one pulse of 1 a is output to the line and input to the switch 123. The above are the functions of the late detection circuit 129 and erasure circuit 1202 shown in FIG.

The output 27-2 is outputted to the coarse adjustment control line via the switch 123, and then passed through the switch 126 to the waveform 27-2, 1200Hz (800Hz) with only one pulse of a shown in the waveform 27-1 deleted. After that, the frequency is divided by the frequency divider 127 and the frequency is divided to 28 600Hz.
(400Hz), 29's 300Hz (200Hz), 30's 150Hz
(100Hz) are produced one after another, and finally, the corrected synchronizing clock pulse 75Hz (50Hz) shown in 31 is obtained.

That is, as can be seen by comparing the waveforms of 21-1 and 31 in FIG. 13, the phase of 21-1 can be delayed by _t21 by the conversion point pulse I of 22. In the case of coarse adjustment, _t21 is 0.833ms (1.25ms).
In other words, one conversion point pulse takes 0.833ms during coarse adjustment.
(1.25ms) delay or lead can be corrected.

Next, FIG. 15 is a time chart when the phase advance is corrected by fine adjustment using the circuit in FIG. 12 when the lead in FIG. 11 and 13 is detected, and is shown enlarged by one bit. . That is, the 11th
Fine adjustment correction by synchronization pull-in when the conversion point pulse _P3 of the received data code is ahead of the synchronization clock 13 on the reception side shown in the figure will be explained.
41 in FIG. 15 shows the synchronization clock pulse before correction, and the repetition period T is T=13.3ms (20ms). The circuit block diagram of FIG. 12 shows a line clock waveform. 42 is a conversion point pulse based on the received data code of the line in FIG. 12. When the phase condition of the conversion point pulse and the synchronization clock 41 is detected, both digital codes are "1", so the advance detection circuit detects the conversion point pulse. 128 operates and rises as shown in the time chart of FIG. 15 43. Reference numeral 44 denotes a clock whose phase is shifted from the synchronizing clock 41 by π radians, and is used as a conditional clock for generating one pulse as described later.
The time charts 45 to 51 in FIG. 15 have been described above with the range of time axes expanded from those in 41 to 44 to make the explanation easier to understand. 45 is
With a repeating clock of 38.4kHz (25.6kHz), the first
2457.6kHz oscillated by crystal oscillator 121 in Figure 2
This is the clock frequency obtained by dividing the output of (1638.4kHz) by the frequency divider 122. This is further divided by 1/2 using the same frequency divider 122 to obtain 46/19.2.
(12.8)kHz is obtained. 47 is a clock with a phase delay of π/2 radians from 46, which is 19.2 (12.8)k.
Hz-π/2.

FIG. 16 is a circuit configuration diagram for explaining the operation of the hex detection circuit 128 and the additional circuit 1201 in FIG. 12. A conversion point pulse 42 and a 75Hz clock 42 for synchronization are input to the input of the lead detector 161, and the phase conditions of both are judged and at the time of the conversion point pulse, the lead detector 161 is activated and its output is The output waveform shown in FIG. 15 43 is obtained. This output 43 and 44 75Hz (50Hz) - π clock
NAND circuit 162 (output “0” at “1” and “1”)
16, a clock waveform shown by an arrow in FIG. 16 appears on the output chip line, which becomes the D input of a 1-pulse generator 163 consisting of a D-type flip-flop circuit. When the clock of 19.2 kHz (12.8 kHz) - π/2 shown in FIG.
Pulse width shown in 8 1/19.2 (12.8) kHz≒0.052
One pulse of (0.078) ms is obtained. The advance detector 161 outputs a pulse having an opposite phase to 48 output from the Q output of the 1-pulse generator 163 to the line N, and is reset to the original state via the reset line N'. 1 pulse 48 output to Linene and
EXCLUSIVE 19.2 (12.8) kHz clock 46
NOR circuit 164 (input is “1” in truth table,
When the output is “1” or “0”, “0”, the output is “0”, and the input is “1”, “0” or “0”, “1”, the output is “1”), one pulse is generated. Figure 15 4 before and after
A clock to which one pulse is added as shown in 9b and 9c is obtained. This signal is output to the line shown in FIG. 16, passes through switchers 123 and 124, and thereafter corrects the phase of the clocks of frequency dividers 125 and 127. That is, the phase after clock b in FIG. 15 49 advances. This is Fig. 15 50, 51, 52 and 53
This is the time chart waveform. However, 52,53
The time interval on the horizontal axis is a time chart with an equal ratio of 41 to 44. 53 is the synchronization clock 75Hz (50Hz) after correction, and compared to 41 before correction, t ₁₁ = 0.052ms due to one conversion point pulse.
(0.078ms) synchronization pull-in is performed to correct the phase lead. The phase timings of sampling pulses CK2, CK22 and quench pulses CK1, CK21 are determined by the corrected clock pulses.

The output of one pulse generation in FIGS. 14 and 16 is input to the switch 123 in FIG.
When the correction width is small, that is, when fine adjustment is required, the signal is input to the frequency divider 127 via the switch 124.
25. In this example, coarse adjustment is 600 (400)
Hz, 9.6 (6.4kHz) during fine adjustment by correcting the phase of the clock pulse for synchronization.
75Hz (50Hz) is corrected and normal reception data is obtained.

As described above in detail with respect to the two embodiments of coarse adjustment using delay detection and fine adjustment using lead detection, the present invention is capable of converting the internal synchronization clock pulse of the receiving device into a conversion point pulse extracted from received data. , compare the mutual phase relationship for each bit, detect whether the slit width is A, B, or C in Fig. 11, determine the advance/lag and the deviation width at the same time, and coarsely adjust the deviation width. This is a received data detection method whose main feature is that it performs correction in two stages: /fine adjustment.

In this example, the bit synchronization correction method of the present invention is
Although the FSK modulation and demodulation method has been explained, the present invention can be applied to any other modulation and demodulation method after demodulation and detection, and synchronization is relatively quick especially at the start of reception even when using a wireless line with poor line quality such as an HF line. It is possible to perform retraction, and stable reception data detection is possible by continuing synchronization correction by fine adjustment during reception. Furthermore, since S/N signal detection control is provided, there is no malfunction of bit synchronization correction due to noise. Moreover, even in the case of diversity reception with multiple reception systems, one bit synchronization circuit can be switched and used in common, making the circuit configuration economical.
Moreover, the sign distortion of the final output can also be reduced.

(Effects of the Invention) According to the present invention, mobile objects, including particularly fast-moving aircraft and ships scattered over long distances, receive data that is unilaterally and continuously transmitted at multiple frequencies from a fixed station. It is possible to configure a high-quality wireless transmission line with minimal reception equipment, and it also improves the reception of conventional wireless lines, where continuous good reception was difficult because the receiving electric field changes from time to time. Significant improvements in quality, simplification of transmitting and receiving equipment, and improved transmission efficiency are significant effects of the present invention.

[Brief explanation of drawings]

Figure 1 is a communication system diagram between a fixed station and a mobile station implementing the present invention, Figure 2 is a communication system diagram between mobile stations implementing the present invention, Figure 3 is a configuration diagram of the transmission system, and Figure 4 is a diagram of the communication system between mobile stations implementing the present invention. 5 is a schematic diagram of a demodulation/detection circuit according to the first embodiment of the present invention, FIG. 6 is an example diagram of a modulated signal spectrum having multiple subchannels, and FIG. 7 is a diagram of the second embodiment of the present invention. FIG. 8 is a schematic diagram of a demodulation/detection circuit of a multi-subchannel receiving device as an embodiment.
An example of the signal spectrum of the FSK modulated wave, Figure 9 is a time chart of each part in the schematic diagram of Figure 5,
FIG. 10 is a judgment diagram of the synchronization phase correction process according to the present invention, FIG. 11 is a time chart of received data and synchronization clock for explaining the operation of the present invention, and FIG. 12 is a diagram showing the phase correction method of the present invention. FIG. 13 is a time chart for explaining the correction of the delayed phase according to the present invention; FIG. 14 is a circuit block diagram for explaining the method of correcting the delayed phase of FIG. 13; FIG. 16 is a time chart for explaining the lead phase correction according to the present invention, and FIG. 16 is a circuit block diagram for explaining the lead phase correction method of FIG. A...Fixed station, _B1 to _Bo ...Mobile station, _f1 , _f2 to _fo ...Transmission frequency, TX...Transmitter, RX, _RX1 , _RX2 ...Receiver, Δf...Transmission bandwidth, _f10 ~f _1o ...Subchannel frequency, A, B, C...Slit (area), 31...
Transmitting terminal, 32...Modulator, 33, 41, 44, 4
5, 51, 52, 71, 72... antenna, 42,
46... Demodulator, 43, 47... Receiving terminal, 53, 7
3...Common amplifier, 54, 55, 56, 74, 7
5, 76...Band filter, 57, 58, 59, 5
05,510,77,78,79,705,70
8...Amplifier, 501, 502, 503, 701,
702, 703...Diode detector, 504, 7
04...Differential amplifier, 508, 509, 708, 7
09... Adder, 506, 511, 706, 711
...integrator, 507,512,707,712...sampling circuit, 513,713...comparison circuit, 5
14,519,714,719,123,12
4,126...Switcher, 515,520,715,
720...Differential circuit, 516,716,121...Crystal oscillator, 517,717,122,125,1
27... Frequency divider, 518, 718... Timing pulse generator, 721, 722... Distributor, 723, 7
24... Code processing circuit, 128... Advance detection circuit, 1
29...Delay detection circuit, 1201...Additional circuit, 12
02...Erasing circuit, 1203...Coarse adjustment slit, 1
204... coarse adjustment slit, 1205... all counter, 1206, 1207... slit counter,
1208... Coarse adjustment/fine adjustment judgment circuit, 141... Delay detector, 142, 162... NAND circuit, 143, 1
63...1 pulse generator, 144...AND circuit, 1
64...EXCLUSIVE NOR circuit.

Claims (1)

[Claims] 1. When data is transmitted between a fixed station and multiple mobile stations or between mobile stations via a shortwave line, and the received data is demodulated and detected on the receiving side using a two-system reception diversity method, the difference between the signal component and the noise component is calculated in bit units. The S/N signal obtained by integrating the signal is compared for both receiving systems, and the better receiving system is selected bit by bit and the output is switched, and the received data code of the selected receiving system is differentiated. When the conversion point pulse arrives, the phase of the conversion point pulse and the phase of the 1-bit long synchronization clock obtained from the one source clock common to the two systems of reception through at least two stages of frequency dividing circuits are determined. detecting the amount of lead, lag, and phase difference of the phase of the synchronizing clock with respect to the phase of the conversion point pulse,
Control is performed for the at least two-stage frequency dividing circuit to generate one pulse when making a lead judgment, and to eliminate one pulse when making a delay judgment, and when the amount of the phase difference exceeds a predetermined range, the at least two-stage frequency dividing circuit is controlled. The pulse generation and the pulse erasure are performed in the frequency dividing circuit at the subsequent stage of the frequency dividing circuit, and when the amount of the phase difference is less than the predetermined range, the frequency dividing circuit at the preceding stage of the at least two stage frequency dividing circuit is performed. A received data detection system characterized in that it is configured to perform bit-by-bit phase correction by generating the pulses and erasing the pulses in a circuit.