JPH0367348A - Surface switch control system for received data memory - Google Patents

Abstract

PURPOSE:To reduce the load of the software of a processor by performing the surface switch control of a data memory set at the reception side in terms of hardware with use of an error check code. CONSTITUTION:A transmission processor 31 is provided with an error check code generating circuit 33 which produces an error check code from the communication data. This produced check code is added to the communication data and sent to a reception processor and received by an error check circuit 44. The circuit 44 checks the errors with use of the received error check code. When the occurrence of an error is detected, the surface switching operation of a received data memory 42 is stopped. Thus the communication data having an error is never read out to a processor 43. As a result, the processor 43 always reads the correct communication. Then the load of the software of the processor 43 can be reduced.

Description

[Detailed Description of the Invention] [W1 Required] A reception data memory consisting of at least two planes is provided on the reception processor side, and by sequentially switching the planes of this reception data memory, communication data transferred from the transmission processor side can be transferred. The present invention relates to a plane switching control method for a reception data memory in an interprocessor communication system configured to be read out to a reception processor side.

The purpose is to reduce the software load on the receiving processor by controlling the plane switching of the receiving data memory using a hardware circuit.

The transmitting processor is equipped with an error check code generation circuit that generates an error check code from communication data, and the error check code generated by this generation circuit is added to the communication data and transmitted, and the receiving processor measures the received error check code. An error check circuit for checking the occurrence of an error using an error check code is provided, and the configuration is such that when the check circuit detects the occurrence of an error, switching of the planes of the received data memory is stopped.

[Industrial F11 Field] The present invention relates to a plane switching control method for a received data memory in an inter-processor communication system.

For example, LAN (Local Area Network) is becoming faster and has a larger capacity.
The amount of information that must be processed by a processor within the computer is increasing, and the burden on the processor is increasing, and there is a need to shorten the information processing time. For this reason,
There is a need to be able to reduce the load on the processor as much as possible by executing surface switching control of the received data memory without placing a burden on the processor.

[Prior Art] Conventionally 9 For example, when MPU communication is performed between microprocessors in a device with a multiprocessor configuration, a receive data memory with a double buffer configuration (two-sided configuration) is prepared in the receiving device, and the memory surface of this receive data memory is Communication data is sequentially written by alternately switching sides, and the communication data is sequentially read out to the receiving processor from the memory side opposite to the writing side.

During this MPtJPt, if an error occurs in the content of the communication information due to an abnormality in the transmission path, etc. 9 If the plane is switched as usual and the write data is read from the reception data memory to the receiving processor, the error information will be loaded, causing a system communication error. For this reason, the receiving processor uses software processing to check whether an error has occurred, and determines whether or not side switching is possible so that when an error occurs, side switching is stopped.

[Problems to be Solved by the Invention] For this reason, the receiving processor must always monitor whether an alarm has occurred and perform surface switching control using software.

This processing increases the software load on the receiving processor. Particularly in systems such as large LANs where the processing load on the processor is large, the software burden of such surface switching control processing cannot be ignored.

Therefore, an object of the present invention is to reduce the software load on the receiving processor by controlling the plane switching of the receiving data memory using a hardware circuit.

CMeans to solve the problemJ FIG. 1 is a diagram explaining the principle of the present invention.

In the figure, 31 is a transmitting side processor, 32 is a transmitting data memory, 33 is an error check code generation circuit, 34 is a multiplexing section, 41 is a demultiplexing section, 42 is a receiving data memory, 43 is a receiving side processor, and 44 is an error checker. The circuit 45 is a surface switching circuit.The surface switching control method of the received data memory according to the present invention is as follows.The receiving processor 43 II+ is equipped with a receiving data memory 42 consisting of at least two surfaces, and the receiving data memory 42 is sequentially operated. In an inter-processor communication system configured such that the communication data transferred from the transmitting processor 31 is read out to the receiving processor 43 side by switching the plane, the transmitting processor 31 side generates an error check code from the communication data. An error check code generation circuit 33 is provided, and the error check code generated by the generation circuit 33 is added to communication data and transmitted, and the reception processor 43 side has an error check that checks for error occurrence using the received error check code. A circuit 44 is provided, and when an error occurrence is detected in this inspection circuit, the received data memory 4
The second plane switching is stopped.

[Operation J: On the transmitting side, when transmitting communication data, the generation circuit 33 generates an error check code from this communication data, and the multiplexer 34
This error check code is added to the communication data and sent to the receiver.

On the receiving side, a separation unit 41 separates the communication data and an error check code, and an error check circuit 44 checks based on the error check code whether an error has occurred in the communication data due to a fault in the transmission path or the like. If no error has occurred, the plane switching circuit 45 alternately switches the planes of the received data memory 42 to write the received communication data to the received data memory 42 and from the received data memory 42 to the processor 43.
Read communication data to and from.

On the other hand, if the error check circuit 44 detects the occurrence of an error, the error detection is notified to the surface switching circuit 45,
Thereby, the plane switching circuit 45 stops switching the planes of the received data memory 42. This prevents error-generated communication data from being read by the processor 43, and allows the processor 43 to always read correct communication data without having to monitor the error occurrence itself. Processing is reduced.

[Example] The present invention will be described in detail below with reference to nine drawings. FIG. 2 shows an inter-microprocessor communication system using a receive data memory surface switching control method as an embodiment of the present invention.

The transmitting section of the communication device (mask side device) 1 includes a microprocessor 11, a two-sided transmit data memory section 12. Transmission command section 14. CRC check code generator 15. Multiplexer 1
It consists of 6 etc. The receiving section of the communication device (slave measuring device) 2 includes a microprocessor 21, a received data memory section 22, and a two-sided receiving data memory section 22. Reception command section 24. It is configured to include a CRC inspection section 25, a separation section 261, and a side switching signal generation section 27. Note that the communication device 1 is also equipped with a circuit similar to the receiving section of the communication device 2, and the communication device 2 is also equipped with a circuit similar to the transmitting section of the communication device 1. These figures are omitted here.

In the communication device I, the transmission data memory unit 12 is a memory in which MPU communication data to be transmitted is set by the microprocessor 11, and while communication data is being written to one memory surface, communication data is written from the other memory surface. Writing and reading are performed alternately so that the data is read out and transmitted via the multiplexer I6.

The transmission command section 14 is a circuit in which a transmission notification (transmission command CMD) is set by the microprocessor 11, and any data other than all "0" bits of the command is used as the transmission command CMD. The transmission command unit 14 sends a side switching signal to the transmission data memory 12, and also sends the set transmission command C.
The MD is sent to the multiplexing section 16.

The CRC check code generation section 15 is a circuit that generates a CRC code (cyclic redundancy code) for the communication data in the transmission data memory section 12, and the generated CRC code is sent to the multiplexing section 16.
sent to.

Multiplexing unit [6 is communication data DT from the transmission data memory 12, transmission command CMD from the transmission command unit 14,
This circuit multiplexes and transmits the CRC codes from the CRC check code generator 15.

In the communication device 2, the two-separation unit 26 separates the communication data DT, reception command CMD, and CRC code from the received signal, and stores the communication data DT in the reception data memory unit 22, the reception command CMD in the reception command unit 24, and the CRC code.
This circuit outputs the code to the CRC inspection section 25.

The reception data memory section 22 has two sides, and the writing and reading sides can be switched so that when the communication data DT is written on one side, the communication data already written on the other side is read out by the microprocessor 21. It is designed to take place alternately.

The reception command section 24 is a circuit in which the transmission command CMD sent from the transmitting side is set as the reception command CMD, and the contents of the reception command CMD are read by the microprocessor 21 as appropriate.

The CRC inspection unit 25 is a circuit that inspects whether an error has occurred in the received data due to a failure occurring in the transmission path based on the received CRC code.When an error occurs, an alarm (CRC error detection) is sent to the side switching signal generation unit 27. signal) ALM
Send out.

The plane switching signal generation unit 27 is a circuit that normally outputs a plane switching signal to the received data memory unit 22 to alternately switch these planes, but it is configured to stop this plane switching when an alarm ALM is received. ing.

FIG. 3 shows the detailed configuration of the surface switching signal generation section 27 and the reception data memory section 23. This circuit distributes the write address generated by the transmission system address generation section 278 and the read address generated at the MPU system address generation section 279 by selectors 272 and 273, respectively, and distributes them to the received data memory 22. ．． 22. Addresses are input alternately to selectors 272 and 27.
3 is controlled by the control signal CN from the surface switching control section 271.
It is done by T.

In addition, the received data memory 22 . ．． 22□ alternately inputs transmission system data (write data from the transmission path), while 3-state buffers 276 and 277 input data to the reception data memory 2.
2. ．． MPLI data from 22□ (processor 21
The state of these three-state buffers is controlled by a control signal CNT from the plane switching control section 271.

The side switching control section 271 includes the received data memory 22, . 2
A switching timing signal CTG that determines the timing at which 2□ performs surface switching and an alarm A from the CRC inspection unit 25.
LM is input, and the control signal CNT is controlled based on these signals.

The operation of the embodiment device will be explained below.

First, in the communication device 9 1 , MPU communication data is set in one side of the transmission data memory section 12 by software processing of the microprocessor 11 . After completing this communication data setting, the processor 21 sends the transmission command section 14
A transmission command CMD (data other than all "O") is written in.

When this transmission command CMD has been stored, a plane switching signal is output to the transmission data memory section 12 to switch the plane of the transmission data memory section 12, and the communication data DT written therein is passed through the multiplexing section 16. It is transmitted to the communication device 2 side.

At the same time, a transmission command CMD is sent from the transmission command section 14 to the multiplexing section 16, where it is multiplexed and transmitted so as to be added to the communication data DT. This transmitted transmission command CMD is used as information to notify the receiving side of the MPUJ communication data loss data.

At the same time, the CRC check code generation unit 15 checks the CRC of the MPU communication data read from the transmission data memory 12.
The check is performed to generate a CRC code, which is added to the MPU communication data DT and the transmission command CMD by the multiplexer 16 and transmitted.

In the receiving device 2, the signal received from the transmitting device 1 is separated into communication data DT and reception command CMD by the demultiplexing unit 26.
and CRC code, and store each in the received data memory 2.
5.

The received data memory section 22 stores the received communication data DT,
It is accumulated by writing on one side which is selected alternately.

At the same time, the CRC checker 25 checks the received CRC code to determine whether an error has occurred in the received communication data DT.

When an error is detected as an error, an alarm ALM is output to the surface switching signal generation section 27.

During normal operation without errors, the side switching signal generation unit 27 writes the received communication data DT to one side of the received data memory unit 22, and at the same time writes the communication data already written from the other side to the microprocessor 21011. The generation of the surface switching signal is controlled so that the surface switching signal is read, but when an error occurs and an alarm ALM is input, this surface switching signal is fixed to prevent surface switching in the received data memory section 22. As a result, if the received data is abnormal, memory side switching is stopped, and abnormal reception data is prevented from being read into the microprocessor 21 side. As a result, only normal communication data is always shown to the microprocessor 21.

The microprocessor 21 monitors the data written in the reception command section 24, and this is the reception command CM.
When it is detected that it is D, MPLI communication data is read from the received data memory section 22.

Note that MPU communication data that was not read out by the microprocessor 21 due to an error occurrence will be recorded, and the microprocessor will take countermeasures at a later date.

Numerous variations are possible in embodiments of the invention. For example, in the above-mentioned actual journey example, a CRC code was used as a code for checking the occurrence of errors in MPU communication data, but of course the code is not limited to this, and other error checking codes such as parity check codes can also be used. Available.

Furthermore, although the data memory for transmission and reception has a two-sided structure, it is of course possible to have a structure of 3[n or more.

[Effects of the Invention] As explained above, according to the present invention, the error detection of MPU communication data is performed by a hardware circuit, and the control unit is configured to switch the plane of the double buffer when normal and to switch planes and return to the mountain when abnormal. Therefore, the microprocessor I11 always sees only normal communication data, and the microprocessor only needs to read the communication data without being aware of whether or not there are errors. It becomes possible to reduce the load.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a block diagram showing an inter-processor communication system using a plane switching control method of a received data memory as an embodiment of the present invention; FIG. 3 is a block diagram showing the double buffer surface switching control circuit portion in the embodiment. In fig. 1.2...Communication device 11.21...Microprocessor 12...Transmission data memory 14...Transmission command section 15...CRC inspection check code generation date...Multiplex section 22... Received data memory section 24... Reception command section 25... CRC inspection section 26... Separation section 27... Plane switching signal generation section 271... Plane switching control section 272, 273... Selector 274 ~277...3 state buffer 278...
Transmission address generator

Claims (1)

[Claims] A reception data memory (42) consisting of at least two planes is provided on the reception processor (43) side, and by sequentially switching the planes of this reception data memory (42), the transmission processor (31) side In an inter-processor communication system configured such that the communication data transferred is read out to the receiving processor (43) side, the transmitting processor (31) side includes an error check code generation circuit (which generates an error check code from the communication data). 33), the error check code generated by this generation circuit (33) is added to the communication data and transmitted, and the receiving processor (43) side is equipped with an error check code that checks for error occurrence using the received error check code. A surface switching control method for a received data memory, comprising a circuit (44) and configured to stop switching the surface of the received data memory (42) when the occurrence of an error is detected by the inspection circuit (44). .