JPH0363278B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal processing apparatus for generating television synchronization signals for combination with a video signal being processed, and more particularly, the present invention relates to a video signal processing apparatus for generating a television synchronization signal for combination with a video signal being processed. The present invention relates to a television synchronization signal waveform generator in which various synchronization signals to be combined with a video signal are digitally generated.

SUMMARY OF THE INVENTION In a preferred embodiment, a digitally generated synchronization signal is substituted for the original synchronization signal of the television signal. These digitally generated synchronization signals are generated synchronously with the digitization of the video portion of the television signal, and the digitally generated synchronization signals are also multiplexed into the stream of digital video data at appropriate blanking intervals. be done. The inventive scheme uses a first digital signal generator to generate a plurality of digital signals representative of the peak amplitude of the desired synchronization signal. A second digital signal generator generates a second digital signal representing the desired edge shape for the synchronization signal being generated.
synchronously generate multiple digital signal values. The first and second digital signal number generators are synchronized with a clock that controls the input of the digitized video signal to the system of the present invention to generate the first and second plurality of digital signal values. A reference signal is received that indicates when and the time intervals to be used. During the appropriate blanking interval, the first
and a second plurality of digital values are multiplexed and their product output to be added to the input video signal. During times other than blanking intervals, incoming digitized video is multiplied by a digital gain value. This resulting stream of digital values is provided to a digital-to-analog converter. The resulting analog level signal is passed through a low pass filter with specific characteristics to obtain an analog television signal.

BACKGROUND OF THE INVENTION Television signals are generally composite signals of two categories of signals: a video information signal component and some synchronization signal components. A common television signal is formed of horizontally distributed lines of video information separated by intervals of horizontal line-related synchronization signals defining the start of each line. These horizontal lines are composed of a raster of vertically dispersed lines defining fields of lines separated by vertical field associated synchronization signals. These fields are then composed of frames each consisting of two interlaced fields of horizontal lines, each field line having a different raster position when displayed. Various synchronization signals included in the television signal serve to synchronize the processing of the television signal and the operation of the processing device and other devices using the television signal.

In color television signals, the synchronization signal includes vertical and horizontal blanking intervals, each consisting of a composite signal of several synchronization signals. A vertical blanking interval includes a vertical blanking level extending between leading and trailing signal transition edges that determines the duration of the vertical blanking interval. For this blanking level, each horizontal sync pulse has a sawtooth pulse interval that defines a number of horizontal blanking period intervals and a number of equalization pulses and a vertical sync pulse between approximately half of the vertical interval. followed by a burst (typically 9-11 cycles) of a sinusoidal chrominance subcarrier signal (color burst). Each horizontal blanking interval between the subsequent half of the vertical blanking interval and the entire field of the line between consecutive vertical blanking intervals extends between the leading and tail signal transition edges, which determines the duration of the horizontal blanking interval. Contains horizontal blanking level. Each horizontal blanking level is provided with a horizontal periodic pulse followed by a color burst. One horizontal periodic pulse and one color burst are provided for each horizontal line of the television signal and serve to keep horizontal scanning and color generation in synchronization. A vertical sync pulse is applied to each field of the television signal to keep the vertical scan synchronized. The sawtooth shape of the vertical synchronization pulses prevents the horizontal scan from losing synchronization. Equalization pulses are provided to ensure proper scanning movement synchronization with the required interlacing of the two fields that make up the television frame. The horizontal and direct blanking levels serve to blank the display between horizontal and vertical traces, and the associated transition edges provide smooth signal transitions between video information signal intervals and blanking.

Proper display and processing of television signals requires the accurate formation of synchronization signals and their insertion into the television signal. In the generation of television signals, the video information is usually generated separately from the synchronization signal, and the two are combined by adding them together in a multiplexer. Furthermore, during post-processing of the television signal,
A new synchronization signal is inserted into the normally processed television signal. This combination or insertion is done at the end of generation or processing to avoid introducing timing disturbances to the synchronization signal and to avoid degradation of the synchronization signal. Also, the transmission of television signals through communication channels often introduces such disturbances and degradation. A video tape recorder (VTR) is an example of such a communication channel. Following such transmission, a new synchronization signal is inserted into the television signal to restore it to its proper form. Video processing amplifiers are commonly used to insert television synchronization signals into the video information.

One particularly important timing relationship between the various components of a color television signal is the phase of the color burst versus horizontal sync pulse. The phase of a burst is typically measured with respect to a point 5% of the leading edge of the preceding horizontal periodic pulse. If noise, signal transmission, or VTR operation corrupts the synchronization signal, it usually results in improper processing and display of the television signal.

Such corruption or distortion often has the particularly undesirable effect of changing the phase of the synchronization signal. This phase change affects the television signal particularly when provided by different television signal sources or when the television signal has been recorded several times and is reproducing a sequence giving rise to several occurrences of the television signal. Complicates processing. For example, distortion of the edges of the horizontal sync pulse will result in errors in measuring the phase of the color burst, and different distortions will lead to different measurement errors. If different VTR or other television signal sources are used to generate a program and phase stability is not maintained between these several sources, different color burst phase identification errors will occur;
This results in the insertion of color bursts at different phases with respect to the edges of the horizontal sync for signals received from various sources. For example, one
If a VTR is used as a source for one program and another VTR is used as a source for another program when a source switch is made, the phase of the color burst relative to the horizontal sync is determined by the phase difference between the two sources. It suddenly shifts. This causes a sudden shift in the hue of objects in the displayed television image. The production of several occurrences of a television signal is also accomplished with small distortions of the often sharp signal transition edges in each recording and playback sequence, and these accumulate on each occurrence of a television signal to produce such a television signal. Since the digital signal significantly degrades the display, the above-mentioned undesirable result occurs.

Furthermore, the time relationships, time periods, rise times, edges, etc. between the various components of the video signal for public transmission, including highly specialized criteria regarding the form and time of occurrence of the synchronization signals contained in the composite television signal. NTSC-RS170A that practically defines the shape
There are national standards such as standards. Such precise criteria must be met for proper functioning of the video system. This is because a new synchronization signal is generated locally and inserted into the video signal being processed in place of the original synchronization signal.

In conventional video processing equipment, such as those used in digital timebase supplements, it is common to convert digitized video to analog form before inserting a synchronization signal. This process and configurations therefor have several drawbacks including crosstalk and phase drift and other forms of instability. Typically, the digitized video signal is converted to analog form and a synchronization signal is generated in a filter for inserting the video information at the appropriate location. However, the circuitry that processes the video information portion of the television signal is typically in close proximity to the synchronization signal generation circuitry, and the signal lines of each circuit have a certain amount of inductive coupling to each other. Because of the relatively narrow pulse width and sharp rise time characteristics of the synchronization signal, high frequency components are generated that are radiated and picked up as crosstalk in the video information circuitry. Such crosstalk can cause undesirable artifacts in the displayed video information.

Phase instability problems also arise in systems where the video information is digitized and the insert synchronization signal is generated in analog form. Typically,
The analog circuitry used to generate the synchronization signal is not locked in synchronization with the clock driving the digital video processing circuitry. This defect in the locked synchronization relationship results in phase variations between the analog synchronization signal and the digital video data.

(Problem to be Solved by the Invention) Therefore, it is necessary to digitally generate television synchronization signals and combine them in synchronization with video information.
A need exists for a system that ensures that a stable phase relationship is maintained between synchronization signals and video information coupled thereto.

(Means for Solving the Problem) According to the present invention, the television synchronization signal to be combined with the television video information in the signal combiner is a digital number giving a digital signal value representing the amplitude peak of the synchronization signal. Digitally generated by a generator. For monochrome television signals, digital signal values are provided that represent the blanking level and the amplitude peaks of the synchronization and equalization pulses. When a color television signal is formed, a digital signal value is given that represents the amplitude peak of several cycles of the color burst following the horizontal synchronization pulse. The time and interval of occurrence of these digital signal values is determined by a reference signal that identifies when a synchronization signal must be inserted into the video information signal. This reference signal is provided to control the digital number generator so that it generates the appropriate digital signal value at the appropriate time for the appropriate duration. In order to ensure that the insertion of the synchronization signal is carried out correctly in the video information signal, the reference signal is also used to synchronize the transmission of the video information signal via the signal path preceding the signal combiner, The arrival of the synchronization signal and the video information signal to the signal combiner is adjusted to effect the desired combination of these signals.

The generated digital signal values accurately define the amplitude peaks, but not the edges of the synchronization signal.
As discussed above, the signal transitions and other edges of the synchronization signal are precisely specified for television signals used for public broadcasting. In such a signal, the edges are defined by complementary sin ² functions, one rising edge and the other falling edge. This sine square function is given by y=(sinx) ² .
Here x has a value of 0°-90°. The complementary form is given by y=1-(sinx) ² . One important feature of the invention includes a technique for processing the digital signal values provided by the first digital number generator to cause edge shaping to form the synchronization signal according to a sine-square function. There is. More particularly, a plurality of digital gain control values representing a sine-squared edge shape are generated by the second digital number generator to occur synchronously with the beginning and end of each synchronization interval. The time and interval of occurrence of these digital gain control values is determined by the reference signal described above that identifies when the synchronization signal must occur within the video information signal. This reference signal is provided to control the second digital number generator so that it generates the appropriate digital gain control value at the appropriate time within the appropriate time period. These generated gain control values are applied to a first input of a digital multiplier. A second input of the multiplier receives the digital signal value provided by the first above-described digital number generator. In this multiplier, the digital signal value is multiplied by the digital gain control value, thereby adjusting the digital signal value at the beginning and end of the synchronization signal according to the sine square function represented by the digital gain control value.

In other embodiments, the digital signal value that defines the peak amplitude and the digital gain control value that defines the edge shape of the digitally synthesized synchronization signal can be multiplied "in front" of the multiplexer. The multiplexer inputs will be already multiplied numbers representing the video information signal on one channel and the digitally combined synchronization signal on the other channel. The multiplexer is switched at the appropriate time to place the digitally synthesized synchronization signal at the appropriate location in the composite television signal being generated.

For something different than the known television signals, the transition edges of the synchronization signal can be defined by a function different from the sine-square function. For such other television signals, the digital gain control value is selected to cause the transition edge to be shaped according to one or more functions required for proper shaping of the synchronization signal. be done.

According to another important feature of the invention, an addressable memory is used to store the digital gain control values that generate the edges of the synchronization signal. Generation of a digital gain control value for a particular edge of a particular synchronization signal is accomplished by control of an address generator that causes the recovery of the digital gain control value from a memory storage location. Although a separate set of gain control values can be stored and restored for each edge of each sync signal to be combined with video information, this preferred embodiment provides the necessary gain control values for all sync signals for a particular television standard. It is characterized by storing a set of digital gain control values that generate all edges. This set of stored digital gain control values is also used to form rising and falling edges defined by related and complementary sine-squared functions. Complementary digital gain control values for one type of edge, such as falling edges, provide non-complementary values to the multiplier for other rising edges before providing them to the multiplier. This is achieved in the preferred embodiment by controlling the address generator to cause the complementary and non-complemented values to recover the gain control values in an inverse sequence. Using addressable memory in this manner simplifies and facilitates generation of digital gain control values.

For devices that use analog television signals, such as television signal display monitors, composite digitized television signals are digital-to-analog (D/
A) applied to the transducer. The D/A converter converts the analog signal from both the digitized video information signal component of the composite television signal and the digitized synchronization signal component that is combined with the video signal component to form the composite digitized television signal. It works to convert to . A filter is used in conjunction with a D/A converter to form a typically continuous composite analog television signal from a series of separate analog amplitude values provided by the converter. A low pass filter is used to facilitate this formation of the analog television signal. This filter has an upper corner frequency slightly less than twice the color subcarrier frequency, and up to at least -6 decibels (dB) at twice the color subcarrier frequency and up to three times the color subcarrier frequency. The frequency is chosen to have an upper stopband that rolls off to at least -55 dB. A single filter with such characteristics allows smoothing of the entire composite television signal provided by the A/D converter in the form of a series of discrete amplitude values.

EFFECTS OF THE INVENTION A television synchronization signal is generated in the digital domain in synchronization with the timing of a video information signal to be combined with a television synchronization signal to form a digitized composite television signal. The video information signal component is then combined with the digitized video information signal and the digitized synchronization signal to prepare a composite signal for use by the television signal using equipment. By processing a composite television signal without separating the signals, it is possible to provide a television signal with precisely shaped synchronization signals that can be divided between the various synchronization signals themselves and establishing and maintaining a stable phase relationship between them and their associated video information signals;

DESCRIPTION OF THE PREFERRED EMBODIMENTS A block diagram of a preferred embodiment of the television synchronization signal generator 10 of the present invention is shown in FIG.
Generally, as described above, a digital television synchronization signal is generated and combined with the video information signal to form the desired composite television signal in accordance with the present invention. Therefore, the video information signal is preferably represented in a compatible digital form for being combined with the digital synchronization signal. The video information signal to be combined with the synchronization signal runs on line 1 to a signal combiner, such as a multiplexer 22, which operates to effect the combination of these two signals.
06 by the video signal processor 24. Video signal processor 24 prepares the video information signal for combination with the synchronization signal. The video information signal is connected to the processor 2 on line 38, as in the case of the signal provided by the well-known television camera.
4, the processor 24 has an analog-to-digital converter that encodes the video information signal into a compatible digital form. Video A/ like this
D signal processing circuits are well known and are found in many conventional video processing amplifiers. However, many television signal sources, such as VTRs, provide video information signals in digital form. When a digital video information signal is provided to the video information processor, this processor is configured to set the required signal level of the digital video signal and the time for providing this digital video signal to the multiplexer 22 for combination with the digital synchronization signal. It is configured to have a circuit to The processing performed by video signal processor 24 is controlled by a clock signal provided on line 36 by reference signal generator 27. This is accomplished by reclocking the samples that form the signal. The clock signal is at a frequency corresponding to the desired data rate of the video information signal. The preferred embodiment of the present invention provides a color filter from a digital video information signal having a data sampling rate (4Fsc) that is four times the frequency of the "nominal" subcarrier signal of the video signal, which is the frequency selected for the clock signal on line 36. configured to form a television signal.

The preferred embodiment of television synchronization signal generator 10 is configured to operate with digital video information signals in the form of 9-bit binary words and digital synchronization signals. Multiplexer 22 is therefore configured to receive these signals via lines 106 and 108 in the form of a nine line bus. Bus bar 106 extends from processor 24 to the first or "A" input of the two inputs of multiplexer 22. Multiplexer 22
A second or "B" input of receives via bus 108 a digital signal representative of the peak amplitudes of the various synchronization signals with which the received video information signal is to be combined. As will be detailed below, the timing of the application of the binary word sequences forming the digital synchronization signal to multiplexer 22 is controlled by a clock signal present on line 36, so that the video information signal and the synchronization signal are The two signals are combined by a multiplexer without introducing a phase discontinuity at the transition between them. This combination of signals is accomplished by controlling multiplexer 22 in the following manner. That is, its A input is coupled alternately to bus 106 during the time period during which the video information signal is to occur in the composite television signal and to bus 108 during the time interval during which the synchronization signal is to appear in the television signal. Ru. This control is accomplished by two status signals provided by reference sync generator 27 that indicate when the video information and sync spacing should occur in the composite television signal. Generators of reference composite television signals for use in synchronizing the operation of television signal processors are well known in the art. They provide a composite blanking reference signal that is used for the purpose of effecting the switching of multiplexer 22 in the preferred embodiment of the invention. The composite blanking reference signal is provided on line 30 and is a two-state signal useful for identifying the duration of horizontal and vertical blanking periods contained within the reference color television signal.

According to one feature of the invention, each of the synchronization signals to be combined with the video information signal is formed from two separately generated digital components: a digital transition edge component and a digital amplitude peak component. Following generation, these components are provided to a digital signal combiner. This combiner is a digital multiplier 2 in a preferred embodiment of the invention.
It is 0. The digital amplitude peak components are generated by a first digital number generator 26 which is operated to provide signal amplitude values in digital form representative of the amplitude peaks of the various synchronization signals to be combined with the digital video information signal. generated. As described above in connection with color television signals, this first digital number generator 26 determines the peak amplitudes of the horizontal and vertical blanking levels, the peak amplitudes of the horizontal sync pulses, and the serrations of the vertical sync pulse intervals. A digital amplitude value is provided representing the amplitude of the interval between peak amplitudes, the peak amplitude of the equivalent pulse, and the peak amplitude of the burst color subcarrier cycle. In common color television signals, these amplitude peaks are defined by only a few different values. NTSC
For color television signals, one value defines the horizontal and vertical blanking levels, the amplitude of the spacing between the front and trailing equivalent pulses, and the amplitude of the spacing between the sawtooth portions of the vertical sync pulses. Other values define the amplitude peaks or tips of the horizontal sync pulses, equivalent pulses, and sawtooth portions of the vertical sync interval, and two additional values define the amplitude peaks of the sine wave forming the color burst sync signal. The PAL color television signal has a synchronization signal with amplitude peaks defined by a similar number of different values, which values are somewhat different from those of the NTSC color television signal. SECAM color television signals are quite different from NTSC and PAL signals, and their synchronization signals can also be defined by a small number of different values.

Regardless of the criteria of the color television signal being processed, the required synchronization signal peak amplitude value is determined in the first digital number generator 26, which will be described in more detail below in connection with Figures 5A-5E. generated in the preferred embodiment by included logic. The operation of this logic is controlled by a reference sync signal provided by reference sync signal generator 27 via lines 30, 32 and 34. A composite blanking reference signal provided on line 30 represents the timing for the start time and duration of the horizontal and vertical blanking intervals. The composite sync reference signal provided by generator 27 on line 32 determines the start time and duration of the equalization pulse, the horizontal sync pulse, and the vertical sync pulse and vertical sawtooth of the vertical sync pulse contained within the reference color television signal. is a two-state signal that is useful for representing The burst gate signal provided by reference sync signal generator 27 on line 34 is another two-state signal useful for representing the duration of a color burst interval contained within the reference color television signal. 5A-5
As discussed below in connection with Figure E, the states of these synchronization signals are detected and decoded by a first digital number generator 26, so that the generator 26 determines the appropriate times for the digital synthesis of the various synchronization signals. to provide an appropriate peak amplitude digital value to the signal combiner 22 for combination with the video information signal.

The first digital number generator can be constructed with relatively simple logic since only a smaller number of different digital values are needed to generate the peak amplitude values for the different synchronization signals. In other embodiments, if necessary, an addressable memory stores these required values and stores them for the formation of a synchronization signal according to an address determined by the above-mentioned reference synchronization signal. can be used to give

The digital transition edge component is operated to provide a signal according to a function determined by the relevant color television signal standard defining the shape of the signal transition edge of the various synchronization signals to be combined within the video information signal. second digital number generator 2
8. Conveniently for the construction of the present invention for color television signals defined by a common international television standard, all such edges are determined by the above-mentioned sine-square equation in which the rise time differs between the various standards. expressed. A preferred embodiment of the present invention takes advantage of this convenience by providing a single set of signal values in digital form for use in forming all edges of all synchronization signals for a particular television standard. take advantage of This single set of values is stored in addressable PROM memory, as described in more detail in connection with Figures 5A-5E. It is true that a single set of values determines the shape of each edge of a sync signal that is shaped to comply with a particular television standard; A family of several sets of such data are stored in the PROM, where the data are represented slightly differently topologically. This allows synchronization to the subcarrier phase to be performed digitally with extremely small drift by selecting sample points of different families that are defined by edges of the same shape but slightly shifted in time with respect to the zero-crossings of the color burst synchronization signal. can be changed.

Memorize the edge that determines the gain control value
PROM addressing is lines 30, 32,
It is similarly controlled by the above mentioned synchronization signal provided by the reference synchronization signal generator 27 via 34. The state of these signals is examined by a second digital number generator 28 and an address signal is generated as a result of the above to address the memory,
A second digital number generator 28 provides appropriate values to determine the desired shape of the signal transition edges for the various synchronization signals. The values for the rising and falling edges are generated by giving two sets of values according to complementary sine-squared functions, these values represent a non-complementary squared function defining the rising edge, and they are Represents a complementary sine-squared function that defines a falling edge. Although two sets of values can be stored in memory for this purpose, the preferred embodiment only has one set of values.
Only one set of values is required, from which two complementary sets of digital gain values are generated. Furthermore, digital signal complementation means separate from the addressable memory may be used to generate a complementary set of values from non-complementary values stored in that memory (or vice versa). , the preferred embodiment provides these two sets by simply reversing the sequence of addressing the memory to recover the stored value. Therefore, fewer digital signal values are used to form all signal transition edges for all synchronization signals to be combined with video transition edges, and fewer digital signal values are used to form all signal peak amplitudes of the synchronization signals. Using only a small number of values provides a very simple way to digitally generate a television synchronization signal for combination with a video information signal.

A single set of transition edge defined digital values is sufficient to form a synchronization signal that is combined with a video information signal having a known constant phase. However, if one digital synchronization signal generation system is used in several different television standards, or as is required when synchronization versus subcarrier phase variations are taken into account, If it is desired to configure television synchronization signal generator 10 to operate in conjunction with a processing television signal processor, a single set of edge shaping gain control values is insufficient. In such embodiments, it is desirable to provide a separate set of transition edge defining digital values for each of the various desired synchronization-to-subcarrier phases. Although it is possible to pass the digital values to separate adjustable delay lines to account for the various phases of the video information signal, the need for so many different phases makes it difficult to determine the accuracy of each of these delays. This would require a very complex delay system that must be clocked very quickly to allow for accurate generation.

In embodiments configured to form synchronization signals having various synchronization-to-subcarrier phases with respect to the reference phase, the second digital number generator 28
The capacity of the memory contained in the is adapted to store the required number of sets of digital numbers. In order to effect selective recovery of the stored sets from memory, a system phase addressing control signal is generated on line 29 consisting of the number of bits necessary to uniquely address each set of edge defined gain control values. to a second digital number generator 28 via the second digital number generator 28. These address bits are added to an addressing signal formed from a reference synchronization signal applied to a second digital number generator 28. The combined address is edge-shaped with multiple bits that select the appropriate set of predefined digital gain control values;
and other bits that select which particular gain control value is to be output on any particular clock cycle. These same system phase addressing control bits are used to effect changes in the timing of the operation of the logic contained in the first digital number generator 26, so that the digital amplitude peak value provided by that generator is When changing the subcarrier phase, it is properly phased to the transition edge value. Since the peak value does not change for different phases of the synchronization signal, changes in the timing of the operation of the logic of the first digital signal generator can be achieved without complexity.

As mentioned above, the two separately generated components are combined to form a synchronization signal that is inserted into the video information. In the preferred embodiment shown in FIG. 1, this combining involves first combining the video information signal and the amplitude peak value provided by the first digital number generator at multiplexer 22 as described above. It is done by twisting. After combining the amplitude peak value with the video information signal, bus 40 provides a first combined output from the output terminal of multiplexer 22 to the "A" input of digital multiplier 20. Digital multiplier 20 is used in the preferred embodiment to perform two functions. One of these functions is to combine the transition edge value provided by the second digital number generator 28 with the amplitude peak value already inserted into the video information signal. This combination is achieved by digitally multiplying the amplitude peak value by the transition edge value provided by the second digital number generator 28 via the busbar 42 to the second "B" input of the multiplier 20. achieved. Therefore, the transition edge value is provided as a gain control value representing a gain ratio number normalized to unity. The other function performed is control of the video information signal gain, which is controlled by an operator controlled device (not shown).
is determined by a video gain control signal applied to busbar 42 extending from . Since both functions require the same kind of operation to be done on these signals, a single digital multiplier 20 can be used, thereby simplifying the construction of the device 10.

However, setting the gain of the video signal and combining the two digital value components to form the synchronization signal can be done separately. In such an embodiment, two multipliers are used. One is placed in the video information signal path between the output of video signal generator 24 and the input to multiplexer 22. A video gain bus 42 extends to this multiplier and provides a video gain control signal thereto that determines the video signal gain. Another multiplier is placed in the signal path between the output of the first digital number generator 26 and the input to the multiplexer 22. In addition to the digital signal value that determines the peak amplitude of the synchronization signal to be generated, this multiplier also receives a transition edge determining digital gain control value provided by a second digital number generator 28. These two streams of digital data are multiplied together and the resulting data stream is input to one channel of a multiplexer for switching to a stream of video information data at the appropriate time.

Other embodiments include a second circuit that performs digital gain control.
multipliers and uses only one multiplier to contain the synchronization signal.
This gain control function may be performed after the digital data stream defining the composite television signal has been converted back to analog form.

In any of these multiplier embodiments, the two digital number generators 26 and 28 are operated synchronously under the control of a reference synchronization signal provided by reference synchronization signal generator 27, as described above. These reference synchronization signals are supplied to two digital number generators 26, as described in detail below.
and 28 and associated addressing circuitry and decoding logic so that the amplitude peak value and the transition edge gain control value are generated by the generator at appropriate times and for appropriate time periods in relation to each other. This allows the formation of the various desired synchronization signals to occur at appropriate times with respect to the video information signals with which they are combined.

For applications where a television signal in analog form is required by the equipment used, digital-to-analog converter 39 forms a composite digital television signal that is applied to the "C" output terminal of multiplier 20. It has its input connected by bus 51 for receiving a multi-bit binary word. Converter 39 converts the multi-bit digital signal provided at its input via line 36 into a serial stream separated at a rate determined by the reference 4Fsc clock signal provided by reference sync signal generator 27. Convert to the amplitude value. A subsequent low pass filter 41 has its input connected by line 53 to receive a serial stream of discrete analog amplitude values, and generates a continuous composite analog television signal from the serial stream of discrete analog amplitude values. The output 55 of the analog television signal is supplied to a device using an analog television signal. As mentioned above, a single lowpass filter is used which has an upper corner frequency slightly less than twice the color subcarrier frequency and at least a negative frequency at twice the color subcarrier frequency. It is chosen to have an upper stopband that rolls off up to 6 decibels (dB) and at least minus 55 dB at frequencies three times the color subcarrier frequency. For an NTSC color television signal, the color subcarrier frequency is approximately
It is 3.58MHz. This filter is used to form the desired continuous composite analog television signal.
The sequence of discrete amplitude values provided by D-converter 39 is smoothed.

To better understand the operation of the preferred embodiment, reference is made to FIG. FIG. 2 shows that the incoming video information signal and the digital signal generator provided by the first digital number generator 26 and the digital transition edge gain control value from the second digital number generator 28 are low during the horizontal blanking interval. The timing relationship between the final analog composite sync signal present at the output of the range filter 41 is shown. FIG. 2A shows the relative placement of horizontal blanking intervals, horizontal periodic intervals, and intervals of a plurality of color burst cycles within a video information signal. The signal before time t ₀ is video information. The horizontal blanking interval begins at time _t0 and extends until time _t5 . The signal after time t ₅ is video information. Horizontal blanking interval time t ₁
and t ₂ is the duration of the horizontal sync pulse. A color burst sync signal interval follows the horizontal sync pulse from time t ₃ to time t ₄ .

FIG. 2B shows the digital signal values output from the first digital number generator 26 in analog format. Although the digital signal value is actually represented by a plurality of bits in either a logic 1 or logic 0 state on the output line of the first digital number generator 26, it is convenient and We show that we represent digital numbers by their analog values if they are converted to decimal system numbers. In the preferred embodiment, the analog value is represented by a 9-bit digital signal, and the analog value for the digital signal value represents the amplitude peak of the blanking level chosen to be _0-10 . The analog value for the horizontal synchronization signal and the digital signal value representing the amplitude peak of the equivalent pulse and the amplitude of the sawtooth interval of the vertical synchronization interval is chosen to be _-11410 . The analog signal values chosen for the digital signal values representing the amplitude peaks of the color burst synchronization signal are +57 ₁₀ and −
57 ₁₀ .

It is known that the vertical blanking interval synchronization signal has a peak amplitude that is the same as the horizontal blanking interval synchronization signal. The vertical blanking interval of the NTSC standard consists of a pre-equalization signal, a sawtooth vertical sync signal interval, a post-equalization signal and some composite horizontal blanking and sync interval sync signals. The peak amplitudes of the pre- and post-equalization signals and the interval between the sawtooth portions of the vertical sync signal are the same as the peak amplitude of the horizontal sync pulse. The peak amplitude of the color burst synchronization signal in the vertical blanking interval following the post-equalization pulse is the same as those duplicates that occur during the horizontal blanking interval preceding lines of video information.
Thus, a set of digital signal values can be used to represent the peak amplitude of the synchronization signal for both the horizontal blanking interval and the vertical blanking interval. Also, for any particular television standard, the edge shape for all sync signal transition edges in both the horizontal and vertical blanking intervals is the same, so that the same set of digital transition edge gain control values (for a given sync-to-subcarrier phase, for a different sync-to-subcarrier phase, a different set of gain control values) are used, but this same set is used to form all edges for all synchronization signals for both horizontal and vertical blanking intervals).

FIG. 2C shows the output from the second digital number generator of digital transition edge gain control values representing the desired shape of edges to be formed with the digitally synthesized synchronization signal in both the horizontal and vertical blanking intervals. Shows relative timing in analog form. In the case of FIG. 2B, the digital transition edge gain control value is a digital number, each represented by a plurality of bits, in either a logic 1 or logic 0 state on one of the output lines of the second digital number generator. It is. These digital gain control values are output sequentially and would have analog values if converted to an analog format that would represent the shape of a (sin(x)) ² curve if plotted. These analog values are
They vary between 0 ₁₀ and 1 ₁₀ and remain at their last value until the next edge transition occurs. Edges A-F are all sin ² edges in the preferred embodiment as they are edge types specified by the NTSC standard.
However, in other embodiments, digital values representing different shapes are generated by a second digital number generator. Edges A and F represent the start and end of the horizontal blanking interval, respectively;
Edges B and C represent the beginning and end of the horizontal sync pulse, and edges A and E represent the beginning and end of the color burst interval.

The waveform of FIG. 2D is generated after the multiplication of the digital signal value by the digital edge transition gain control value and the resulting digital product is converted to a stream of separated analog signal values by D/A converter 39 and by filter 41. The output waveform from multiplier 20 is shown after it has been filtered to smooth the signal.

As shown in Figure 2, the digital signal value is
The digital edge transition gain control values are applied to the multiplier 20 to take their peak amplitude values between the relevant times so that the appropriate edge shape can be formed. For example, Edge 44
is the output of the first digital number generator 26 at time t ₀
This is formed by making a transition to a digital number representing the horizontal blanking level at A, which defines the shape of edge A. This is done by making a transition from 1 to ₁₀ in columns in spaced steps. 0 to ₁₀ begins to occur at the B input of multiplier 20 at a time slightly after time t ₀ . If this sequence of events were reversed or otherwise altered, edge 44 in FIG. 2D would not be properly formed. The same is true for edge 44 in FIG. 2B. In FIG. 2B, the output of the first digital number generator is a digital transition edge gain that makes the transition from 0 ₁₀ to 1 ₁₀ in a sequence of spaced steps ending at time t ₁ such that edge 48 is properly formed. Takes the value of the horizontal synchronization pulse peak amplitude at time _t1 , which is the same time when the output of the second digital number generator starts to output the sequence of control values. A similar situation can be seen for edges C, D, E and F by considering the timing of the occurrence of the digital signal value represented by Figure 2B and the digital transition edge gain control value represented by Figure 2C. It becomes clear that it can be shown that they exist for each of them. Of course, the waveform of Figure 2B can be modified according to a function other than those mentioned above, which would result in the waveform of Figure 2D when multiplied by a gain value representing a function other than the sin ² function shown in Figure 2C. It is possible for this to occur. However, for digital embodiments, the waveforms of FIGS. 2B and 2C are the simplest for construction.

As is clear from the foregoing, edge 44 in Figure 2D is a digital gain control value having a value such that when edge A starts downwards, i.e. the output of the second digital number generator decreases in a sin ² manner. Start downwards as you begin to represent that sequence of . Therefore, the shape of edge 44 is formed by the shape of edge A. The advantage of generating the desired shape for edge 44 and all other edges in this manner is that the actual timing of the start and end of that edge, its shape and its passage through the 50% amplitude point are precisely controlled. That's what it means. This is the most important advantage for forming the transition edge 48 of FIG. 2D, which is the leading edge of horizontal synchronization. Accurate control of the timing and shape of this edge is important in being able to control the synchronization versus subcarrier phase. Precise control of the timing and shape of edges 50 and 52 is also important as they represent the end of horizontal synchronization and the beginning of a burst interval, respectively.

FIG. 3 shows a more detailed diagram of the discrete values for the analog format digital gain control values that make up each sin ² edge A-F of FIG. 2C. There are 16 sets of digital gain control values that define 16 sin ² edges. Edge E ₁ and E ₁₆
represents only the 1st and 16th such edges. Other edges exist somewhere between these two limits, but all edges have the sin ² form. Each edge is defined by eight spaced sample values, one of which is output for every clock cycle of the 4Fsc clock signal, as represented by the eight clock times shown below the curve. The value for any discrete one of the set of transition gain control values for any particular one of the eight clock times is determined by the selected sin ² associated with a vertical line extending from the associated clock time.
Given by the intersection with Edge. The 50% amplitude point of each particular one of the 16 pairs of sin ² edges is
4Fsc occurs at different times with respect to the time line.
As will be explained in more detail below, various television standards and desired shifts in synchronization versus subcarrier phase for any given television standard may be used to provide several families of edge-defined gain control values. It is possible to adjust the synchronization vs. subcarrier phase to accommodate.

As will be apparent from the description in connection with FIG. 5, in a preferred embodiment of the present invention, the horizontal sync to subcarrier phase can be coarsely and finely adjusted by the user. This allows the user to
It is possible to input a signal that moves the horizontal sync envelope, represented by edges B and C in Figure C, over one full 360 degree cycle of the subcarrier. Providing a different family of gain control values allows for fine tuning ability for this function.

The same mechanism that allows adjustment of the sync-to-subcarrier phase also serves as a mechanism that allows a 25 Hz offset to be inserted into the video equipment to meet the PAL standard. Both the 25 hertz offset and the sync-to-subcarrier phase change are accomplished by shifting the position between the sync and blanking sync signals with respect to the time position of the zero crossings of the color burst sync signal in the horizontal blanking interval. This process is accomplished in the coarse adjustment described above by varying the timing of the generation of address signals to the PROM that stores the digital edge transition gain control values. In the above detailed adjustment,
Further adjustment is achieved by selecting a different one of the family of edge defined gain control values to access from the PROM.

In FIG. 3, edge E ₁₆ is advanced by one quadrant, ie, one quarter of a subcarrier cycle, from the time position of edge E ₁ . In the first set defining edges E ₁ , the gain control values accessed at sample 8 hours are repeats of the gain control values accessed at sample 7 hours. Also, in the 16th set of gain control values E ₁₆ ,
The gain control values accessed at sample times 7 and 8 have unique values, whereas the gain control values accessed at sample times 1 and 2 are repeats of each other.

The relative levels of each of the sample points are set to a level that results in the formation of the desired edge shape and meets the rise time requirements of the NTSC standard. Clearly, the present invention provides a highly flexible manner to form any desired pulse shape with virtually any rise time without the use of expensive and complex filters.

In embodiments where the incoming video information signal is in digital form, video signal processor 24 converts the incoming digital samples defining the video information signal into two complementary formats and the blanking levels of the incoming video information signal are 0, _10, and 10. It works to shift the digital display of video information. The video signal processor also adds a sign bit so that the increasing luminance signal is the complement of positive two and the synchronization signal is the complement of negative two. This process draws a blanking level (128 in a 9-bit video system with level 512 as the maximum luminance value and a sync chip at level 14) from the incoming video such that the blanking level is at level 0. This is equivalent to converting the incoming data to the complement of two by adding a sign bit of 0 for positive levels and 1 for negative levels.

Figures 4A and 4B illustrate the timing for the address signal generated by the logic for addressing the PROM of the envelope generator 28 to cause generation of a digital value representing the synchronization signal during the horizontal blanking interval. Show the diagram. The timing relationships associated with the generation of digital values representing synchronization signals that occur during vertical synchronization intervals are similarly generated as described in detail below in connection with the timing PROM 100 shown in FIG. 5B. The figures also give a pooling equation that is positive for any particular time interval represented by the box defined by the dotted horizontal and vertical lines shown in the figures. Each signal is circled and assigned a time line to the left of that signal. line 1
The signal indicates the timing of the desired sin ² edge such that the edge is represented by the same reference letter as represented in FIG. 2C. This representation of time line 1 is of course not the actual signal, but of the digital transition edge gain control value when converted to a series of discrete analog voltage levels and filtered to smooth the transition between these levels. 2 is a graphical representation of wake-up time and analog voltage level.

The meaning and use of other signals in time lines 2-15 of FIGS. 4A and 4B are explained in FIG.
It will be better understood by referring to Figure E. The portions of logic corresponding to the functional blocks of FIG. 1 are described in order so that the specific circuits that make up each functional block can be identified.

5A and 5B, the logic constituted by first digital number generator 26 and second digital number generator 28 is shown. The input signals, composite blanking, composite sync and burst gate, are signals on lines 30, 32 and 34 from reference sync signal generator 27. The construction of a reference synchronization signal generator is well known to those skilled in the art, and integrated circuits are commercially available to perform this function. The timing of these three signals is shown in FIG. 6, along with the relationship these signals have with respect to the signals at test points TP-2 and TP-3. Generally, the signal generated by the reference synchronization signal generator 27;
Composite blanking, composite sync and burst gates dictate the occurrence and duration of all synchronization signals of the composite video signal during both horizontal and vertical blanking intervals. The edges of these signals are used to signal the beginning of the process of restoring the digital transition edge gain control values that define the sin ² edges for the synchronization signal that is being digitally synthesized. Each of the signals of reference sync signal generator 27 indicates the start time and duration of a particular one of the sync signals of the composite video signal. That is, line 30
The composite blanking signal at transitions 49 and 4
7 indicates the start time and duration of the horizontal blanking interval. Similar transitions, not shown in FIG. 6, indicate the start time and duration of the vertical blanking interval of the composite video signal. line 3
The composite sync signal at 2 indicates the start time and duration of the sawtooth of the horizontal and vertical sync signals, the equalization signal, and the vertical sync signal. Transitions 54 and 5 in Figure 6
6 indicates the start and end of the horizontal synchronization signal during the horizontal blanking interval. The burst gate signal on line 34 indicates the start time and duration of the color burst interval in the horizontal and vertical blanking intervals. Transitions 57 and 59 indicate the start and stop of the color burst interval of the horizontal blanking interval. The state of these reference synchronization signals from the reference synchronization signal generator 27 is shown in FIG. 6 only for horizontal blanking intervals, but the transition of the signals from this during vertical blanking intervals is shown as well. These transitions between vertical blanking intervals are
They serve the same purpose as the transitions of these signals shown in FIG. 6, except that they provide reference timing for the vertical blanking interval synchronization signal instead of the horizontal blanking interval synchronization signal. These transitions between vertical blanking intervals control the digital composition of the vertical blanking interval synchronization signals in accordance with the specifications of the particular television standard contemplated. The peak amplitude of the vertical blanking interval, pulse shape and sequence of pulses are well known to those skilled in the art.

These reference synchronization signals are gates U120 and U1.
Buffed at 35, NAND gate U1
TP-2 in FIG.
A waveform is generated. All signals must be AND gated to obtain the TP-2 waveform,
Gate U110 performs this function. The pulses of the TP-2 waveform have edges at the times at which each sin ² edge is to be formed. TP−
The purpose of the 2 signal is to signal the time at which the sine squared edge must be formed. this
The TP-2 signal is also used to access the gain control values needed to form these edges.
Begins the process of addressing the PROM. In addition, the TP-2 signal has the specific peak amplitude required at any particular time for the first digital signal processor to generate the appropriate digital signal value and multiply it with its gain control value. Initiating an event that generates an appropriate signal to control the first digital signal generator to represent the value. Primarily, the TP-2 waveform represents the time of each transition between video information and synchronization signals and the transitions between various versions of the synchronization signal. For example, transition 58 represents the boundary between the video information signal and the beginning of the horizontal blanking interval. Transition 60 represents the transition in the horizontal blanking interval of the synchronization signal from the horizontal blanking level to the horizontal periodic level. Transition 62 represents the tail end of the horizontal sync signal when the voltage level of the final composite video signal is assumed to return from the peak amplitude level of the horizontal sync signal to the horizontal blanking level. Transition 64 represents the beginning between color bursts and transition 66 represents the end of the color burst interval. Transition 68 represents the end of the horizontal blanking interval.

Has one input that receives the burst-off signal
The NAND gate 35 receives the burst gate signal from the gate U110 under processing conditions when there is no burst signal, such as when processing a monochrome signal.
Avoid passing through. Reference synchronization signal generator 2
7 continues to generate the burst gate signal even when the monochrome signal is being processed. The burst off signal is a command from the user console, which is a logic low signal that causes gate 35 to prevent the burst gate signal from passing to gate U110, thereby causing transitions 64 and 66 of the TP-2 signal.
prevent the formation of

Each of the transitions present in the TP-2 signal is detected by an edge detection circuit consisting of IC circuits U95, U108, and U72, as shown in time line 5 of FIG.
−3 signal is converted into one of the pulses. The operation of this edge detector is clear to those skilled in the art;
Any edge detector design is sufficient for purposes of implementing the present invention. The purpose of the edge detector is
The purpose is to issue a pulse for each transition of the TP-2 signal. IC circuit U72 is a Fairchild 74F161 synchronous presettable modulus 16, binary counter that counts 4 Fsc clock pulses (70 nanosecond period) when a signal at pin 7 enables counting. The preset input of this counter is connected to the synchronous pair subcarrier phase adjustment circuit 10 by a bus 70.
1 (Figure 5B) and a 25 Hertz offset circuit. Data at bus 70 is stored in counter U72.
Preload the exit count to. When the counter reaches this count, the end count output pin 15 goes high, causing node TP-3 to go low for one clock cycle under the action of inverter U58. By varying the count preloaded into counter U72, the pulse of the TP-3 signal at the TP-3 circuit point shown on time line 5 of FIG. can be shifted. The address signal for accessing the edge shaping gain control value from the second digital signal generator is similar to the signal that controls the operation of the first digital signal generator 26.
Generated as starting at the time when 3 goes low. an address signal that controls the second digital signal generator 28 and another signal that controls the first digital signal generator 26 by varying the time of the high versus low transition of TP-3 with respect to the transition of TP-2; It is possible to vary the time at which the is generated. This is a feature that allows the synchronization-to-subcarrier phase to be adjusted in a coarse manner one quadrant at a time. Also, a function that allows the generation of signals to be synchronized by the same clock signal so that the first and second digital signal generators can generate the appropriate digital values for performing the multiplication at the appropriate times. There is also. By appropriately presetting the count of counter U72, the horizontal period and horizontal blanking synchronization signals are shifted with respect to the zero crossings of the color burst interval, as will be explained in more detail below. By presetting the count of U72 with data on bus 70, coarse adjustment of the time of occurrence of the sine-squared edge of the horizontal sync and horizontal blanking sync signals with respect to the time of occurrence of the color burst interval can be achieved. The adjustment is
Associated with an integer number of 4Fsc cycles. Therefore, other television standards can be accommodated and the synchronous to subcarrier phase can be adjusted for any particular television standard without drift due to the digital and synchronous manner in which the adjustment is made. can.

Pulses of the TP-3 signal are used to signal when each sine-square transition edge is to be formed. This is illustrated by time line 2 of Figures 4A and 4B, where the TP-3 pulse is shown as a negative pulse, one of which occurs just before each sine-square transition edge of time line 1 occurs.

The signal at TP-3 is applied to the PROM of a second digital number generator 28 which is used to store a digital transition edge gain control number such that the number defining the sine squared transition edge begins to appear at the output of the PROM.
used to start the process of addressing. To accomplish this PROM processing function, appropriate address signals must be generated to access the PROM. Figure 5A
The signal at TP-3 is applied to the load input of another presettable modulo 16, binary counter U84 which counts 4 Fsc cycles starting from a fixed number applied to the preset input. This occurs each time the TP-3 pulse loads the preset count.

Signal A at time line 3-10 in Figures 4A and 4B (hereinafter referred to as Figure 4 unless there is a particular problem)
0-A7 represents the binary output of counter U84,
Timing pulse generation shown in Figure 5B
Serves as an address signal for PROM100.
Signal A0 is ÷2 counts of 4Fsc clock pulses on line 71. A1 signal is A0 signal 2
The A2 signal is divided by A1 in binary.
It is the binary division of the signal by two. The same applies to A3. A4 signal is counter U84
When the count reaches 16, signal A4 makes a high-to-low transition on the next 4Fsc clock transition following the final count.

The other three signals A5, A6 and A7 are PROM
100, is generated by the logic shown in FIG. 5B to serve as an address signal for a timing signal generator in the form of U85. Signal A5 is the fourth
The digital transition edge gain control value output by the second digital number generator 28 is accessed in a sequence shown on time line 8 of the figure and in which the gain control value is increasing from 0 ₁₀ to 1.0 ₁₀ . It is low when it is assumed that Signal A
5 is high when the digital transition edge gain control values are assumed to be accessed in the reverse order, such that the gain control values are decreasing from 1.0 ₁₀ to 0 ₁₀ . This is the part of the logic circuit that plays a part in controlling whether the sine squared edge being formed is a rising edge or a falling edge. The manner in which this is done is explained in more detail below.

Signal A6 on time line 9 of FIG. 4 is referred to as the wide sync signal and is in a logic 1 state starting at the time before the sine squared edge representing the beginning of the horizontal sync interval is to be taken. This A6 signal remains at a logic one until a later time when the sine square tail of the horizontal sync signal must be formed. The purpose of the wide sync signal is to provide timing for the first digital signal number generator 26 in the form of a sync/burst signal for which the wide sync signal is a "forehead" signal. This synchronization/burst signal is applied to the first digital signal number generator when the digital signal value defining the peak amplitude of the synchronization signal is to be applied to the multiplier and when the digital signal value defining the peak amplitude of the burst signal is applied to the multiplier. to indicate when it should be given.

The signal A7 shown on time line 10 in FIG. 4 is called a wide burst signal. It causes a transition to a logic one state starting at a time before the sine-square leading edge of the color burst sync signal "envelope", i.e. the shape defined by the chip of the sine wave cycle of the color burst sync signal, is to be formed. make. The A7 signal remains in a logic 1 state until a later time when the sine square tail of the color burst envelope is to be formed. This wide burst signal stores a gain control value that indicates to a second digital signal number generator 28 when the burst interval is occurring and defines the edge shape for the horizontal and vertical blanking period synchronization signals. Other signals 62 shown in Figure 5D as address bits for the PROM
Used with 5/525. wide burst and 6
The 25/525 signals together define which standard is operating, allowing selection of the appropriate family of gain control values to meet the edge shape and rise time requirements of that particular standard. for example,
The SECAM standard does not use any bursts, and the PAL standard requires a different synchronization signal rise time than the NTSC standard.

A specific preload number for counter U72 and a specific one of the 16 families of selected gain control bits control the user console to dictate the desired amount of subcarrier phase versus sync with the input signal from the 25 Hertz offset circuit. controlled by the input signal from the device. These input signals, which are in digital format, are added in adder 101 of FIG. 5B, and the three most significant bits of the result are provided by bus 70 to the preset input of counter U72 of FIG. 5A. These three bits select the desired quadrant of the required coarse synchronization versus subcarrier phase adjustment. There are four possible quadrants representing one total subcarrier cycle corresponding to the phase changes that can be selected. Fine adjustment of the synchronization versus subcarrier phase is accomplished in response to the dust control signal, or SCH phase, provided on line 29 by appropriate operator phase selection equipment (not shown). AM3-AM6 of results from adder 101
The four least significant bits, represented by , allow selection of a particular one of the 16 possible families of edge defined gain control values within the selected quadrant. The above four bits are connected to exclusive OR gate 1 on four of the address inputs of the PROM of the second digital signal generator 28 which stores gain control values to define the edge shapes for the sync and burst sync signals.
03, 104, 105 and 109 and bus bar 107. Address bit A5 is exclusive OR gate 103, 104, 105 and 109
given as other input to . A5 is logic 0
, the resulting bit AM3−AM
6 passes through the gate unchanged. When A5 is a logic one, the resulting bits AM3-AM6 are all inverted through the gate. This helps select the gain control bits to define the proper edge direction.

PROM 100 locks latch 100a in response to address signals A0-A7 present at its address inputs.
A timing signal is generated via a line 102 extending to. This latch 100a determines the time periods during which the various synchronization and blanking intervals occur.
Reclocking the timing signals used by other circuits of the system, including AM3-AM7 and AM0-AM2, which indicate the time and direction for the generation of edge shapes. The manner in which levels and edge shapes are generated in response to these timing signals will be stored in detail below.

Before the generation of signals A5-A7 is mentioned,
The operation of NAND gate 79 needs to be explained. NAND gate 79 has three inputs, namely TP-
3, a signal at pin 10 associated with the burst off signal, a signal at pin 11 associated with the burst gate signal which is NANDed with the burst off signal, and a reference vertical pulse signal. The reference vertical pulse signal is low at the leading edge of the vertical sync during the vertical blanking interval and remains in this low state for the remainder of the vertical blanking interval. The purpose of NAND gate 79 is to influence the generation of the A6 and A7 address signals so that the digitally synthesized burst synchronization signal is not generated at undesired times, such as when processing monochrome signals.

The timing diagram of FIG. 7 shows the signal states of various signals at the input and output of gate 79 under various conditions. The signals on time lines 1 and 2 are the TP-2 and TP-3 signals already mentioned above. gate 79
The signal at input pin 10 of is shown on time line 3. This signal is the Q inverted output of flip-flop 74 and is set to a logic one on the occurrence of each TP-3 pulse with one exception. This is because the TP-3 pulse is coupled to the clear input of flip-flop 74.

The exception to this rule is that the burst gate signal at time line 5 of FIG. 7 from reference sync signal generator 27 is in a logic 1 state (the burst gate signal at time has been inverted by inverter U135). Occurs between hours. The burst gate signal is caused to reach gate U110 in FIG. 5A only when a color television signal is being processed in accordance with the present scheme. For purposes of explanation, the burst gate signal is referred to as absent when the burst off signal is active, and vice versa when the burst off signal is not active. In the case of monochrome signals, there is no burst gate signal. The signal on time line 4 of FIG. 7 shows the U110 input signal at pin 10 at a time when no burst signal is present. This is the signal state for pin 10 of U110 when a monochrome signal is being processed. Pin 11 of gate U110
The input signal is the inverted burst gate signal on line 34 from reference sync signal generator 27 after being buffered and inverted by inverter 135 and gated by the burst off signal at gate U109. If the burst gate signal is off, the sine-squared "envelope" signal has a value corresponding to 0, so no transition is generated during the time interval during which a color burst would be present in the color television signal. . The input to NAND gate 79 is the reference vertical pulse on line 81. This signal functions as described above and serves to inhibit burst related address signals to PROM 100 during vertical intervals. The output signal from pin 8 of gate U110 is shown on time line 6 of FIG. 7 when the burst gate signal is present during color signal processing, and when the burst gate signal is absent during monochrome signal processing. is shown on time line 7 of .
This signal is clocked by the reclocking flip-flop U9 which is clocked by the 4Fsc reference clock.
5, thus synchronizing the output transitions of gate U110 to the 4Fsc reference clock.

Re-clocking flip-flop 95 pin 9
The Q output of U134 is connected to the clock inputs of two D-type flip-flops 83 and 85. U
The operation of NAND gate 80 of U134 and U110 is shown in the timing diagram of FIG. The composite sync signal on line 87 shown in time line 4 of FIG. and 85 asynchronous direct set inputs. The clock inputs of flip-flops 83 and 85 are connected to gate U11.
0 receives the reclocked output signal from pin 8. The logic state of this signal is indicated by either time line 2 or 3 in FIG. 8, depending on whether the burst gate signal is present or absent. Since the D input of flip-flop 83 is grounded, transitions towards the clock input information at pin 8 of NAND gate 79 will cause the Q output at pin 9 to go to logic 0 except when the preset input is held at logic 0. Set. Therefore, when the composite sync signal on time line 4 sets the Q output of flip-flop 83, it means that the low-to-high transition 282 or 284 is on time line 2, depending on whether a color or monochrome signal is being processed. or 3 at the end of the horizontal sync interval which occurs high at pin 8 of NAND gate 79 until composite sync goes low. As a result, the Q of flip-flop 83 is
A transition 286 at the output occurs, representing the end of the "wide sync" period. It does not depend on whether a color or monochrome signal is being processed, since the sync signal interval is the same in either case. Transition 286 on time line 5 occurs after the end of the horizontal synchronization interval represented by composite synchronization signal transition 186 and must be clocked with the TP-3 signal and the 4Fsc clock signal. For this purpose it is provided in a flip-flop 87. The D input of flip-flop 87 is connected to the Q output of flip-flop 89, the D input of flip-flop 89 is connected to point TP-3, and its clock input is coupled to the 4Fsc clock.
Flip-flop 87 is clocked by the 4Fsc signal and produces at its Q output the signal A6 shown by time line 9 in FIG. This signal is a "prelude" to the wide sync signal.

In FIG. 8, the Q output signal from flip-flop 83, shown on time line 5, is also connected to the D input of flip-flop 85. The Q output at pin 5 of flip-flop 85 is set to logic 1 by transition 154 of the composite sync signal. The Q output of flip-flop 85 is reset to logic 0 after the high-to-low transition 286 of the wide sync ``lead'' signal from the Q output of flip-flop 83 upon the occurrence of certain conditions. This condition occurs at the time of the next low-to-high transition on the clock input of flip-flop 85. The clock input of flip-flop 85 is NAND gate 79/flip-flop U.
95, the next low-to-high transition will be either transition 288 or 290 of time line 2 or 3, depending on whether a burst gate signal is present, ie, whether a color or monochrome signal is being processed. This resulting output signal transition at the Q output of U 134 is shown at 292 and 294 on time lines 6 and 7 of Figure 8 for burst gate present and burst gate absent, respectively. Q of flip-flop 85 on line 91
This signal at the output is a "forehead" signal for the wide burst signal A7 in time line 10 of FIG. 4 in defining the duration of the wide sync signal, although it is not its starting time. The start time of the wide burst signal is determined by the 4Fsc clock and TP.
-3 signal and gating the result with a signal referred to as Brutzf's blanking signal, described below.

The Q output of flip-flop 85 on line 91 is gated through NAND gate 80. NAND gate 80 converts this signal into a burst-off signal and flip-flop 83 on line 93.
is gated with the Q negative output of , generating the signal on time line 8 in FIG. The burst-off signal is a logic 1 when the color signal is being processed;
It therefore does not block the passage of the signal on line 91 during color processing, but it does prevent the burst-off signal from passing through gate 80 during times when it is a logic 0 indicating conditions or monochrome processing where digital synthesis of the burst signal is not desired. Block the passage. Time line 8 does not indicate a condition in which the burst-off signal would block the passage of the signal on line 91 through gate 80. The Q-NATE output of flip-flop 93 on line 93 is connected to flip-flop 8.
To create transitions opposite to these with a Q output of 3,
Transition 286 on time line 5 causes the output of gate 80 to make transition 295 on time line 8 because the signal on line 91 is a logic one at this time. The high-to-low transition 292 of the signal in line 91 during color processing gives rise to the low-to-high transition 252 in time line 8 of FIG. The signal on time line 8 at the output of gate 97 is another "advanced" signal A for wide burst signals. All that remains to complete the generation of the wide burst signal is to reclock the signal on line 97 with the TP-3 and 4Fsc signals and gate it with another signal, namely the Brutzf blanking signal. To accomplish this, the signal on line 97 is reclocked by flip-flops 82 and 84 with the 4Fsc and TP-3 signals and gated with the Brutzf blanking signal in gate 88 to generate the A7 address signal. This address signal A7 is only a "forehead" of the wide burst signal shown by time line 10 in FIG. The actual wide burst signal is the address signal A to generate the output pit D4 shown at time line 10 in FIG.
PROM1 by decoding 0-A7
Generated by 00. This Brutzf blanking signal is only valid during PAL signal processing.
In PAL processing, there is one horizontal line interval of each vertical blanking interval without any burst synchronization signal during the vertical blanking interval. The time of occurrence of each such horizontal line interval varies in each field of each frame in a periodic manner called a Brutzf sequence. The Brutzf blanking signal is not digitally synthesized during these horizontal line intervals of vertical blanking intervals that do not support bursts so that the burst synchronization signal is not present when processing the PAL signal.

The operation of flip-flops 82 and 84 is illustrated in the timing diagram of FIG. Time line 3 shows the D input signal at pin 12 of flip-flop 82 which is connected to output pin 12 of gate 80.
This signal is clocked by the 4Fsc clock to create transitions 96 and 98 on time line 4, where the Q inverted output at pin 8 represents the reclocked output of gate 80. flip flop 84
The Q negated output at pin 6 of is shown on time line 5. This signal represents the output of gate 80 which is reclocked with the TP-3 signal at pin 3 from the Q output of flip-flop U121. The signals at time lines 4 and 5 are then ANDed by gate 86 to be another "predecessor" to the A7 wide burst signal at pin 6 of gate 86.

The A5 address signal is a digital transfer edge gain control value that is PROM of the second digital number generator 28.
plays a part in controlling the order in which they are accessed. PROM100 has address signals A0-A7
and generates output bits D0-D7 according to a truth table that can be given from FIG. These output bits D3-D7 are D from latch U97.
3--the signal at the output line designated D7. The D0-D2 output bits correspond to the pair in Figure 5D.
The envelope shaped address bits AM0-AM2 at bus 120 are coupled to the address ports of PROMUs 99 and 111. The states of these address bits AM0-AM2 are represented as the states of three bits D0-D2 on time line 1A of FIG. During the formation of edge A, three bits D0-D2 decode address bits A0-A7 in the sequence 7, 6, 5, . . . 0.
During edge B, address bits A0-A7 define eight addresses during the eight clock cycles of edge formation that are different from the eight addresses defined by A0-A7 when edge A is formed. The contents of the eight addresses accessed during the formation of edge B are for the eight sample points for the sine-squared edge gain control value of the sine-squared edge accessed in the sequence 0, 1, 2,...7. An 8-bit pattern for bits D0-D2, which is the address given to a pair of PROMUs 99 and 111, is defined. The sequence for all other edges is that represented on time line 1A in FIG.

The A5 signal is the address bit provided to address bus 120 by adder 101 (Figure 5B).
The process of changing the order of access of the gain control values is aided by inverting the bits that select a particular one of the 16 families of curves selected by AM3-AM6. The reason for this becomes clear by examining FIGS. 2 and 3. If address bits AM3-AM6 select edge _E1 , then the inversion of bits AM3-AM6 selects edge _E16.
This is the choice. The reason why this is necessary is best explained by an example. - at the output of the first digital signal generator to form a falling sync edge 48 shown in time line D of FIG.
It is necessary to multiply the _114.10 digital signal by a series of digital transition gain control values (these increase in value from _0.10 to _1.0.10 and define a sine-squared edge). E ₁ in FIG. 3 is one such sequence of gain control values. The first and second gain control values in the _E1 edge type do not have the same value, but the seventh and eighth gain control values have the same value. If the sequence of gain control value recovery is reversed to form a rising edge 50 at time line D of FIG. ₂ , the edge shape A different edge shape will be for edge 50 than for edge 48. This means that if the Edge E ₁ gain control values are accessed in the opposite order, the eighth value is the first gain control value (which is multiplied by the digital signal value representing the peak amplitude -114). This is because the seventh gain control value becomes the second gain control value used for multiplication. In order to have the same edge shape for edges 48 and 50, the 8th and 7th gain control values for edge E ₁ must be different from the 1st and 2nd gain control values for E ₁ . . This is not true for E ₁ , but it is true for edge E ₁₆ , where the A5 address bit is inverted by inverting address bits AM3-AM6.
E ₁₆ becomes selected for restoration of its gain control value upon formation of edge 50. A similar situation exists for all edge formations for all synchronization signals in both vertical and horizontal blanking intervals. The A5 signal is generated by flip-flop 9 which reclocks the TP-2 signal at the D input with the TP-3 signal as it is reclocked by flip-flop 89 with the 4Fsc clock signal.

All address signals A used to access a pair of PROMUs 99 and 111 while storing digital values to be used in multiplication.
0-A7 are generated as they are synchronized with the 4Fsc clock. This helps maintain the scheme's high degree of phase stability between the video information signal and the synchronization signal being digitally combined, and between the synchronization signals themselves.

Signals A0-A7 are on time line 11-1 in FIG.
Timing PROM that generates the signals shown in 5.
Used as address input to 100. These signals provide the timing for horizontal blanking, horizontal sync, vertical blanking, sawtooth of the vertical sync interval, and digital synthesis of the equivalent pulse sync signal. The purpose of PROM 100 is to decode address signals A0-A7 to generate the signals shown on time lines 11-15 of FIG. This simplifies the generation of the timing signals mentioned above. PROMU99 and U111 address the A0-A7 addresses because they need to be described below for the generation of the timing signals shown on time lines 11-15 in FIG. It cannot be directly addressed using signals. These signals are important for the correct generation by the first digital signal generator of digital signal values representing the peak amplitude values of the various synchronization signals for the various television standards for which the synchronization signals are to be generated. Using separate logic to decode address signals and generate the necessary timing signals adds circuit complexity. The pool representation representing various times in the time line of Figure 4 is the bus line 1 of a particular binary word.
Points to the address that causes the output at 02.
Each bit of each of these binary words has a logic state indicated for the signal corresponding to that bit on time line 11-15 of FIG. The corresponding state of address bits A0-A7 that causes the generation of each output binary word D0-D7 at any particular time is reflected in the pool representation of address bits corresponding to that particular time. These binary output words are reclocked by a latch 104 consisting of eight D flip-flops clocked by a 4Fsc clock at pin 11. The outputs of these latches are the sync/burst signal, the narrow blanking B signal, the wide blanking signal, the wide burst signal, the narrow blanking A signal, and the envelope forming signals AM0-AM2. The purpose of each of these signals is explained below in conjunction with a description of the logic into which they are input.

The sync/burst signal at time line 14 is from the leading edge of the horizontal blanking interval to the end of the horizontal sync interval (at which time it goes high for the duration of the burst period and remains high until the beginning of the next blanking interval).
It's as low as. This signal makes a similar transition during the vertical blanking interval.

The sync/burst signal is applied to the input of the first digital signal number generator 26 to signal the logic when transitions between sync and burst occur. This causes the first digital signal number generator to change the digital signal value at its output from a value representing the peak amplitude of the synchronization to a value representing the peak amplitude of the burst signal. To understand how this occurs, refer to Figures 5C and 10. FIG. 5C shows the first one in which multiplexer 22 is connected by bus 108 to the outputs of two multiplexers U61.
indicates that it has an input for receiving the output of the digital signal number generator. These multiplexers output 10 bit digital data representing the magnitude and sign of the peak amplitude of all synchronization signals. FIG. 10B represents a binary bit pattern representing the peak amplitudes of the synchronization signals to be generated and their relationship to the signal shown in FIG. 10A. The signals of FIG. 10A represent the signals that generate the bit pattern shown in FIG. 10A. The lines identify which bits are indicated by the bit significance indicators, such as ²⁰ , written on each line above from the outputs of multiplexers U61 and U62. The line identified by ²⁰ is the least significant bit of the 10-bit data and is coupled to pin 11 of U76.

The digital level assignments (relative to values equivalent to their analog values in the decimal system) for the respective peak amplitudes of the horizontal and vertical blanking interval synchronization signals are as follows. Sync=-114,
Burst = +57 and -57 for alternating peaks, Blanking = 0, Beak White = +414. The same values are used for the peak amplitude of the synchronization signal in the vertical blanking interval. The NTSC standard is
The vertical sync interval sawtooth and equalization pulses start at the same level as the horizontal sync pulses and have the same peak amplitude as the horizontal blanking level. Also, the vertical synchronization interval starts from the horizontal blanking level and has a peak amplitude equal to the peak amplitude of the horizontal blanking level. The remaining synchronization signals in the vertical blanking interval time interval following the post-equalization pulse interval are repeats of the horizontal blanking interval synchronization signals. The color burst interval exists in the vertical blanking interval portion that follows the post-sync interval when a color video information signal is being processed. Different digital peak amplitude levels are PAL
Used for reference synchronization signal generation.

The bit patterns for the synchronization, blanking and burst synchronization signals exhibit certain characteristic patterns that are preferably used to simplify the circuitry of the first digital signal number generator 26. For example, all bits in bit positions 2 ⁷ , 2 ⁸ and 2 ⁹ (sign bits) are always the same and only alternate between logic 0 and logic 1 states to represent a level.
Therefore, the lines representing these bits work together. The same is true for bits in bit positions ²⁴ and ²⁵ . All other bits are unique. During burst intervals, either horizontal or vertical blanking intervals, the sync/burst signal is a logic one and the wide burst signal is a logic one. These two signals are connected to the preset and clear inputs of two flip-flops 187 and 189 as shown in FIG. 5C. Both of these flip-flops are Fairchild's 74F74
It is.

Therefore, during the burst interval, both flip-flops 187 and 189 free run in synchronization with the 4Fsc clock signal and without interference from the signals at their preset and clear inputs, and they are both at the active low level. be. The result is as follows during the burst interval. The two flip-flops are clocked by 4Fsc clock pulses. The D input of flip-flop 187 is coupled to the Fsc rate clock via inverter U74 and exclusive OR gate U70. Exclusive
The other input to OR gate U70 is a decoder (not shown) that decodes a signal from the user console that indicates which television standard is being processed.
is combined with This signal either inverts the Fsc clock signal through an exclusive OR gate or passes it through the gate without being inverted according to practical television standards. Flip Flop 189 D
The input is coupled to the 2Fsc clock via exclusive OR gate 191. Gate 191 either inverts the 2Fsc clock signal or passes it through without inverting, depending on the state of the NTSC(-) reference determination signal decoded from the user console input.
This signal is logic 0 when operating in NTSC standard.
, and the gate 191 is in a passing state. The Q output of flip-flop 189 is therefore 4Fsc
Logical 0 to 4Fsc between 2 clock cycles
It alternates up to a logic one between two cycles of the clock. This output is passed through inverter U63 to 2
It is connected by line 193 to the enabling inputs of two multiplexers U61 and U62. line 19
When the signal at 3 is a logic 0, the multiplexer output is enabled and provides the bit pattern of the selected input on output bus 108. If the multiplexer outputs are not enabled, they provide an all zero bit pattern to the output bus 108. These all zero bit patterns represent the zero reference line level of the burst signal of the signal shown in FIG. 2B.
This zero level reference line segment best represents the burst zero crossings of the analog filtered output. Their time positions are A whose zero reference line segments are synchronized with the clock signal and whose time positions vary with the changing preload count of U72.
Because it occurs without response to the 0-A7 address signal, it does not change with changes in the preload count loaded into counter U72 of FIG. 5A. This is such that a coarse adjustment of the sync-to-subcarrier phase is achieved because the sync-to-subcarrier phase is measured from the edge of sync to the zero-crossing of the burst interval. The time positions of the synchronization, blanking, and burst envelope edges change with changing preload counts, but the zero crossings of the burst interval do not change with changing preload counts. Therefore, the synchronization versus subcarrier phase can be made to change by one quadrant at a time by changing the preload count of U72.

The particular inputs of multiplexers U61 and U62 that are selected are controlled by signals 625/525 from a reference decoder (not shown). This signal indicates which of the various criteria are valid.
Since the peak amplitude levels for the various synchronization signals are different under different criteria, the multiplexer U
The input data for the A and B inputs to U61 and U62 are such that one input data pattern represents the peak amplitude level for the synchronous burst under one criterion and the other input data pattern represents the peak amplitude level for the synchronous burst under the other criterion. is set to represent the peak amplitude level for. Then signal 625/
525 selects the appropriate input data pattern according to the particular criteria in effect at this time.

During the burst period, the peak amplitude ranges from 0 to +57
, then back to 0, then to -57, then back to 0, and so on, completing one complete cycle of the subcarrier, or one Fsc clock cycle. The signal on line 193 controls the transition of the output bit to the 0 level by disabling the outputs of multiplexers U61 and U62 at appropriate times, as will be apparent to those skilled in the art. Exclusive OR gates 195 and 197 connect flip-flops 187 and 189 and inverter U6.
3 and decodes the input signal described above so that the appropriate bit pattern occurs for the appropriate duration and at the appropriate time at the A and B inputs of multiplexers U61 and U62. The manner in which this decoding is performed is shown in the interconnections shown in FIG. 5C, the signal timings shown in FIGS. 4 and 10, and in FIG. 10B.
The various bit patterns under the NTSC standard will be apparent to those skilled in the art. This decoding at the input of the multiplexer causes the appropriate digital signal values representing the peak amplitudes of the various synchronization signals at the horizontal and vertical blanking intervals to be coupled via multiplexer 22 to the A input of multiplier 20 at the appropriate time. occurs at the appropriate time and duration for various criteria at the output bus 108.

Regarding other signals generated by the timing PROM 100 of FIG. 5B, a wide burst signal is a signal that indicates the presence of a burst interval. It is not generated when the burst gate and burst off (-) signals indicate the absence of a burst to be generated. The wide burst signal has a certain criterion, i.e., edge D at time line 1 in Figure 4.
It is high before the start of the color burst interval during color processing under and low after the end of the burst interval, ie, after edge E in time line 1.
As mentioned above, this wide burst signal is used to preset the Q and Q negation outputs of flip-flop 187 to logic 1 during the synchronization interval and to prevent bursts from forming under certain criterion-dependent conditions. 525 standard with prescribed signals
Used as one address bit to PROM U99 and 111. A wide blanking signal and narrow blanking A and narrow blanking B signals are similarly generated. These signals are discussed below with respect to the logic to which they are coupled. Narrow blanking A
The difference between the signal and the narrow blanking B signal is used for downstream timing logic where one is slightly delayed from the other and the propagation gate delay delays the arrival of the signal to be timed by it. It just means that it can be done.

In FIG. 5C, the second digital number generator 2
8. Multiplexer 22 and multiplier 20
The remaining logic not yet discussed will now be explained. Multiplier 20 has its A inputs Y0-Y1
The TRW 112KJ4C accepts one digital number at 1 and multiplies it by another digital number (received at B inputs X0-X11). These A inputs form the multiplexer 22.
AND29821 High Performance Bus Interface Registers are coupled to the outputs of U77 and U76. Each of these flip-flops has a D input coupled to an input port consisting of pins 2-11 and has a 4Fsc
It consists of a plurality of D-type flip-flops having clock inputs coupled together to pin 13 for receiving clock signals. Each of these flip-flops has its Q coupled to one of the output pins 14-23.
All these output pins are pin 1 which are coupled to a gate circuit which will be described in more detail below.
They are simultaneously enabled or disabled depending on the state of the output enable signal at. Flip-flop U77 has an input for receiving level-shifted 10-bit, two-complement format digital video data on bus 106 from video signal processor 24. U76 has an input connected to bus 108 that supports digital signal values that define the peak amplitudes of the various synchronization signals.

Multiplexer 22 connects the output of either U77 or U76 to the A input, ie the A input of FIG. 1, depending on which one is enabled by the gate circuit. This gate circuit is timing PROM1
00 to enable the U76 latch output during horizontal and vertical blanking intervals. This connects the digital signal value from the first digital signal number generator 26 to the A input of the multiplier when the peak amplitude digital signal value is to be inserted into the stream of video information digital data coming into bus 106. do. This allows the creation of new digital format synchronization signals.

As mentioned above, the switching action by multiplexer 22 is provided by gates 114, 116 and 11
The horizontal blanking signal (narrow blanking A signal) is gated with the SECAM Bottle Enable (-) signal by 8. this
SECAM bottle enable (-) signal is for all NTSC
and is a logic 1 during PAL operations and is only assigned a logic 0 level during the vertical blanking interval of SECAM operations. For this reason, NTSC and
The SECAM Bottle Enable (-) signal is a logic 1 during all of the time during PAL operation. The narrow blanking A signal is a logic 1 from the time just after the leading edge of blanking, ie, edge A of FIG. 4, to the time just before the trailing edge of blanking, ie, edge F of FIG. 4. If the narrow blanking A signal is logic 1 and
When the SECAM Bottle Enable (-) signal is a logic one, the output of gate 116 is low thereby enabling synchronization and burst latch U76 and transmitting digital data to first digital signal number generator 2.
6 to the A input port of the multiplier 20. Gate 114 inverts the narrow blanking A signal thereby causing gate 118 to disable the output of multiplexer U77. This is the A of multiplier 20 when the peak amplitude digital signal value is input to the multiplier.
Video data on the bus 106 is blocked from reaching the input. A reference of digital data representing the peak amplitude of the synchronization signal to be digitally synthesized at the correct time controlled by the synchronization signal generator 27 and at digital sample data representing the video information or image portion of the overall television signal. Video information is accurately inserted into the digital data stream in synchronization with the clocking clock. The output of gate 118 is narrow blanking A
Enables the output of latch U77 during times when the signal is a logic 0, i.e., outside the vertical and horizontal blanking intervals.

The reason the narrow blanking signal is used to generate the enabling signals to U77 and U76 of multiplexer 22 is that the video is at the blanking level and the gain of the multiplier is zero at the edge transition of the narrow blanking signal. This is because there is. This prevents the generation of spurious signals during multiplexer switching operations. In other embodiments, the new superimposed blanking signal may be based on the bus 4 instead of being based on the original video blanking pulses.
It can be coupled to the A input of multiplier 20 to be multiplied by a gain number of 2. Based on the blanking pulses of the original signal is used in the preferred embodiment because the timing of blanking is less important than the timing of synchronization and bursting and it makes the circuit more simple.

The digital signal value from the first digital number generator 26 is multiplied in a multiplier 20 by a digital transition edge gain control number that ranges from 0 to 1.0 in the decimal system. These gain control numbers are reproduced from PROM U99 and 111 in FIG.
is applied to the B input of The PROM U99 stores gain control numbers to define the edge shape for only the sawtooth portion of the horizontal and vertical sync signals, front and rear equalization pulses, and vertical sync pulses. The digital transition edge gain control values that define the edge shapes for the horizontal and vertical blanking intervals are PROM-U for reasons that will become clear from the description below.
For PROM U99 stored in 111, during the blanking period, the gain number on busbar 42 is a digital number that would represent the transition edge gain control number. During the horizontal blanking interval they are
If converted to an analog voltage, it would represent the waveform at time line 1 of FIG. 4A. During the vertical blanking interval, the digital transition edge gain control number is applied in analog voltage form to the edges of the vertical blanking interval's synchronization signal, i.e. the front and rear equalization pulses, the vertical synchronization interval and its serrations, and the vertical blanking A signal similar in characteristics to that in Time Line 1 of FIG. 4 is defined, except that it defines the time and shape of the occurrence of the horizontal blanking interval signal following the equalization pulse interval after the interval.

During the time between the horizontal and vertical blanking intervals the B input of multiplier 20 is connected to decoder U45;
Reclocking latch U60 receives digital line control numbers sent from the user console at bus 42 via bus 110' and latch 113. The advantage of this is that a digital gain control function for the video information signal can be easily implemented without the need to add a lot of new circuitry. This also makes more efficient use of the multiplier 20, which is extremely expensive. The whole system is made more economical by using it during times when it would be useless if it were used alone for digital synthesis of the synchronization signal.

As mentioned above, the digital transition edge gain numbers that define the desired edge shapes for the horizontal and vertical blanking synchronization signals are stored in PROM U 111. This PROM stores gain control numbers for 525 lines of NTSC standard video blanking pulses. Other PROMs (not shown) are 625
Used to store gain numbers that define the desired edge shape for the horizontal and vertical blanking synchronization signals used in line PAL standards. PROM U 111 is enabled only during the intervals where the leading and trailing edges of the vertical and horizontal blanking intervals are formed. The reason why the gain control number for the blanking synchronization signal is not stored in the PROM U99 is that the rise time of the blanking interval can be arbitrarily changed by gain setting. The edges of the blanking synchronization signal must create a smooth and precisely shaped transition from the amplitude level of the video information signal to the blanking level. Because the video information signal level depends on the gain level set by the operator, special circuitry is required to accommodate changing video information gain levels.

This special circuit is PROM U 111 and bus 201 which couples video information gain control data to the address inputs of this PROM. PROM・
U111 has several families of gain control values stored therein. Each family defines a sine-square shape that creates a transition from a particular video amplitude level to a blanking level. The address input coupled to bus 201 is set by the operator and receives a bit pattern that defines the desired video gain level. Bus bar 201 is coupled to the five most significant bits of the output of latch U45. This latch receives video gain control data from the operator console. The bit at busbar 201 causes selection of the appropriate family of gain control values for the video gain level present at the beginning of a particular blanking interval, whether it is horizontal or vertical blanking. PROM U 111 is enabled only during the time interval when the leading and trailing edges of the blanking interval are formed by ANDing together the narrow blanking and wide blanking signals. From time lines 12 and 13 of FIG. 4, if these two signals are ANDed, the result is the time difference between transition 203 on time line 12 and transition 206 on time line 13. This results in pulses of equal duration. This is the time interval in which edge A on time line 1 (which is the leading edge of the blanking interval) is formed. A similar result occurs for edge F, the tail end of the blanking interval, where the pulse has a duration equal to the time between transitions 207 and 209. This AND function is performed by NAND gate 211 in FIG. 5D. This gate has appropriately inverted wide blanking and narrow blanking A signals as its two inputs. The output of gate 211 is a logic low PROM U61
connected to the chip select input. this is
This results in PROM U111 being activated only at appropriate time intervals.

Eight families of gain control values are provided for each selected gain level. Each has a slightly different phase with respect to the zero crossing of the burst synchronization signal. The particular one of these families selected is controlled by the bit pattern on bus 205. This bus supports three address bits AM4-AM6 from a synchronous to subcarrier phase adjustment circuit which selects the desired synchronous to subcarrier phase. Therefore, the sync-to-subcarrier phase can be adjusted digitally in the system by moving the time position of the blanking and sync edges with respect to the zero-crossings of the burst sync signal.

Once a particular one of the family of gain control values is selected, that particular one of the gain control values output at any particular time is determined by the timing PROM.
100 by the bit pattern on bus 120 supporting address bits AM0-AM2. The order of recovery of these gain control values is
It is controlled in the same way as it is for PROM U99.

Address bits AM0-AM2 are 5th A and 5th
Generated from the A0-A7 address bits generated by the logic in Figure B. The logic of Figures 5A and 5B generates the A0-A7 address bits and timing signals based on the incoming reference sync and clock signals from the reference sync generator. This reference synchronization signal generator operates in synchronization with the station reference clock signal. It will be appreciated that because the video information processing signal is synchronized with this local reference clock, the timing of edge formation of the various synchronization signals is precisely controlled with respect to the video information signal.

The PROM address bits at bus 120 cycle through the addresses to sequentially select transition edge gain control numbers 1-8.
The transition edge gain control number output from the PROM is reclocked via latch 113 placed on bus 42 and clocked by the 4Fsc clock. The gain control value is then applied to the "B" input port of multiplier 20 and
It is used to multiply the number at the input and thereby produce an output stream of digital numbers at port C of the multiplier.

FIG. 5E shows the logic of video signal processor 24. In the embodiment of the digital video information signal as shown in FIG.
128 ₁₀ digital levels are subtracted from the incoming digital video information samples coming from the left side of busbar 38 by adding 384 digital levels to the incoming binary data. These video information samples of the incoming binary data are binary numbers representing the result of analog-to-digital conversion of the video signal at a certain sampling rate. In the preferred embodiment, the sample rate is four times the subcarrier frequency. The video signal processor also converts the digital video sample data to two's complement to make it compatible with the operation of multiplier 20.
Additionally, the video signal processor transforms the incoming 9-bit data into 10-bit data by adding a sign bit that is 0 for levels above the blanking level and 1 for levels below the blanking level. Convert to The overall operation of the video signal processor is to output 2 of the 9 bits leaving the blanking level which is 128 ₁₀ of the incoming video data.
, and add a sign bit as the _10th bit.

The features mentioned above apply to Carry 115, 117 and 11.
three 4-bit binary full adders with 9, clocking latch 123 and re-clocking latch 1
Done at 25. Incoming digital data is coupled to the "B" input of the adder via a clocking latch 123, which is clocked by a 4Fsc clock so that when it arrives at the adder it is synchronized with the rest of the system. I am forced to do it. The carries from each adder are combined with the carries to the next higher significance adder. The carry from the most significant adder 119 is coupled through an inverter 121 to the tenth bit of the output data bus 106'. The "B" outputs of these adders are combined into 9-bit digital video information data. _B3 of adder 115 is the least significant bit of input data
CL0, and this adder _B3 input is the most significant bit CL8 of the 9-bit input data. This binary video information input data has levels varying from _0.10 to _512.10 , where the sync chip is at 14 and the blanking level is at 128. The purpose is to convert the blanking level to 0 ₁₀ and add the sign bit as the 10th bit, thereby converting to the complementary format of 2. To do this, ₃₈₄₁₀ is added to the input binary signal and the carry overflow of adder 119 is inverted and coupled to the tenth bit, the sign bit of output bus 106'. This is done as follows.

The A inputs of these adders are coupled by bus 37 to an 8-bit number consisting of bits B0-B7 from the constant generator. This constant generator is actually a black level adder; however, for purposes of the present invention, bits B0-B7 support a bit pattern equal to ₁₂₈₁₀ . That is, bit B7 is logic 1.
and all other bits are logic zero. B ₂ and A ₂ of adder 115 are installed to prevent them from floating. Therefore, if busbar 37 were the only one, only 128 would be added. However, adder 119
A ₃ input is the binary number 100000000 equal to 256 which is 2×
It is similarly coupled to a logic 1 by wire 43 representing 10 ⁹ . Therefore, 256+128 are added to the input binary data for a total of 384 digital levels.
These 384 digital levels are added to the input data as a bias. The result is that the blanking level of 128 ₁₀ in the input binary data representing video information is 1000000000 or 2 ₁₀ 512 ₁₀
It is to be converted into. The tenth bit of logic one, representing level ₅₁₂₁₀ , is provided from the carry-out output at pin 9 of adder 119, which is inverted to be the sign bit of zero. 128 ₁₀
The resulting output word at bus 106' for the blanking level input is 1000000000 or 0 ₁₀ plus 10 of 9 bit data to create a 10 bit output word.
0 sign bit as the th bit. 12
8 All input values greater than or equal to ₁₀ have a 0 sign bit and X ₁₀ +
384 ₁₀ - 512 ₁₀ plus a bit pattern representing 384 10 -512 10. where X is the decimal equivalent of the input binary number.

These ten bits on bus 106 are reclocked to output bus 106 by reclocking latch 125. This latch 125 is similar to the input clocking latch 123 on line 36.
It is clocked by the 4Fsc clock signal.
The resulting converted data is provided to multiplexer 22 at output bus 106.

The output of multiplexer 20 at bus 51 is a digitally controlled video gain and a new digitally synthesized horizontal sync, equalization pulse, vertical sync interval, sawtooth, color burst, horizontal and vertical blanking. A stream of digital numbers representing a composite video signal with a synchronization signal. The circuitry that can be used to perform the digital-to-analog conversion of converter 39 and the filtering of filter 41 of FIG. 1 is well known to those skilled in the art and will not be described here.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a preferred embodiment of the present invention. FIG. 2 is a timing diagram representing signals that are multiplied to form a synchronization signal for insertion into a television signal in accordance with a preferred embodiment of the present invention. FIG. 3 is a diagram of eight samples forming the digital gain control value stored in a programmable read only memory (PROM) to form the signal transition edges of the television synchronization signal. Figures 4A and 4B are timing diagrams of various signals associated with various occurrences applied to a multiplier to form a television synchronization signal. 5A-5E illustrate a logic diagram of the preferred embodiment of the present invention of FIG. 1 with the D/A converter and low pass filter removed. FIG. 6 shows a timing diagram of the various signals used to effect the generation of address and timing signals that control the first and second digital signal generators. FIG. 7 shows various timing diagrams used to clock the logic that generates the wide sync and wide burst signals. FIG. 8 is a timing diagram of the signals involved in forming the wide sync and wide burst signals. 9th
The figure is a timing diagram of signals generated in forming a wide burst signal. Figure 10 shows the first peak amplitude of the synchronization signal to be synthesized in binary form.
FIG. 2 is a timing diagram and truth table for the digital generator signals of FIG. In the figure, 20 is a digital multiplier, 22 is a multiplexer, 24 is a video signal processor, 25
is a constant generator, 26 is the first digital number (signal)
27 is a reference signal generator, 28 is a second digital number (signal) generator, 39 is a D/A converter,
41 indicates a low pass filter.

Claims (1)

Claims: 1. A device for digitally generating a synchronization signal, comprising first means 26 for providing at least one digital signal value representative of an amplitude peak of said synchronization signal; second means 28 for providing at least one set of digital gain control values occurring synchronously with the beginning and end of each synchronization signal time interval;
and means 2 for multiplying each of a set of digital gain control values from said second means by a corresponding digital signal value from said first means and outputting a digital signal representing the digital product of said multiplication.
0, a reference signal generating means 27 for generating a common reference timing signal defining a synchronization signal time interval, and a reference signal generating means 27 for controlling the timing of supply of the digital signal value and the gain control value of the set, respectively. means 30,3 for coupling the reference timing signal to both the first means 26 and the second means 28;
2. A television synchronization signal waveform generator characterized by comprising: 2, 34. 2. A television synchronization signal waveform generator as claimed in claim 1, wherein said second means 28 stores at least one set of digital gain control values in a sin ² edge type digital representation. 3. Said synchronization signal comprises a burst signal consisting of a plurality of cycles of synchronization signal and subcarrier signal, said second means 28 storing a family of sets of digital gain control values, each set containing all of said synchronization signals. 3. A television synchronization signal waveform generator according to claim 1, wherein each set has a different synchronization with respect to the subcarrier phase relationship. 4 Said second means 28 are selected to receive said reference timing signal and generate address signals therefrom to access and couple to said means for multiplication a particular set of said family of sets of gain control values. 4. The television synchronization signal waveform generator of claim 3, wherein the television synchronization signal waveform generator is configured to access a set of gain control values. 5 said first means 26 having a video information input;
having an input for receiving a digital signal value from
It further includes multiplexer means 22 having a control input coupled to receive a reference timing signal for controlling switching between said inputs, wherein said means 20 for multiplication includes a plurality of multiplexer means 22 coupled to the output of said multiplexer means. 5. A television synchronization signal waveform generator as claimed in claim 4, having one input and a second input coupled to the output of said second means. 6 Said second means 28 is a memory having address inputs, control inputs and data outputs, said memory synchronizing said gain control values at appropriate times to define the edges of said synchronization signal as sin ² shaped edges. 3. The television synchronization signal waveform generator of claim 2 further comprising means for generating a plurality of address and control signals coupled to said address and control inputs for output. 7. The television synchronization signal waveform generator of claim 2, further comprising means for reversing the sequence of accesses of said gain control values upon formation of a predetermined edge. 8. Said second means 28 are a memory having an address input, a control input and a data output, said memory instructing said gain in a first sequence at an appropriate time to define a first edge of said synchronization signal. said address and address such that said memory synchronously outputs said gain control values in reverse sequence at appropriate times to output control values synchronously and to define a second edge of said synchronization signal; 3. A television synchronization signal waveform generator as claimed in claim 2, further comprising means for generating a plurality of address and control signals coupled to a control input. 9. A television synchronization signal waveform according to claim 1, comprising means 24 for supplying the video signal as a digital value representative of the amplitude of the video signal, said digital value being supplied in synchronization with a clock signal. Generator. 10 Said means 24 for providing a video signal
multiplexing means having a first input coupled to said first means and having a second input coupled to said first means further having a control input coupled to said means for providing a reference signal as well as an output; , the multiplexing means is configured to combine either the first input or the second input with the output depending on the state of the reference signal, and the multiplication means 20 is configured to combine the output of the multiplexer with either the first input or the second input. 10. The television synchronization signal waveform generator of claim 9 further comprising a digital multiplier having a first input coupled thereto and having a second input coupled to said second means. 11. In an apparatus for digitally generating a synchronization signal having edges of a predetermined shape for insertion into a video signal to form a composite video signal, means for sequentially generating a plurality of addresses; memory means 28 for storing at each said address a digital gain control value having a magnitude defining the shape of said edge and for outputting the digital value stored at each said address when the address is generated; each said digital gain control by a digital signal value representing a preset signal having at least a predetermined amplitude during the time said digital gain control value is outputted to output a synchronization signal of said digital gain control value; comprising means 20 for multiplying values and a reference timing signal generator 27 configured to provide a common timing signal controlling the initiation of generation of said addresses and the provision of preset signals. A television synchronization signal waveform generator characterized by: 12. Claim 11, wherein said memory means stores digital gain control values defining the blanking and synchronization pulse edge shapes of the video mechanism.
The television synchronization signal waveform generator according to paragraph 1. 13. The television synchronization signal waveform generator of claim 12, wherein said memory means further stores digital gain control values defining the shape of the burst envelope of the video mechanism. 14. A method for digitally generating a synchronization signal, comprising: providing a first plurality of digital signal values representative of amplitude peaks of the synchronization signal; generating the first plurality of digital signal values; providing a second plurality of digital signal values representative of a desired shape of the edges of the synchronization signal in a synchronization relationship determined by the method; and controlling the timing of the provision of the first and second plurality of digital signal values. generating a common reference timing signal; and multiplying the first and second plurality of digital signal values to obtain a plurality of digital product values representative of the desired synchronization signal shape and amplitude. Television synchronization signal waveform generation method. 15. converting the video signal into a third plurality of digital video signal values using a predetermined clock signal; generating the first and second plurality of digital signal values in synchronization with the clock signal; applying the first plurality of digital signal values to the stream of the third plurality of digital video signal values for a selected time interval; and generating a plurality of digital product values defining the synchronization signal. 15. The television synchronization signal of claim 14, further comprising the step of multiplying said first and second plurality of digital signal values in synchronization with said clock signal for said selected time interval. Waveform generation method. 16 converting the resulting output stream of digital products into analog values after the step of applying to said stream in a digital-to-analog converter operating synchronously with said clock signal and generating this analog output via a reduction filter; the filter further includes a step passing through the filter having an upper corner frequency approximately equal to twice the color subcarrier frequency and having a frequency of at least -6 dB at twice the color subcarrier frequency; 16. The method of claim 15 having an upper stopband that rolls off to at least -55 decibels at a frequency three times the carrier frequency. 17. The patent further comprising the step of, at the user's option, multiplying the third plurality of digital video signal values by a digital gain number or a stream of varying digital gain numbers during a time when the step of applying to the stream does not occur. A television synchronization signal waveform generation method according to claim 16.