JPH0362956A - Semiconductor chip carrier - Google Patents

Semiconductor chip carrier

Info

Publication number
JPH0362956A
JPH0362956A JP1198833A JP19883389A JPH0362956A JP H0362956 A JPH0362956 A JP H0362956A JP 1198833 A JP1198833 A JP 1198833A JP 19883389 A JP19883389 A JP 19883389A JP H0362956 A JPH0362956 A JP H0362956A
Authority
JP
Japan
Prior art keywords
metal plate
semiconductor chip
heat
recess
adhesive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1198833A
Other languages
Japanese (ja)
Inventor
Koji Minami
浩司 南
Takeshi Kano
武司 加納
Kaoru Mukai
薫 向井
Masaki Tanimoto
谷本 正樹
Toru Higuchi
徹 樋口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP1198833A priority Critical patent/JPH0362956A/en
Publication of JPH0362956A publication Critical patent/JPH0362956A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To increase the freedom of the shape of an external heat radiator and to achieve high integration density, high functions and high speed of a semiconductor chip by providing a first recess part for mounting the semiconductor chip, providing a second recess part for heat radiation in an insulating and bonding layer, and arranging a second metal plate so that the second metal plate extrudes from the second recess part through the insulating layer on the surface of the second recess part of a first metal plate. CONSTITUTION:A semiconductor chip 10 is mounted on a first metal plate 2 in a first recess part 11. Then, the heat generated in the semiconductor chip 10 is absorbed in the first metal plate 2. A second metal plate 8 is arranged at the bottom surface of a second recess part 12 on the opposite side of the first metal plate 2 having excellent heat conductivity through a bonding layer 7 so that the metal plate extrudes from the second recess part 12. The heat passes through the second metal plate 8. The heat is conducted to the attaching surface which is larger than the outer surface of the second metal plate 8 and attached to the second metal plate 8. The heat is further conducted to an external heat radiating body 9 having fins 17. Therefore, the heat does not stagnate in the first metal plate 2. The heat is radiated into the air. Thus, the carrier can cope with the achievement of the high integration density, the high functions and the high speed of the semiconductor chip 10.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体チップ搭載に用いられる半導体チン
プキャリア関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor chip carrier used for mounting semiconductor chips.

[従来の技術] 半導体チップキャリアを構成する樹脂絶縁層はガラス布
を基材としたエポキシ樹脂積層板などのプリント配線板
が用いられ、このようなプリント配線板は熱の伝導性が
悪くて放熱を良好になすことができない。先に本発明者
らは、特開昭62−052992において第3図に示す
如くプリント配線板から構成された半導体チップキャリ
アの放熱性を良好にするためにプリント配線板の絶縁N
1に挿入された金属板2の動きを阻止しさらに、絶縁層
l・と金属板2に生ずる隙間を密閉して耐湿性を高めた
半導体チップキャリアを提供した。ところが、半導体チ
ップの高速化、高集積化、高機能化による半導体チップ
の発熱量の増大にともなって熱放散性の優れた半導体チ
ップキャリアの造出かますます大きく期待される中で、
外部放熱体を前記半導体チップキャリアに取り付けるの
に、金属板2が絶縁Ntの表面より窪んでいるために外
部放熱体の形状に制限が加わり取り付は部が放熱用の第
2の四部12より小さな外部放熱体に制限され、放熱量
の増大をはかる外部放熱体の形状の自由度が小さなもの
であった。
[Prior art] Printed wiring boards such as epoxy resin laminates based on glass cloth are used for the resin insulating layer that constitutes semiconductor chip carriers, and such printed wiring boards have poor heat conductivity and are difficult to dissipate. cannot be made in good condition. Previously, in JP-A No. 62-052992, the inventors of the present invention have developed the insulation N of a printed wiring board in order to improve the heat dissipation of a semiconductor chip carrier composed of a printed wiring board as shown in FIG.
To provide a semiconductor chip carrier which prevents the movement of the metal plate 2 inserted into the metal plate 1 and further seals the gap formed between the insulating layer l and the metal plate 2, thereby increasing moisture resistance. However, as the amount of heat generated by semiconductor chips increases due to faster speeds, higher integration, and higher functionality, there are increasing expectations for the creation of semiconductor chip carriers with excellent heat dissipation.
When attaching the external heat radiator to the semiconductor chip carrier, since the metal plate 2 is recessed from the surface of the insulating Nt, the shape of the external heat radiator is limited, and the mounting part is closer to the second four parts 12 for heat radiation. The external heat sink is limited to a small size, and the degree of freedom in the shape of the external heat sink to increase the amount of heat dissipation is small.

〔発明が解決しようとする課題] 熱放散性をさらに一層高めるための外部放熱体の形状に
加わった制限を解除するとともに、外部放熱体を簡単に
取り付けできる構造の半導体チップキャリアを提供する
ことにある。
[Problems to be Solved by the Invention] To provide a semiconductor chip carrier having a structure that eliminates restrictions placed on the shape of an external heat sink to further enhance heat dissipation performance, and allows the external heat sink to be easily attached. be.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は前記課題を解決するために、絶縁層の貫通穴に
埋入された第1の金属板、この金属板と絶縁層の一方の
表面に絶縁接着層を介して配設された導体回路及び、絶
縁接着層に形成された半導体チップ搭載用の第1の凹部
を備え、他方の表面に配設された絶縁接着層、この絶縁
接着層に放熱用の第2の凹部を設けて前記第1の金属板
の周縁部を被覆する鍔を備え、それぞれの凹部の底面に
露出する前記第1の金属板の第2の凹部の表面に接、、
?7層を介して第2の金属板が前記第2の四部から突出
して配設されてなることを特徴とする半導体チップキャ
リアを提供するものである。
In order to solve the above problems, the present invention includes a first metal plate embedded in a through hole of an insulating layer, and a conductor circuit disposed on one surface of the metal plate and the insulating layer via an insulating adhesive layer. and a first recess formed in the insulating adhesive layer for mounting the semiconductor chip, an insulating adhesive layer disposed on the other surface, and a second recess for heat dissipation provided in the insulating adhesive layer. a flange that covers the peripheral edge of the first metal plate, and is in contact with the surface of the second recess of the first metal plate exposed at the bottom of each recess;
? The present invention provides a semiconductor chip carrier characterized in that a second metal plate is disposed to protrude from the second four parts through seven layers.

〔実施例] 以下に、本発明を図面に基づいて詳しく説明する。第1
図aは本発明の一実施例に係る斜視図。
[Example] The present invention will be explained in detail below based on the drawings. 1st
Figure a is a perspective view of one embodiment of the present invention.

第1図すは外部放熱体を取り付けた第1図aのXY断面
図である。第1図a、bの半導体チップキャリアは絶縁
層1及び絶縁層1の貫通穴3に埋入された第1の金属板
2.この絶縁層lと第1の金属板2の一方の表面に絶縁
接着層5を介して配設された導体回路4及び、前記第1
の金属板2とこの絶縁接着層5に形成された半導体チッ
プ1゜搭載用の第1の凹部11とを備えている。そして
、他方の表面にも絶縁接着層5が配設され、この絶縁接
着層5に放熱用の第2の凹部12を設けて前記第1の金
属板2の周縁部を被覆する鍔6が形成されている。前記
放熱用の第2の凹部12が設けられた絶縁接着層5の表
面には導体13が設けられている。この放熱用の第2の
凹部の底面に露出する第1の金属板2と絶縁接着層5の
表面に配設した導体13とを金属N14で接続し一体化
したものでは、熱伝導路の確保と放熱面の拡大の点で放
熱には一層有利である。なお、第11第2の凹部11,
12としての形状は周知の如く四角柱状が一般的である
が特に制限する趣旨ではなく円柱などでもよい。上記構
成の半導体チップキャリアにおいて、第1の凹部11の
第1の金属板2に半導体チップ10を搭載すると半導体
チップ1゜から発生する熱は、第1の金属板2に吸収さ
れさらに、熱伝導性に優れた第1の金属板2の反対側に
おいて、第2の凹部12の底面に接着層7を介して第2
の凹部12から突出して配設された第2の金属板8を通
過し、第2の金属板8に取り付けられた第2の金属板8
の外表面より大きな取り付は面と側面にフィン17を有
する外部放熱体9へと移動し、熱が第1の金属板2内に
こもることなく空気中に放熱されることになって半導体
チップlOの高集積化、高機能化、高速化に対応可能と
なる。なお、第2の金属板8を放熱用の第2の凹部12
に接着N7を介して配設するときに、絶縁層1と絶縁接
着層5の厚さによって第2の凹部12の深さにばらつき
が生しても、断面が台形を有し、両側に勾配が相反する
傾斜辺を有する台形の傾斜辺が前記鍔6の内周端に当接
する第2の金属板8を用いると、常に第2の金属板8は
第2の凹部12の周縁部に隙間を生じることなく第2の
凹部12から突出して配設することができ好ましい、第
2の金属板8の形状は四角錐台に限定されるものではな
く、第2の凹部I2が円の場合は円錐台などと任意に適
したものを選ぶことができる。
FIG. 1 is an XY sectional view of FIG. 1a with an external heat sink attached. The semiconductor chip carrier of FIGS. 1a and 1b includes an insulating layer 1 and a first metal plate 2 embedded in a through hole 3 of the insulating layer 1. A conductor circuit 4 disposed on one surface of the insulating layer l and the first metal plate 2 with an insulating adhesive layer 5 interposed therebetween;
2 and a first recess 11 formed in the insulating adhesive layer 5 for mounting a semiconductor chip 1°. An insulating adhesive layer 5 is also provided on the other surface, and a second recess 12 for heat dissipation is provided in this insulating adhesive layer 5 to form a flange 6 that covers the peripheral edge of the first metal plate 2. has been done. A conductor 13 is provided on the surface of the insulating adhesive layer 5 where the second recess 12 for heat radiation is provided. The first metal plate 2 exposed at the bottom of the second recess for heat dissipation and the conductor 13 disposed on the surface of the insulating adhesive layer 5 are connected with metal N14 to ensure a heat conduction path. This is more advantageous for heat dissipation in terms of expanding the heat dissipation surface. Note that the eleventh second recess 11,
As is well known, the shape of 12 is generally a quadrangular prism, but it is not particularly limited and may be a cylinder or the like. In the semiconductor chip carrier having the above configuration, when the semiconductor chip 10 is mounted on the first metal plate 2 of the first recess 11, the heat generated from the semiconductor chip 1° is absorbed by the first metal plate 2, and the heat is further transferred to the first metal plate 2. On the opposite side of the first metal plate 2, which has excellent properties, a second
The second metal plate 8 is attached to the second metal plate 8 by passing through the second metal plate 8 disposed so as to protrude from the recess 12 of the second metal plate 8.
The mounting area larger than the outer surface of the semiconductor chip is moved to the external heat radiator 9 having fins 17 on the surface and side surfaces, and the heat is radiated into the air without being trapped within the first metal plate 2. It becomes possible to respond to higher integration, higher functionality, and higher speed of IO. Note that the second metal plate 8 is provided with a second recess 12 for heat radiation.
Even if the depth of the second recess 12 varies depending on the thickness of the insulating layer 1 and the insulating adhesive layer 5 when the second recess 12 is disposed through the adhesive N7, the cross section has a trapezoidal shape and slopes are formed on both sides. When using the second metal plate 8 in which the slope side of the trapezoid having opposite slope sides contacts the inner peripheral end of the collar 6, the second metal plate 8 always leaves a gap at the peripheral edge of the second recess 12. The shape of the second metal plate 8, which is preferable because it can be disposed so as to protrude from the second recess 12 without causing a problem, is not limited to a truncated square pyramid. You can choose anything suitable, such as a truncated cone.

このように絶縁接着層5と第2の金属板8の埋め込み部
分の間に隙間が生じないので水分や湿気の浸透経路を作
らない。そのため半導体チップキャリアの耐湿性を向上
させることができ、半導体チップの耐湿信頼性を向上さ
せる効果をもたらす。
In this way, since no gap is created between the insulating adhesive layer 5 and the buried portion of the second metal plate 8, no penetration path for water or humidity is created. Therefore, the moisture resistance of the semiconductor chip carrier can be improved, resulting in the effect of improving the moisture resistance reliability of the semiconductor chip.

外部放熱体9の第2の金属板8への取り付けは、熱伝導
性に優れた接着剤、半田および、あらかじめ双方にねし
止め加工を施た機械的な方法などを用いることができる
。また、外部放熱体9の形状も角柱で側面フィン17を
有するものあるいは、第2図に示す如く円柱で上面フィ
ン18を有するものなど一般に放熱体、放熱フィンとし
て用いられているものを用いることができる。
The external heat radiator 9 can be attached to the second metal plate 8 using an adhesive with excellent thermal conductivity, solder, or a mechanical method in which both parts are pre-fastened. The shape of the external heat radiator 9 may be a prism with side fins 17, or a cylinder with top fins 18 as shown in FIG. 2, which are generally used as heat radiators or heat radiating fins. can.

なお第1図すでは、第1の凹部11の金属板2に搭載さ
れた半導体チップ10と絶縁接着層5の表面に形成され
た導体回路4は金属線20を介して接続されさらに、こ
の導体回路4は外部端子として働く端子ビン15を挿入
するための絶縁層1と絶縁接続層5に形成されたスルホ
ールのスルホールメツキ層16に接続している。
In addition, in FIG. 1, the semiconductor chip 10 mounted on the metal plate 2 of the first recess 11 and the conductor circuit 4 formed on the surface of the insulating adhesive layer 5 are connected via the metal wire 20. The circuit 4 is connected to a through-hole plating layer 16 of through holes formed in the insulating layer 1 and the insulating connection layer 5 into which terminal pins 15 serving as external terminals are inserted.

また、第2図では、周知の如く絶縁接着層5の端部まで
展設された導体回路4にリードフレーム19を外部端子
として接続し表面実装用の半導体チップキャリアを構成
している。
Further, in FIG. 2, as is well known, a lead frame 19 is connected as an external terminal to a conductive circuit 4 extended to the end of an insulating adhesive layer 5 to constitute a semiconductor chip carrier for surface mounting.

次に、使用材料について述べると、第1図の半導体チッ
プキャリアを構成する絶縁N1及び絶縁接着層5として
は、基材に樹脂を含浸乾燥して得られたプリプレグの樹
脂を硬化した絶縁材料が用いられる。ここで絶縁層lの
樹脂としては耐熱性、耐湿性に優れかつ樹脂純度、特に
イオン性不純物の少ないものが好ましい。具体的には、
エポキシ樹脂、ポリイミド樹脂、フッソ樹脂、フエノル
樹脂、不飽和ポリエステル樹脂、PP○樹脂などが適し
ている。なお絶縁層1及び絶縁接着層5の基材としては
、紙よりガラス繊維などの無機材料の方が耐熱性、耐湿
性などに優れ好ましい。
Next, regarding the materials used, as the insulation N1 and the insulation adhesive layer 5 that constitute the semiconductor chip carrier shown in FIG. used. Here, the resin for the insulating layer 1 is preferably one that has excellent heat resistance and moisture resistance, and has high resin purity, particularly low ionic impurities. in particular,
Epoxy resins, polyimide resins, fluorocarbon resins, phenolic resins, unsaturated polyester resins, PP○ resins, and the like are suitable. As the base material for the insulating layer 1 and the insulating adhesive layer 5, an inorganic material such as glass fiber is preferable to paper because it has better heat resistance and moisture resistance.

絶縁層fFJi5の半導体チップ10の搭載側の表面の
導体回路4やこの反対側の表面の導体13には、銅、真
鍮、アルミニウム、鉄、ニッケル、などから適宜選択し
て適用でき、中でも銅が導電性、熱伝導性に優れ特に好
ましい。導体回路4や導体13を形成するにあたっては
、アディティブ法、サブトラクティブ法などの種々の方
法が用いられる。スルホールメツキ層16や放熱用の第
2の凹部12に露出する第1の金属板2及び、放熱用の
第2の凹部12の内壁から絶縁接着層5の表面の導体1
3を接続し被覆する金属層14は絶縁接着層5の表面の
導体回路4や導体13の形成時にスルホールメツキ法な
どで形成される。
The conductor circuit 4 on the surface of the insulating layer fFJi5 on the side where the semiconductor chip 10 is mounted and the conductor 13 on the opposite surface can be selected from copper, brass, aluminum, iron, nickel, etc., and among them, copper is used. It is particularly preferred because of its excellent electrical conductivity and thermal conductivity. In forming the conductor circuit 4 and the conductor 13, various methods such as an additive method and a subtractive method are used. The first metal plate 2 exposed to the through-hole plating layer 16 and the second recess 12 for heat radiation, and the conductor 1 on the surface of the insulating adhesive layer 5 from the inner wall of the second recess 12 for heat radiation.
The metal layer 14 connecting and covering the insulating adhesive layer 5 is formed by a through-hole plating method or the like when the conductor circuit 4 and the conductor 13 are formed on the surface of the insulating adhesive layer 5.

絶縁N1の貫通穴3に挿入される第1の金属板2、第1
の金属板2に接着層7を介して配設される第2の金属板
8および、第2の金属板8に取り付けられる外部放熱体
9としては、例えばw4Fi、銅合金板、銅−インバー
−銅合金板、鉄−ニッケル合金板、その他鋼板、鉄板、
アルミニウム板などを使用することができる。
The first metal plate 2 inserted into the through hole 3 of the insulation N1, the first
The second metal plate 8 disposed on the metal plate 2 via the adhesive layer 7 and the external heat sink 9 attached to the second metal plate 8 include, for example, W4Fi, copper alloy plate, copper-invar- Copper alloy plates, iron-nickel alloy plates, other steel plates, iron plates,
An aluminum plate or the like can be used.

接着層7を形成する材料としては、銀粉入りエポキシ樹
脂やポリイミド樹脂などを用いることができる。
As a material for forming the adhesive layer 7, epoxy resin containing silver powder, polyimide resin, or the like can be used.

〔発明の効果〕〔Effect of the invention〕

本発明に係る半導体チップキャリアは叙述の如く絶縁層
の貫通穴に埋入された第1の金属板、この金属板と絶縁
層の一方の表面に絶縁接着層を介して配設された導体回
路及び、絶縁接着層に形成された半導体チップ搭載用の
第1の凹部を備え、他方の表面に配設された絶縁接着層
、この絶縁接着層に放熱用の第2の凹部を設けて前記第
1の金属板の周縁部を被覆する鍔を備え、それぞれの凹
部の底面に露出する前記第1の金属板の第2の凹部の表
面に接着層を介して第2の金属板が第2の凹部より突出
して配設されているので、第2の金属板への取り件部の
形状が第2の金属板よりも大きい形状の外部放熱体も容
易に取り付けることができ、外部放熱体の形状の自由度
が大きくなる。
As described above, the semiconductor chip carrier according to the present invention includes a first metal plate embedded in a through hole of an insulating layer, and a conductor circuit disposed on one surface of the metal plate and the insulating layer via an insulating adhesive layer. and a first recess formed in the insulating adhesive layer for mounting the semiconductor chip, an insulating adhesive layer disposed on the other surface, and a second recess for heat dissipation provided in the insulating adhesive layer. The second metal plate is provided with a flange that covers the peripheral edge of the first metal plate, and the second metal plate is attached to the surface of the second recess of the first metal plate exposed at the bottom of each recess via an adhesive layer. Since it is arranged so as to protrude from the recessed part, it is possible to easily attach an external heat radiator whose attachment part to the second metal plate has a larger shape than the second metal plate, and the shape of the external heat radiator The degree of freedom increases.

したがって、半導体チップの高集積化、高機能化、高速
化によって増大する発熱に対応可能となるものである。
Therefore, it is possible to cope with the increase in heat generation due to higher integration, higher functionality, and higher speed of semiconductor chips.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す断面図、第2図は本発
明の他の実施例である。 l・・・絶縁層    2・・・第1の金属板3・・・
貫通穴    4・・・導体回路5・・・絶縁接着層 
 6・・・鍔 7・・・接着層    8・・・第2の金属板9・・・
外部放熱体 10・・・半導体チップ11・・・第1の
凹部 12・・・第2の凹部13・・・導体  14・
・・金属層
FIG. 1 is a sectional view showing one embodiment of the invention, and FIG. 2 is another embodiment of the invention. l... Insulating layer 2... First metal plate 3...
Through hole 4...Conductor circuit 5...Insulating adhesive layer
6... Tsuba 7... Adhesive layer 8... Second metal plate 9...
External heat sink 10...Semiconductor chip 11...First recess 12...Second recess 13...Conductor 14.
・Metal layer

Claims (2)

【特許請求の範囲】[Claims] (1)絶縁層の貫通穴に埋入された第1の金属板、この
金属板と絶縁層の一方の表面に絶縁接着層を介して配設
された導体回路及び、絶縁接着層に形成された半導体チ
ップ搭載用の第1の凹部を備え、他方の表面に配設され
た絶縁接着層、この絶縁接着層に放熱用の第2の凹部を
設けて前記第1の金属板の周縁部を被覆する鍔を備え、
それぞれの凹部の底面に露出する前記第1の金属板の第
2の凹部の表面に接着層を介して第2の金属板が前記第
2の凹部から突出して配設されてなることを特徴とする
半導体チップキャリア。
(1) A first metal plate embedded in a through hole of an insulating layer, a conductor circuit disposed on one surface of the metal plate and the insulating layer via an insulating adhesive layer, and a conductive circuit formed in the insulating adhesive layer. a first recess for mounting a semiconductor chip; an insulating adhesive layer disposed on the other surface; a second recess for heat dissipation is provided in the insulating adhesive layer to cover the peripheral edge of the first metal plate; Equipped with a covering tsuba,
A second metal plate is provided on the surface of the second recess of the first metal plate exposed at the bottom surface of each recess through an adhesive layer so as to protrude from the second recess. Semiconductor chip carrier.
(2)前記第2の金属板は断面が台形を有し、両側に勾
配が相反する傾斜辺を有する台形の傾斜辺が前記鍔の内
周端に当接することを特徴とする請求項1記載の半導体
チップキャリア。
(2) The second metal plate has a trapezoidal cross section, and the sloped sides of the trapezoid have sloped sides with opposite slopes on both sides, and the sloped sides of the trapezoid abut against the inner peripheral end of the collar. semiconductor chip carrier.
JP1198833A 1989-07-31 1989-07-31 Semiconductor chip carrier Pending JPH0362956A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1198833A JPH0362956A (en) 1989-07-31 1989-07-31 Semiconductor chip carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1198833A JPH0362956A (en) 1989-07-31 1989-07-31 Semiconductor chip carrier

Publications (1)

Publication Number Publication Date
JPH0362956A true JPH0362956A (en) 1991-03-19

Family

ID=16397677

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1198833A Pending JPH0362956A (en) 1989-07-31 1989-07-31 Semiconductor chip carrier

Country Status (1)

Country Link
JP (1) JPH0362956A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5942796A (en) * 1997-11-17 1999-08-24 Advanced Packaging Concepts, Inc. Package structure for high-power surface-mounted electronic devices
JP2011258878A (en) * 2010-06-11 2011-12-22 Otics Corp Element mounting structure
JP2017069253A (en) * 2015-09-28 2017-04-06 ニチコン株式会社 Semiconductor Power Module
JP2017069547A (en) * 2015-08-31 2017-04-06 ジョンソン エレクトリック ソシエテ アノニム Thermally efficient electrical assembly

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5942796A (en) * 1997-11-17 1999-08-24 Advanced Packaging Concepts, Inc. Package structure for high-power surface-mounted electronic devices
JP2011258878A (en) * 2010-06-11 2011-12-22 Otics Corp Element mounting structure
JP2017069547A (en) * 2015-08-31 2017-04-06 ジョンソン エレクトリック ソシエテ アノニム Thermally efficient electrical assembly
JP2017069253A (en) * 2015-09-28 2017-04-06 ニチコン株式会社 Semiconductor Power Module

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