JPH0362246A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0362246A JPH0362246A JP1198215A JP19821589A JPH0362246A JP H0362246 A JPH0362246 A JP H0362246A JP 1198215 A JP1198215 A JP 1198215A JP 19821589 A JP19821589 A JP 19821589A JP H0362246 A JPH0362246 A JP H0362246A
- Authority
- JP
- Japan
- Prior art keywords
- ram
- output
- outputs
- semiconductor integrated
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000001514 detection method Methods 0.000 claims description 15
- 238000012360 testing method Methods 0.000 abstract description 7
- 238000012544 monitoring process Methods 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000012856 packing Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
Landscapes
- Dram (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Semiconductor Integrated Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路に利用され、特に、ＲＡＭ （
ランダムアクセスメモリ〉ブロックと論理回路とを有す
る半導体集積回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention is applied to semiconductor integrated circuits, and in particular, to RAM (
The present invention relates to a semiconductor integrated circuit having a random access memory block and a logic circuit.
本発明は、論理、回路部と、複数のＲＡＭブロックとを
含む半導体集積回路において、
少なくとも二つの前記ＲＡＭブロックの出力を入力し各
ＲＡＭブロックの出力が一致しているか否かを検出出力
する一致検出回路と、この一致検出回路の出力を外部に
取り出す端子とを設けることにより、
前記ＲＡＭブロックの試験専用ピン数を減少させたもの
である。The present invention provides a semiconductor integrated circuit including a logic circuit, a circuit section, and a plurality of RAM blocks. By providing a detection circuit and a terminal for taking out the output of the coincidence detection circuit to the outside, the number of test-dedicated pins of the RAM block is reduced.
従来、この種の半導体集積回路はＲＡＭブロック単体を
試験するため、前記ＲＡＭブロック自身に直接アクセス
できるように前記ＲＡＭブロックの入出力本数以上の試
験専用ピンを必要としていた。Conventionally, in order to test a single RAM block, this type of semiconductor integrated circuit has required a number of test-dedicated pins greater than the number of input/output pins of the RAM block so that the RAM block itself can be directly accessed.
前述した従来の半導体集積回路は、ＲＡＭブロックの入
出力ピン数に応じて、多数の試験専用ピンを設定しなけ
ればならないので、搭載パフケージが多ピン化し、実装
面積が増大し、コストに多大なる影響を与える欠点があ
った。In the conventional semiconductor integrated circuit described above, it is necessary to set a large number of dedicated test pins according to the number of input/output pins of the RAM block, which increases the number of pins in the mounting puff cage, increases the mounting area, and increases costs. There were some drawbacks that affected me.
本発明の目的は、前記の欠点を除去することにより、試
験専用ピン数を減らし、実装面積の増大を抑えコストを
低減できる半導体集積回路を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit which can reduce the number of test-dedicated pins, suppress an increase in mounting area, and reduce costs by eliminating the above-mentioned drawbacks.
本発明は、論理回路部と、複数のＲＡＭブロックとを含
む半導体集積回路において、少なくとも二つの前記ＲＡ
Ｍブロックの出力を入力し各ＲＡＭブロックの出力が一
致しているか否かを検出出力する一致検出回路と、この
一致検出回路からの出力を外部に取り出す端子とを設け
たことを特徴とする。The present invention provides a semiconductor integrated circuit including a logic circuit section and a plurality of RAM blocks, in which at least two of the RA
The present invention is characterized in that it is provided with a coincidence detection circuit which inputs the outputs of the M blocks and detects and outputs whether the outputs of each RAM block match, and a terminal which takes out the output from this coincidence detection circuit to the outside.
各ＲＡＭブロックに同一試験データを入力し、その出力
データについて一致検出回路で一致しているか否かを検
出する。すなわち、一致すれば各ＲＡＭブロックは正常
動作であり、不一致であればいずれかのＲＡＭブロック
が不正常動作であると判定できる。The same test data is input to each RAM block, and a match detection circuit detects whether or not the output data match. That is, if they match, it can be determined that each RAM block is operating normally; if they do not match, it can be determined that one of the RAM blocks is operating abnormally.
従って、試験専用ピンは１本でよいことになり、大幅に
試験専用ピンを削減することが可能となる。Therefore, only one test-dedicated pin is required, making it possible to significantly reduce the number of test-dedicated pins.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例の要部を示すブロック構成図
である。FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention.
本実施例の半導体集積回路１は、論理回路部２と、二つ
のＲＡＭ （Ｉ）３とＲＡＭ （ＩＩ）４とを含み、さ
らに本発明の特徴とするところの、ＲＡＭ（１）３およ
びＲＡＭ （ＩＩ）４の出力を入力し、ＲＡＭ （Ｉ）
３の出力とＲＡＭ （ｎ）４の出力とが一致しているか
否かを検出出力する一致検出回路５と、この一致検出回
路５からの判定出力９を外部に取り出す端子としての判
定出力端子１０とを含んでいる。The semiconductor integrated circuit 1 of this embodiment includes a logic circuit section 2 and two RAM (I) 3 and RAM (II) 4. (II) Input the output of 4, RAM (I)
A coincidence detection circuit 5 detects and outputs whether the output of 3 and the output of RAM (n) 4 match, and a judgment output terminal 10 serves as a terminal for taking out the judgment output 9 from this coincidence detection circuit 5 to the outside. Contains.
そして、一致検出回路５は、ＲＡＭブロック（Ｉ）３と
ＲＡＭブロック（■）４との出力をそれぞれ人力して両
者の不一致をとる二つの排他的論理和回路（ＥＸ−ＯＲ
回路） ５ａおよび５ｂと、排他的論理和回路５ａおよ
び５ｂの出力の論理和をとる論理和回路５ｃとを含み、
ＲＡＭ （Ｉ）３およびＲＡＭ （ｎ）４には、それぞ
れＲ／Ｗ （読出し／書込み）制御人力６、アドレス入
カフおよびデータ人力８が入力されるよう接続される。The coincidence detection circuit 5 then operates two exclusive OR circuits (EX-OR circuits) that manually calculate the mismatch between the outputs of the RAM block (I) 3 and the RAM block (■) 4, respectively.
circuit) 5a and 5b, and an OR circuit 5c that ORs the outputs of the exclusive OR circuits 5a and 5b,
RAM (I) 3 and RAM (n) 4 are connected to receive R/W (read/write) control power 6, address input cuff, and data power 8, respectively.
次に、本実施例の動作について説明する。Next, the operation of this embodiment will be explained.
Ｒ／Ｗ制御人力６、アドレス人カフおよびデータ人力８
によって、ＲＡＭ （１）３およびＲＡＭ（■）４に同
一データを書き込み、ＲＡＭ （Ｉ）３およびＲＡＭ
（ＩＩ）４を同時に読み出すことによって、もし、デー
タが一致しているならば判定出力９は「Ｌ」レベル、不
一致ならびｒＨＪレベルとなり判定出力端子ｌＯに出力
される。これによってＲＡＭ （Ｉ）３およびＲＡＭ
（ＩＩ）４のどちらか、もしくは両方に故障があれば不
一致の「Ｈレベルが出力され、ｌピンだけをモニタすれ
ばＲＡＭブロックの試験が可能になる。R/W control manpower 6, address man cuff and data manpower 8
writes the same data to RAM (1) 3 and RAM (■) 4, and writes the same data to RAM (I) 3 and RAM (■) 4.
(II) By reading out 4 at the same time, if the data match, the judgment output 9 becomes the "L" level, and if they do not match, the judgment output 9 becomes the rHJ level and is output to the judgment output terminal 1O. This allows RAM (I)3 and RAM
(II) If there is a failure in either or both of 4, a mismatched "H" level is output, and it is possible to test the RAM block by monitoring only the 1 pin.
第２図は一致検出回路の他の例を示す回路図である。FIG. 2 is a circuit diagram showing another example of the coincidence detection circuit.
本例の一致検出回路１１は、二つのＲＡＭブロックの出
力をそれぞれ入力する排他的否定論理和回路（ＥＸ−Ｎ
ＯＲ回路）１１ａおよびｌｌｂと、この排他的否定論理
和回路１１ａおよびｌｌｂの出力を入力し論理積をとり
判定出力９を出力する論理積回路１１Ｃとを含んでいる
。The coincidence detection circuit 11 of this example is an exclusive NOR circuit (EX-N
(OR circuit) 11a and llb, and an AND circuit 11C which inputs the outputs of the exclusive NOR circuits 11a and llb, performs a logical product, and outputs a determination output 9.
この場合には、二つのＲＡＭブロックの出力が一致した
ときに判定出力９はｒＨＪレベルとなり、同様にＲＡＭ
ブロックの試験が可能である。In this case, when the outputs of the two RAM blocks match, the judgment output 9 becomes the rHJ level, and similarly the RAM
Block testing is possible.
以上説明したように、本発明は、複数のＲＡＭブロック
の出力同士を一致検出回路で判定できるようにすること
により、試験専用ピンの数を減らすことができ、実装面
積の増大を抑えコストを低減できる効果がある。As explained above, the present invention allows the outputs of multiple RAM blocks to be judged by a coincidence detection circuit, thereby reducing the number of test-dedicated pins, suppressing an increase in mounting area, and reducing costs. There is an effect that can be achieved.
第１図は本発明の一実施例の要部を示すブロックａ戊図
。
第２図はその一致検出回路の他の例を示す回路図。
１・・・半導体集積論理回路、２・・・論理回路部、３
・・・ＲＡＭ （Ｉ） 、４・・・ＲＡＭ （ｎ） 、
５．１１・・・−致検出回路、６・・・Ｒ／Ｗ制御入力
、７・・・アドレス入力、８・・・データ入力、９・・
・判定出力、１０・・・判定出力端子。FIG. 1 is a block diagram showing essential parts of an embodiment of the present invention. FIG. 2 is a circuit diagram showing another example of the coincidence detection circuit. 1... Semiconductor integrated logic circuit, 2... Logic circuit section, 3
...RAM (I), 4...RAM (n),
5.11... - match detection circuit, 6... R/W control input, 7... address input, 8... data input, 9...
- Judgment output, 10... Judgment output terminal.
Claims (1)
体集積回路において、 少なくとも二つの前記ＲＡＭブロックの出力を入力し各
ＲＡＭブロックの出力が一致しているか否かを検出出力
する一致検出回路と、 この一致検出回路からの出力を外部に取り出す端子と を設けたことを特徴とする半導体集積回路。[Claims] 1. In a semiconductor integrated circuit including a logic circuit section and a plurality of RAM blocks, the outputs of at least two RAM blocks are input and it is detected whether the outputs of each RAM block match. A semiconductor integrated circuit comprising: a coincidence detection circuit that outputs an output; and a terminal that takes out the output from the coincidence detection circuit to the outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1198215A JPH0362246A (en) | 1989-07-31 | 1989-07-31 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1198215A JPH0362246A (en) | 1989-07-31 | 1989-07-31 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0362246A true JPH0362246A (en) | 1991-03-18 |
Family
ID=16387408
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1198215A Pending JPH0362246A (en) | 1989-07-31 | 1989-07-31 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0362246A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6515915B2 (en) | 1998-02-23 | 2003-02-04 | Micron Technology, Inc. | Circuits and methods for outputting multi-level data through a single input/output pin |
-
1989
- 1989-07-31 JP JP1198215A patent/JPH0362246A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6515915B2 (en) | 1998-02-23 | 2003-02-04 | Micron Technology, Inc. | Circuits and methods for outputting multi-level data through a single input/output pin |
| US6519190B2 (en) | 1998-02-23 | 2003-02-11 | Micron Technology, Inc. | Circuits and methods for inputting multi-level data through a single input/output pin |
| US6525958B2 (en) * | 1998-02-23 | 2003-02-25 | Micron Technology, Inc. | Circuits and methods for compressing multi-level data through a single input/output pin |
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