JPH0361211B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a simulation method for an electronic computer, and particularly to a vector instruction simulation method in a vector processor whose processing is divided into a scalar unit and a vector unit. .

[Conventional technology and problems]

A vector processor consists of a scalar unit that processes so-called scalar instructions and a vector unit that processes vector instructions that process a large amount of data at once, and a general-purpose computer is generally used for the scalar unit. For this reason, when a vector processor is being developed, a scalar unit may exist, but a vector unit may not yet exist.

Even in such a situation, program development for vector processors and hardware development are generally progressing in parallel, and early debugging of the programs is desired. In addition, it may be necessary to confirm the design of the vector processor at an early stage. For this reason, conventionally these things have been done using a software simulator.

FIG. 3 shows an example of a conventional simulation method.

In conventional simulation methods, when an instruction to be simulated is detected, a system interrupt such as a supervisor call instruction (SVC instruction) or monitor call instruction (MC instruction) is used, the instruction to be simulated is determined from the interrupt code, and that instruction is executed. was conducting a simulation.
That is, for example, as shown in Figure 3, the SVC code is registered in advance, and the instructions to be simulated are written to the SVC using an assembler macro, etc.
Convert to instructions. Then, prepare for program execution such as setting initial data, and if an SVC interrupt occurs during program execution, check the SVC interrupt code in the simulator and execute the simulation corresponding to each registered interrupt code. . Then, through the system control unit
Return to SVC interrupt point.

In this conventional method, the simulation becomes system interrupt processing, and the processing routine using a group of scalar instructions that performs the simulation is
There is a problem in that it is treated in the same way as an operating system and requires complicated procedures to communicate with the system. In addition, when using system interrupts, there is a drawback that all interrupt codes for SVC interrupts and MC interrupts must be registered for each instruction, and the instructions of the program to be simulated must be converted into SVC instructions etc. in advance. There is a drawback.

[Means for solving problems]

The present invention aims to solve the above problems and makes it possible to shorten simulation time and simplify communication procedures with complex systems by using program exception interrupts instead of using system interrupts such as SVC instructions. Then, scalar instructions are executed on the scalar unit, and vector instructions are executed by transferring control to the software simulator, which is expanded to a scalar instruction that is executed on the scalar unit, due to a program exception in the scalar unit. There is. That is, the vector instruction simulation method of the present invention is a method for simulating instructions executed in a vector processor consisting of a scalar unit and a vector unit, and identifies a vector instruction in the simulation mode and interrupts a program exception. and a software simulator that simulates the processing of each vector instruction by a series of scalar instructions, and executes a program consisting of vector instructions and scalar instructions in a simulate mode. When doing so, the scalar instructions are executed as they are on the above scalar unit, and the control for vector instructions is transferred to the above software simulator which is treated as a program exception interrupt. It is characterized in that the type of vector instruction that has interrupted is determined, and the above-mentioned scalar instruction group that simulates the determined vector instruction is executed. Hereinafter, embodiments will be described with reference to the drawings.

〔Example〕

FIG. 1 shows an example of a system configuration in which the present invention is implemented.
FIG. 2 shows an embodiment of the simulation method according to the invention.

The vector processor 1 consists of a scalar unit 2 and a vector unit 3. However, in the case of the present invention, the vector instruction executed by the vector unit 3 is simulated by the scalar unit 2, so the vector unit 3 does not necessarily have to exist. Therefore, an ordinary general-purpose computer can also be used as the vector processor 1.

Control register 4 is one of many control registers held by scalar unit 2, and has a valid flag for vector unit 3. By turning off this valid flag, vector instructions can be prohibited and program exception interrupts can be generated for vector instructions. The instruction decoder 5 decodes instructions fetched from the memory 8 and executed. When the instruction code is a scalar instruction, the instruction processing unit 6 executes the instruction. When the instruction code is a vector instruction, the program exception interrupt generating section 7 generates a program exception interrupt.

Memory 8 is a storage device that stores instructions and data processed by vector processor 1. The simulation target program 9 consists of an instruction sequence including vector instructions, but in the case of the present invention, the object may be the same as in the case where no simulation is performed, and the vector instructions are pre-programmed.
There is no need to change it to SVC instruction etc.

The simulate mode setting unit 10 executes processing to set the control register 4 to a state in which vector instructions are prohibited and to set the vector instruction simulate mode. Also, a new PSW is set so that the control transfer destination when a program exception interrupt occurs is the start address of the control section 12 of the software simulator 11.

The software simulator 11 includes a control section 12 that controls simulation, and vector instruction simulation processing sections 15a, 15b, . . . that simulate vector instructions using a group of scalar instructions for each vector instruction. The control unit 12 also includes an interrupt address extraction unit 13 that extracts the address where a program exception interrupt has occurred, and a vector instruction pseudo processing unit 15a, which determines the type of instruction stored at that address, and depending on the instruction type, 15b... is provided.

Next, an example of the simulation method according to the present invention will be explained with reference to FIG.

When simulating vector instructions, first a program exception interrupt is registered in the system. Then, the control register 4 is set to a state in which vector instructions are prohibited. Note that this processing is not necessary in the case of a system in which program exception interrupts are caused from the beginning by execution of vector instructions.

Thereafter, when the simulation target program 9 is executed, the scalar instructions are sequentially executed by the instruction processing section of the scalar unit 2. When a vector instruction appears in a program, the instruction decoder 5
The program exception interrupt generating section 7 is activated by the program exception interrupt generating section 7, and a program exception interrupt is generated. As a result, control is transferred to the control unit 12 of the software simulator 11, and the control unit 12 first determines whether it is a registered program exception interrupt. Regarding unregistered program exception interrupts,
Processed as an abnormal interrupt and software simulator 1
1 is canceled, and the execution of the simulation target program 9 is ended.

If it is a registered program exception interrupt, the interrupt address is investigated according to the old PSW, and the interrupt vector instruction code is determined from the interrupt address and interrupt code. The instruction operands are also extracted, and the vector instruction pseudo processing units 15a, 15b, . . . corresponding to the instruction code are extracted.
, and simulates data processing using vector instructions using a series of scalar instructions. Thereafter, in the control unit 12, various registers are restored as necessary, and control is transferred to the instruction following the instruction that caused the program exception interrupt by a load PSW instruction or the like. Thereafter, the instructions of the simulation target program 9 are processed in the same way, and when the program is completed, the simulation mode is canceled. By doing so, all instructions are executed on the scalar unit 2.

〔Effect of the invention〕

As described above, according to the present invention, there is no need to register SVC codes compatible with vector instructions or convert instructions to be simulated, and the software interface with an operating system or the like is also simplified. Therefore, even if the vector unit does not exist or becomes a failure, it is possible to efficiently execute a vector processor program using only the scalar unit. For example, when debugging a vector processor program for early development, or for testing when a vector unit fails, the processing results of vector instruction execution by the actual vector unit are compared with the processing results from simulation. The simulation method according to the present invention can be used in a wide range of applications, such as when making a diagnosis.

[Brief explanation of drawings]

FIG. 1 shows an example of a system configuration in which the present invention is implemented.
FIG. 2 shows an embodiment of the simulation method according to the present invention, and FIG. 3 shows a conventional simulation method. In the figure, 1 is a vector processor, 2 is a scalar unit, 4 is a control register, 5 is an instruction decoder, and 6 is a scalar unit.
1 is an instruction processing unit, 8 is a memory, 9 is a simulation target program, 10 is a simulation mode setting unit, 11 is a software simulator, 12 is a control unit, 13 is an interrupt address extraction unit, 14 is an instruction type determination unit, 15a, 15b, and 15c represent vector instruction pseudo processing units.

Claims (1)

[Claims] 1 A method for simulating instructions executed in a vector processor consisting of a scalar unit and a vector unit, which includes a means for identifying a vector instruction and generating a program exception interrupt in a simulation mode, and a means for generating a program exception interrupt for each vector instruction. A software simulator is provided that simulates processing using a series of scalar instructions, and when a program consisting of vector instructions and scalar instructions is executed in the simulate mode, the scalar instructions are directly transferred to the above scalar unit. For vector instructions, control is transferred to the software simulator as a program exception interrupt, and the software simulator determines the type of vector instruction that has interrupted based on the interrupt address. A vector instruction simulation method characterized in that the above-mentioned scalar instruction group that simulates the determined vector instruction is executed.