JPH0359753A - Bidirectional bus buffer - Google Patents

Abstract

PURPOSE:To reduce the number of buffer ICs by dividing a n-bit buffer into two groups or more, independently forming bus control terminals corresponding to respective groups and applying different bus control to respective groups. CONSTITUTION:The 8-bit bus buffer is divided into two groups; X and Y groups. The X group is controlled by two control signals DIRX (direction control of X), the inverse of GX (enable control of X) and the Y group is controlled by two control signals DIRY (direction control of Y), the inverse of GY (enable control of Y). A gate 11 controls the A B of the X group and a gate 12 controls the B A of the X group. Similarly, a gate 13 controls the A B of the Y group and a gate 14 controls the B A of the Y group. Thus, the number of buffer ICs can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data bus buffer in an information processing device such as a personal computer.

[Prior art] Conventionally, there are 7 bidirectional buffers for data buses.
4LS245 is famous. This is shown in FIG. Third
Figure (α) is the circuit diagram of 74LS245, and (b) is the circuit diagram of 74LS245.
FIG. 4 is a symbol diagram of 4LS245. (C) is 74I, 5
This is a summary of the functions of H.245. The 74LS245 is an 8-bit bidirectional buffer with two control signal handles R and G. G is a buffer enable signal; when G=L (low level is written as L), it is enabled; when G:H (high level is written as H), it is disabled. When G=H is disabled, both the input side (A1 to A8) and the B side (B1 to B8) are not driven and are in a high impedance state. DIR is a direction signal that controls the direction of the buffer when enabled with G=L. When D/R=H, the signal on the A side drives the B side. That is, the direction of the buffer is A9B. When DIR=L, the signal on the B side drives the A side. That is, the direction of the buffer is B″:>A
becomes. In any case, in the 74LS245, the eight signals (A1 to A8 and B1 to B8) always operate in the same way.

[Problems to be Solved by the Invention] Normally, the 8-bit data bus is driven using the conventional bidirectional bus buffer 74LS245 (101 in FIG. 5-(h)), but this may be inconvenient in some cases. This is the case as shown in FIG. 5, in which one address is divided into two addresses and used by 10 devices.

The I10 device (in uses bits 7 to 4 of the I10 address area J and the I10 address area, and
B) uses bit 380 of the 10th address area in the 100th address area. If a conventional 74LS245 is used, the bus buffer in such a case will be as shown in FIG. 4 (α) and FIG. 4 Ch). 3 is the engineering 10 device (a), and 5
2 is a part other than the bus buffer of the equipment (A), and XD7 to XDO are internal data buses within the equipment. SD7 to SDO are system data buses, and the
Figure (b) shows a common path for information processing devices including an I/O device (b). Signals -asy and -0SL in 2 are chip select signals obtained by decoding address areas J and L, respectively. Connect the data buses XD7 to XDO of the engineering 10 equipment (a) to the system data buses SD7 to 5DO.
(> In this case, two 74LS245 (2
101) are required. For bits 7-4, the bus buffer is enabled when either 103J or -aSL is active, and for bits 3-0, the bus buffer is enabled when 108J is active. Similarly, two 74
LS245 is required and each bus buffer is controlled by a separate signal.

As shown in the above example, when one device/τ address is divided and used by two devices, two bus buffers are required for the device if the conventional 74LS245 is used. However, this was extremely disadvantageous in terms of cost and board space. The purpose of the present invention is to improve this point.

[Means for solving the problem] The means for solving the problem is to provide a new bus buffer as shown below. It is a bidirectional bus buffer that divides the bus buffer into two or more groups and has separate control inputs for each group.

[Example] The present invention will be explained in detail based on the following example. FIG. 1(α) is a bidirectional bus buffer according to the present invention, and FIG. 1(b) is its symbol diagram.

The 8-bit bus buffer has two groups:
It can be divided into The X group is DXRX (direct
tion Control of X) and GX(e
control of X), and the X group is controlled by two control signals:
(direction control of Y
) and G Y (enable control of
Y) is controlled by two control signals. Gate 11 controls A→B of X group, and gate 12
controls B→A of group X. Similarly gate 13
．． controls the A→B of the X group, and the gate 14 controls the B→A of the X group. DIRX, GX, DIR
X.

The meaning of Ding T is summarized in Figure 1(d). S
l, SO are signals for deciding how to divide into groups, and when (31,5o)=(0,0), A1 to A7. E
1~B707 bits are included in the X group, A8. B8
1 bit is included in the X group. (Sl, 30)
= (0, 1), the X group has 6 bits and the X group has 2 bits. The relationship between (si, so) and grouping is summarized in FIG. 1 CC>. Figure 1 (
α), (AI tBl )(A2.B2)(A
3. B3) The 4 bits of (A4.B4) are always (31, S
o) is included in the X group, and 1 bit of (A8.B8) is always included in the X group. (A5.B
5) (A6.B6).

The 3 bits of (A7.B7) are 31. X depending on the value of So
Included in the group or included in the X group.

This is selected by the selector 10 as the control signal of the X group and
This is achieved by switching group control signals. The relationship between si, so and the grouping of each bit is also summarized in FIG. 1 (CC). The above is an explanation of the bidirectional bus buffer according to the present invention. Fig. 2 (a) shows what happens when this bidirectional bus buffer is used in the I10 device shown in Figs. 4 (α) and (b). , (5) in Figure 2 (α
) 2.3 and 4.5 in (b) are the same as those in Fig. 4 (a) and (b). 1 is a bidirectional bus buffer according to the present invention, and two 74Ls in FIG. 4(α)j(h)
It is used in place of S245. Looking at the bidirectional bus buffer 1 of the device (a) in Fig. 4 (α), (Sl, 5o) = (i, 1'), as can be seen from Fig. 1 (c). , X group and X group are divided into 4 bits each. X Group (X
Figure 4 (α) is attached to the control terminals RX and D1 of D7-4).
The same signal as that in the DIR and MA of the 74LS245 that buffers XD7 to 4 of the I10 device (A) is input to the control terminals of the X group (XD3 to 0) RY and GM. 74LS is buffering XD3 to 0 of the processing/copying device (a) in Figure 4 (α).
24! M') The same signal as that in DIR and DIR is input. Therefore, regarding the bus buffer of the I10 device (a), the functions shown in FIGS. 2 and 4 are exactly the same. The same can be said about the bus buffer of the device (b) in FIG. 4(b).

[Effects of the invention] Examples using the conventional bidirectional bus buffer shown in FIGS. 4(α) and (b) and examples using the bidirectional bus buffer 1 according to the present invention shown in FIGS. 2(α) and (b) As can be seen from the comparison, the use of the bidirectional bus buffer of the present invention allows the number of buffer circuits (integrated circuits) to be reduced compared to the conventional one.
Costs can be reduced and circuit board space can be saved. This is effective in reducing the price and size of the information processing device. Furthermore, since the bidirectional bus buffer according to the present invention can be grouped freely, the same process can be used in a wide range of applications.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a bidirectional bus buffer according to the present invention. Figure 1 (α) is a circuit diagram, Figure 1 (b) is a symbol diagram, Figure 1 (C) is an explanatory diagram of 51SO signals and grouping, and Figure 1 (d) is an explanatory diagram of control signals. It is. FIG. 2(α) and FIG. 2(b) are diagrams showing an embodiment using a bidirectional bus buffer according to the present invention. Figure 3 shows a conventional bidirectional bus buffer (74LS245).
FIG. 3(α) is a circuit diagram, FIG. 6(b) is a symbol diagram, and FIG. 3(C) is a functional explanatory diagram. Figure 4 (α), (b)
is a diagram showing the embodiment of FIG. 3. FIG. 5 is an explanatory diagram of the example of FIGS. 2 and 4. 1. Bidirectional bus buffer 2 according to the present invention.・・・・・・Parts other than the bus buffer of the equipment 10 (A) 3 ・・・・・・Engine 10 equipment (A) 4 ・・・・・・
... Parts other than the bus buffer of the device (b) 10......Eng/τ device (b) 0...
...Selector<1,12,13,14...Gate 01
・・・・・・Conventional bidirectional bus buffer (7°4LS2
45)

Claims (2)

[Claims] (1) In an n-bit bidirectional bus buffer housed in one integrated circuit package, the n-bit buffer is divided into two or more groups, each having a separate bus control terminal for each group, and each A bidirectional bus buffer characterized by being able to perform different bus controls for groups of. (2) The bidirectional bus buffer according to claim 1, further comprising means for instructing how to divide the n-bit buffer into two or more groups, and the number of bits in each group can be made variable.