JPH0352218B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge detection device for a CCD, and particularly to a new configuration of a charge detection device that can be effectively constructed on the same semiconductor substrate as a two-phase operation buried channel CCD.

Generally, CCD charge detection requires fast response, high sensitivity, low power consumption, etc., as well as simplicity of external circuitry and ease of adjustment. In particular, since a buried channel CCD performs a faster transfer operation than a surface channel CCD, the detection circuit integrated therewith is required to have high-speed response to meet the above-mentioned high-speed transfer performance.

The signal charge detection circuit connected to the output terminal of the CCD usually uses a source follower circuit composed of a pair of insulated gate field effect transistors (hereinafter abbreviated as MOST). Currently, the upper limit of the operating frequency of embedded channel CCDs with a transfer electrode length of about 10 μm has reached several tens of MHz.
Unless the response frequency of the detection circuit that detects the charge of the CCD corresponds to the operating frequency of the CCD, the CCD cannot exhibit high-speed operation.
This will be briefly discussed below.

As shown in Figure 1, the load on the floating diffusion layer D, which is the output terminal of the CCD, is the capacitance of the diffusion layer D and the active charge detection source follower circuit connected to it.
It is a capacitive load like the gate capacitance of MOSTQ _A. Therefore, the transferred charge Q _T which is the output of the CCD
In order to detect with high sensitivity in the form of voltage V, V=
Due to the relationship Q _T /C, the gate capacitance of the active MOSTQ _A must be small, so the active
It is not possible to increase the dimensions of MOSTQ _A.

On the other hand, the output end of the source follower circuit is
It is determined by the sum of the capacitance of the diffusion layer connecting the source of MOSTQ _A and the drain of the load MOSTQ _L (hereinafter referred to as the DS point) itself, and the input capacitance of the sample-hold MOST (not shown) connected to the DS point.
It is also capacitive. Therefore, from the perspective of a single-stage source follower circuit, its load can be regarded as the capacitance C _L as shown in FIG.

On the other hand, as mentioned above, it is not possible to increase the dimensions of active MOSTQ _A , but since load MOSTQ _L is not connected to the input terminal of the source follower circuit, it is possible to increase the dimensions of this load MOSTQ _L. If the dimensions are increased, the conductance G _L of the load MOSTQ _L will be increased, the charging/discharging time constant of the capacitive load C _L will be shortened, and the response speed of the source follower circuit will therefore be increased. Therefore, increasing the size of the load MOSTQ _L allows the source follower circuit to operate at high speed.

Figure 2 shows the active MOST current I _D and the load MOST
The current I _L at DS point is plotted on the vertical axis, and the voltage at point DS V _DS is plotted on the horizontal axis.
FIG. 3 is a diagram showing movement of the operating point of FIG.

As is well known, the saturation current I of a single MOST is
It is determined by (V _G − V _T ). However, V _G is the input gate voltage and V _T is the threshold voltage, but in the active MOST of the source follower circuit, the difference between the voltages V _GG and V _DS at the gate terminal GG and DS point (V _GG − V _DS ) corresponds to V _G above. Therefore, the saturation current I of the active MOST is (V _GG - V _DS - V _T ) ²
However, if the active MOST is of the surface channel type and therefore V _T 0, the above saturation current I can be effectively expressed as (V _GG - V _DS ) ² , and the active
The saturation current I of the MOST is drawn by the square characteristic of V _GG -V _DS , for example, as shown by the curve E in FIG.

By the way, the gate terminal GL of the load MOST is normally connected to the source terminal SS, which should be grounded. To determine the conductance of this load MOSTQ _L ,
If the saturation current flowing through MOSTQ _L is a small value as shown by I _L1 in Figure 1, then the current
The operating point is, for example, point A on curve H so that I _L1 matches the current _ID flowing through the active MOST. By the way, a voltage of V _DD =12V is applied to the gate terminal V _GG of the active MOST via the reset transistor Q _R . Therefore, if the transferred charge Q _T enters the floating diffusion layer D from the CCD and generates a voltage of 2V, the gate terminal voltage V _GG of the active MOSTQ _A will change from the above 12V to 10V. It exhibits a drop of 2V to . If this voltage drop occurs, the current I _D of active MOSTQ _A will decrease and the operating point will be B.
Therefore, the current I L of the load MOSTQ _L is smaller than the current I _L , that is, I _D < I _L.

This state of I _D <I _L means that the charge in the load capacitance C _L flows out through the load MOSTQ _L , that is, it is discharged. However, since the voltage V _DS at point DS, that is, the voltage across the load capacitance C _L , is constant, the decrease in the current I _D described above is first expressed as a movement from point A to point B in Figure 1, but the operation The point further follows the square characteristic curve of the active MOST until it reaches a point C, where it finishes discharging, and at this point C the active MOSTQ _A
The currents I _D and I _L1 with the load MOSTQ _L are again balanced.

Conversely, when the gate voltage V _GG of active MOSTQ _A starts from 10V
If increased to 12V, the active MOSTQ _A current I _D will be
After increasing while V _DS is constant and reaching point D on curve E, it returns to point A along square characteristic curve E and reaches equilibrium.

In this case, the operating speed of the source follower circuit takes a complex form expressed by an integral equation, so it will be omitted for the sake of understanding, but diagrammatically, the line between B and C can be approximately regarded as a straight line. Or D~A
The slope between them corresponds to the speed of change of the operating point.

As can be seen from this figure, the slope between B and C or between D and A is not very steep, and if the current flowing through the load MOST is as small as I _L1 , the response of the source follower circuit is not fast. That's what I understand.

Therefore, now, in order to speed up the source follower circuit, the ratio W/L of the gate width W to the gate length L of the load MOSTQ _L is increased, and the current of the load MOSTQ _L , which was previously I _L1 , is reduced to I Increase it to a value of _L2 .

In this way, the movement of the operating point due to the change in the input voltage V _GG of the source follower circuit as described above will be as shown in a to b to c to d to a in FIG. 2, and especially b to c and d. It is understood that the source follower circuit has high-speed response from the fact that the slope of ~a is steep.

However, if we increase the dimensions of the load MOSTQ _L and increase the current flowing through the MOSTQ _L ,
As mentioned above, the response speed increases, but the active
MOST gate terminal voltage V _GG is 12V as mentioned above.
The voltage at the V DS point decreases, while the voltage at the V _DS point decreases. That is, there is a drawback that the amount of voltage shift in the source follower circuit increases. Although this increase in the amount of voltage shift may not be a big deal in a single-stage source follower, when the source follower is connected in two stages, the effect cannot be ignored and becomes a cause of distortion in the output signal.

The present invention was made in view of these drawbacks.
By adjusting the threshold voltages of the active MOST and load MOST mentioned above, the amount of voltage shift mentioned above can be prevented from increasing, and the buried channel can be
The present invention aims to provide a novel charge detection device that can be formed on the same semiconductor substrate as a CCD using the same manufacturing process, and will be described in detail below with reference to FIG.

FIGS. 3a, 3b, and 3c show the manufacturing process of the charge detection device according to the present invention, and these steps will be described in order below.

First, in a predetermined region of a P-type semiconductor substrate 1, for example, a first active region A in which both a buried channel CCD and a reset MOST whose floating diffusion layer serving as its output terminal is shared with the source diffusion layer are formed; An insulating layer 2 for defining a second active region B in which both the active MOSTQ _A and the load MOSTQ _L constituting the source follower circuit are to be formed is formed by a so-called LOCOS method.

After that, for example, the phosphorus (P) ion is
The substrate 1 was implanted on the above surface as shown by arrow A with a dose of 1.2×10 ¹² cm ^-2 and an energy of 90Kev.
A layer 4 of opposite conductivity type, that is, n-type, is formed as shown in FIG. 3a.

Next, after forming an insulating film 5 with a thickness of, for example, 1200 Å on the surface of the substrate 1 as shown in FIG. 3b,
A polysilicon layer is deposited on the upper surface by CVD or the like and patterned to form a first layer polysilicon gate electrode shown as 6 in the figure. Next, using the polysilicon gate electrode 6 as a mask, boron (B) ions are implanted at a dose of, for example, 8×10 ¹¹ cm ^-2 and an energy of 90 Kev as shown by the arrow RO, thereby removing the previously formed n-type. A part of the layer (buried layer) is compensated and in the active area A the CCD
charge guide area 7 in the
A semiconductor region 7' is formed directly under the gate of the MOST, and in the active region B there are various active and load regions.
A semiconductor region 7'' is formed directly under each gate of the MOST.Semiconductor regions 7',
7'' are the same as the guide regions 7 regularly arranged in the buried layer in the CCD and are of n ^- type.

Next, as shown in FIG. 3C, the upper surface of the polysilicon gate electrode 6 previously formed is oxidized to form an insulating film 8 for surface insulation, and a second layer polysilicon gate electrode 9 is formed. Afterwards, by self-aligned diffusion method, it becomes the source and drain of the reset MOST in the active region A.
In active region B, active MOST and load MOST
Phosphorus (P) is diffused into the substrate 1 so as to form an n ⁺ diffusion layer 10 that will serve as the source and drain.

Thereafter, an insulating film 11 is formed by oxidizing and insulating the upper surface of the second layer polysilicon gate electrode and performing passivation. A contact hole is made for the electrode, and aluminum (Al) is deposited and patterned to complete the wiring. In this way, the n-layer formed by implanting P in the process of FIG. B in the process of figure b
The P layer formed by implantation is only 1 μm,
Here, there is a buried channel CCD having a semiconductor layer 7 as a charge guiding region and a semiconductor layer as a charge storage region in the active region A, and a reset CCD having a semiconductor layer 7' identical to the charge guiding region directly under the gate. At the same time as the MOST is completed, an active and load MOST is formed in the active region B, which also has a semiconductor layer 7'', which is the same as the charge guiding region, directly under the gate.

Here MOST and reset for active and load
The region immediately below the gate of the MOST is compensated as a result of the implantation of both P and B impurities and becomes n ^- type, and in particular, the value of the threshold voltage V _th of the active MOST is as follows.
This results in a negative value of about 5V.

In this way, if we form the same impurity doped layer as the charge guiding region of the CCD section directly under the gate of the active MOSTQ _A and the same name as the load MOSTQ _L , the threshold voltage of both the active and load MOSTs can be reduced. As mentioned above, becomes about -5V, and as a result, the above-mentioned (V _GG - V _DS ) ² curve becomes curve G shown in Fig. 2 in the steady state, and becomes curve H in the transient state, resulting in the above voltage shift. The amount does not have to be large. Moreover, as can be seen from the movement range e-f-g-h-e of the operating point between both curves G and H, the slopes between f and g and between h and e are steep. It can be seen that the response speed is high.

According to the charge detection device according to the present invention described above, not only the embedded channel CCD section and the charge detection section can be manufactured in the same process, but also the charge detection device for the load forming the charge detection circuit of the source follower configuration integrated with the CCD can be used. In addition, the threshold voltage of both MOSTs for active use can be set to, for example, about -5V, and therefore, for the reasons mentioned above, the response speed of the source follower circuit, which is the detection circuit, can be increased without increasing the amount of voltage shift. As a result, great practical effects can be expected.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a source follower configuration detection circuit normally used for CCD charge detection.
FIG. 2 is a diagram showing the operating points of the active MOST and the load MOST constituting the detection circuit of the source follower. Furthermore, FIGS. 3a, b, and c show channel type CCDs in which the charge detection device according to the present invention is embedded.
This figure shows a process diagram for manufacturing the product all at once by integrating it with the product and using the same process. 1: Semiconductor substrate, 2: Insulating layer for defining active region, 5: Insulating film covering the substrate surface, 6, 9: Polysilicon gate electrode, 7: Charge guiding region, 8, 1
1: Insulating film on polysilicon gate surface, A, B:
Active region, Q _R : MOST for reset, Q _A : Active MOST forming the source follower circuit, Q _L : Load MOST forming the source follower circuit, _ID : Active
Drain current of MOST, I _L : Drain current of load MOST, D: Floating diffusion layer of CCD, C _L : Capacitive load, I _L1 : Low current value of load MOST, I _L2 : Load
High current value of MOST.

Claims (1)

[Claims] 1. Charges in a source follower configuration connected to the output electrode of a buried channel CCD having charge guiding regions 7 regularly formed in a buried layer 4 and formed on the same semiconductor substrate as the CCD. In a charge detection device having a detection circuit, a layer on the semiconductor substrate is placed directly under each gate electrode 9 of an active insulated gate field effect transistor Q _A and a load insulated gate field effect transistor Q _L included in the charge detection circuit. A charge detection device characterized in that it has an impurity doped layer 7'' formed simultaneously with a charge guiding region in the buried layer.