JPH0348527A - Phase synchronizing oscillator circuit - Google Patents

Abstract

PURPOSE:To obtain the phase synchronizing oscillator circuit which can be realized extending over a wide frequency range by constituting it so that an output frequency range of a desired oscillator is brought to phase synchronization in plural multiple degrees extending over an output frequency range or above of a voltage control oscilla tor. CONSTITUTION:An output frequency fVCO of a voltage control oscillator 1 is brought to RM multiplication through a multiplier 7, and mixed 2a with an oscillation frequency fOSC of a desired oscillator, for instance, a YTO 8. In this state, a part of an output of the oscillator 1 is brought to frequency division by an NM frequency divider 12, and in this case, brought to phase comparison 5b with a reference signal of 100kHz and brought to feedback to the oscillator 1. Subsequently, RM executes multiplication, for instance, within a range of 20-90. Next, a single brought to phase comparison 5a of an output of an LPF 10 and fIF of an IF frequency is brought to feedback to the oscillator 8. In this case, this circuit is constituted so that an output frequency range of the oscillator 8 is brought to phase synchronization in a multiple degree extending over an output frequency range or above of the oscillator 1. Accordingly, in a hardware constitution of an fVCO generating loop, it is possible to eliminate the need of a mixer, and a phase synchronizing oscillator which can be realized in a wide frequency range is obtained.

Description

Detailed Description of the Invention [Field of Industrial Application] This invention is concerned with high-frequency phase synchronization of an oscillator over a wide band in the high-frequency region higher than microwaves. [Prior Art] Fig. 5 is a block diagram showing a conventional phase-locked oscillator circuit.
2 is a ξ mixer, 3 is an “M” frequency divider, 5 is a phase/frequency detector (hereinafter referred to as φ detector), 6 is a loop filter, 7 is a multiplier, and 8 is a microwave band voltage control. An oscillator (hereinafter referred to as YTo), O is an adder, 10 is a low-pass filter, and 11 is an output terminal. Next, we will explain the operation. In general, oscillators using yttrium-iron-garnet (Y.I.G.) crystals are widely used as microwave band oscillators, and products with broadband properties ranging from 4 to 18 GHz, for example, have also appeared. YTO8 is such an oscillator, and in order to obtain an output signal over a wide band, phase synchronization is often performed from the viewpoint of frequency stability. In other words, first, the YTO8 is controlled by the output of the adder 9, and rough tuning is performed near the target frequency, but fine tuning using a phase locking circuit is required to match the exact frequency. It is. With this coarse tuning, the output frequency of YTO 8 "fosc" is approximately 20 to 3 times higher than the frequency from multiplier 7.
It is set to a frequency as low as 0MHz. Therefore,
The frequency from the multiplier 7 and rosc are mixed in the mixer 2a, converted to this lower frequency, and converted to an intermediate frequency (hereinafter referred to as IF).
). The actual multiplier output is
The frequency is an integer multiple of the frequency of the fundamental wave and includes countless harmonics, but only a certain portion of the frequency close to the frequency of rosc is extracted by the low-pass filter 10. This ■F is phase-compared with the frequency -fIF of a signal accurately produced by a synthesizer in a low frequency band in the φ detector 5a, and the error fraction is extracted as a voltage output. By feeding this negative feedback to the adder 9 via the loop filter 6a, the setting error due to the coarse tuning is compensated for and automatically controlled to obtain an accurate frequency. Phase synchronization using a feedback circuit is generally widely performed, and the oscillation frequency fVc of the VCOI is similar to fIF. Since both are made with high precision using a phase-locked circuit, fOSC can have an accuracy that matches these stability levels.

The relationship between these frequencies will be explained. First, r vc
o is mixed with a stable signal of 200Ml{z by mixer 2b, and its IF is divided into 1/M by M frequency divider 3. On the other hand, a similarly stable signal of 10 MHz is divided into 1/N by the N frequency divider 4 to create a signal, and this frequency and the above frequency-divided signal are compared in phase with the φ detector 5b and sent to the VCO 1. When it returns, the two input frequencies of the φ detector are controlled to match, as explained above. Therefore, fVeO when the frequency of ■co is finally stable is M −'. fvco -200-10 (MH
z) ”'(1)N.This feedback loop is called the M/N loop,
In this conventional example, the frequency range of r vco is approximately 182~
198MHz. When the fVCO signal frequency is input to the multiplier 7, harmonics are output at frequencies that are integral multiples of the fVCO signal frequency. However, as mentioned above, the desired harmonic signal is a multiplied order signal having a frequency about 20 to 30 MHz higher than the fosc, and this is the N-order signal. Therefore f03 after stabilization
, the frequency of is expressed as lower 2 by organizing the above explanation. f osc -N-f vco - f IF"200
N-10M-fly (MHz) ''(2) where f
As mentioned above, if the IF has a frequency range of 20 to 30 MHz, it is possible to set the frequency below 10 MHz, and in the M/N loop, higher frequency units are set to the M and N frequency dividers, so it is possible to set the frequency as desired. r osc corresponding to the frequency of
can be clearly determined. In an actual device, M. Since it is necessary to calculate equation (2) to set the N frequency division ratio and fIF, a microprocessor-based control method is used. [Problem to be solved by the invention] As can be seen from the relational expressions (1) and (2), the conventional phase-locked oscillation circuit is constructed from a logical idea, but it is difficult to realize it by hardware. There were some difficulties in doing so. In other words, (as seen from equation 11, fVeO is always 2
Although it is assumed that the frequency is lower than 00MHz, the VCO
If the frequency stability of I is poor, there is a risk of accidentally exceeding it. In the conventional example above, the frequency is not set above approximately 198 MHz, but if the frequency exceeds 20 MHz due to temperature changes in the circuit structure, there is a possibility that the M/N loop will phase synchronize with the opposite frequency, 202 MHz. In this case, there was a risk that the YTO frequency ros'c would become a random frequency. Also, as can be seen from formula <2>, the desired YTO frequency r
As asc increases, the multiplication order N also increases, so fVc in equation (1). The limit is approaching <200MHz. Therefore, the risk of erroneous phase synchronization with the opposite frequency increases as described above, so ros. (approximately 80 0 0 MHz in the conventional example above)
, there was a problem that the variable bandwidth could not be freely expanded (4 GHz width in the above conventional example).This invention was made to solve the above problems. The purpose of this invention is to obtain a phase-locked oscillator circuit that enables frequency sweep over a wide band by avoiding the risk of phase locking, and which can bring out the performance of a wide-band (for example, 4 to 18 GHz) oscillator. [Means to solve the problem]? The phase-locked oscillator circuit according to the invention uses a frequency obtained by multiplying the output frequency fvco of a voltage controlled oscillator by a multiplier and an output frequency f from a desired oscillator. After mixing C, the phase synchronization is performed with another signal frequency f■.
The frequency range of omc is configured to be phase-synchronized at multiple multiplication orders over the frequency range of fVC6. Further, the phase-locked oscillator circuit according to the present invention has a means for setting discrete values at equal intervals as the frequency of the fVCO, and a means for compensating the discrete values, in order to have the above-mentioned circuit configuration. The frequency fIF! means for setting a discrete frequency f'lF at equal intervals or narrower intervals than the frequency of the VCO; It is equipped with a means to [Operation] In this invention, since the above structure is adopted, f VC
It is possible to eliminate the need for a mixer in the hardware configuration of the O-operation lube, and it is possible to obtain fvco with only one type of frequency division ratio, which allows the phase including the ξ mixer in the closed circuit to be adjusted. It is possible to prevent erroneous phase synchronization with the image side frequency peculiar to the synchronization circuit, and f vc
o frequency limitation can be eliminated.

〔Example〕

An embodiment of this invention will be explained below with reference to the drawings. FIG. 1 is a block diagram showing a phase-locked oscillation circuit according to an embodiment of the present invention. In the figure, 12 is a frequency divider based on a new concept (frequency division ratio -Nd). The oscillation frequency f of YTO8 ..., compared to the conventional frequency range lower than 8000 MHz, which is higher and wider than 4000 MHz to 1800 MHz.
The circuit configuration set for z will be described. First, the oscillation frequency f wee of vcot is set in the vicinity of 200 MHz or a lower frequency range as in the conventional case. First, multiplier 7
Consider the harmonic order RH due to. ? 1A shall be created using a low frequency synthesizer as in the past, and its frequency range will be 30 to 40 MHz. Therefore, rearranging the preconditions for calculating formula (3), f vco ≦2 0 0 MHz = {4) f I
F-30 to 40 MHz...(5) r.
．． c-4 0 0 0 ~ 1 8 0 0 0 ・(
6). Therefore, the value of R8 is the minimum value RM. MIN,
or maximum value RM. ■Brim, becomes . However, INT() leaves only the integer part of the operation result and represents truncation of the decimal part. Therefore, the range of R8 is approximately 20
~90. (An approximate value is sufficient.) Next, consider the frequency range of f vco. The maximum frequency is 2
00MHz, and consider the lowest frequency.

Is this by changing the f vco frequency and multiplying by R0?
Since the frequency range of f■ is only a 10 MHz variation range according to equation (5), it is determined from the point that it is necessary to suppress the variation to 10 MHz or less. In other words, from equation (3), R4
・fvc0-f. . It is sufficient if f wee can be changed by the same amount even if R i changes so that 10f■ remains constant. R. The change in R. The smaller the RM, the better the effect. Since we only need to consider the time of MIN, the lowest frequency of f vco
o. MIN is RM. NIN (=20) ・fvc0. XXX
(=200MHz)= (Rx.x+M+ 1)
・f vcc++MIN・' f VCO. MIN'
1 9 0 MHz Therefore, the range of f VC6 is as follows after reviewing equation (4).

fvC0=190MHz~200MHz
...(7) Next, consider the tuning step (minimum frequency interval) required for f vco. This means that when the frequency of fvco is changed by the minimum unit (that is, tuning step), the frequency range of fIF is 10MH, similar to the above.
It is found from the condition that z is not exceeded, and if Δf▼co is the tuning step, Δrvco X (20 to 90 times) < 10
MHz...(8).゜． Δf VCO <0.5 M
Hz~0. 1 1 MHz Therefore, Δfvc. =1
00KHz is sufficient.

Based on the above results, the operation of the embodiment shown in FIG. 1 will be explained. Since f vco is divided by N by the frequency divider 12, its phase is compared with the 100 KHz reference signal by the φ detector 5b, and negative feedback is provided, the frequency relationship after this system is stabilized is f VCO "0. IXNH (MHZ) ・
...(91 However, NM = 1900 to 2000. Since this system does not include a winder, if a phase/frequency comparator (for example, Motorola (7) MC4044) is used as the φ detector 5b, the VCO1 can be free run. Even if the frequency is not strictly limited, it is possible to match the frequency with the stability of the IOOK}lz reference signal. Therefore, reviewing equation (3), f osc = RM ・f v−. f IF ・
”CI (11, and R M r r VCO
+ f IF calculation method is the target frequency f o
It can be calculated from mc using the following procedure. Alternatively, what is meant by the αυ equation and (self) equation is that even if the tuning step of Δf VC6 is changed in equation (8), the frequency change after multiplication is within 1QMHz, so the approximate multiplication order R. If we give f
Since the IF has a degree of freedom of 1QMHz width, it is always possible to This is because of the theory that there should be an fvco that can be set to the target frequency ("f o * c + f + y) later. The αυ formula is calculated from the lowest possible multiplication order to derive its R. The basic idea is to try to It is quite possible that there are multiple numbers, but if one is selected and determined, there will be no inconvenience and the circuit can operate normally.By the way, in the conventional example shown in Fig. 8, the frequency is 10MHz. For the following tuning changes, it is sufficient to simply change fIF, but in the configuration shown in Figure 1, there may be cases where all settings must be changed even for the smallest unit of frequency change.To deal with this, In equation 5), f■ is a variation width of lQMHz, but this is also a variation width of 20MHz (for example, 2 0 MHz
40 MHz), it is easy to understand that a similar effect can be produced. Here, when R4 is set using equation (11) and configured as actual hardware, f
VeO may be slightly higher than 200 MHz, but in such cases N. If you set it a little higher, it will not affect the operation of the circuit as a whole. Although the above embodiment shows a circuit that does not use the ξ mixer, it may be a circuit that mixes the 210 MHz reference signal with the mixer 2b as in the second embodiment of the present invention shown in FIG. In the configuration shown in Figure 1, the frequency division ratio N = 1900 to 2
000, but as in the configuration shown in Figure 2, the frequency is 210MHz.
If mixed with 10M}Iz~20MHz, the frequency division ratio by the frequency divider 12a can be set to a small value of N'N=100~200, and the speed of the circuit can be increased. The configuration shown in Figure 2 is decisively different from the conventional configuration shown in Figure 8.
There is no need to be particular about the frequency of 210MHZ, and VCO1
This means that it can be separated from the free-run frequency with a margin. (Conventionally, it was not possible to change 200 MHz.) Furthermore, the configuration shown in FIG. 3 is a diagram showing a third embodiment of the present invention in which the frequency resolution does not need to be so fine.
If the frequency resolution of fesc is LOOKHz, then LP
The output of the FIO can be directly divided by the frequency divider 13,
The entire band can be phase-synchronized using one type of reference signal (100 KHz).

With this structure, the relationship between the frequency division ratio K of the frequency divider 13 and fIF can be expressed as follows.

Next, a fourth embodiment of the present invention will be described.

FIG. 4 is a block diagram showing a phase-locked oscillation circuit according to a fourth embodiment of the present invention. is a low frequency band synthesizer oscillator, 15.16 is a read-only memory (hereinafter referred to as ROM), and 17 is an adder. The oscillation frequency f asc of YTO8 was about 4G}lz in the conventional example shown in FIG. 8, because the sweepable bandwidth could not be widened. In this precept, we will use 4-18G as an example.
An example in which the band can be widened over the entire Hz range will be shown. First, for each frequency of fore + rvco + fIF (the reason for setting will be explained later), unlike the conventional example, approximately the following ranges are assumed.

fvco = 268~290MHz
"JS) far = 30~50MHz
-α groan fosc = 4 00 0”1 8
0 0 0 MHz -αD As shown in equation (2) in the conventional example, a new relationship is set for each frequency. If the order of the desired harmonic generated by the multiplier 7 is R8, the relational expression for each frequency is similarly fosc = RM °fvco + fIF
It is possible to set ゛=QlO. Multiplication order (positive integer) = R. is in the following range from the a time formula.

rvco maximum/J\ = 68 However, INT[] indicates that the integer part of the operation result is left and the decimal part is truncated. Therefore R. is always an integer in the range of 13-68.

On the other hand, in the conventional structure, hc. was set independently by the frequency division ratios N and M, but in this configuration, it is set only by the frequency divider 12. The frequency of fVco is divided by the frequency division ratio N, and the resulting frequency is the 100KHz reference signal and the φ detector 5.
Since the phase is compared at point b, the frequency after this feedback system is stabilized is 100KHz. It becomes a multiplied frequency.

fvco -0. I MHz X NM (however, Nx
= integer from 2680 to 2900)...From the α ω 0 ω equation, a characteristic difference between the present configuration and the conventional example arises.

In other words, (in formula 19, the frequency variable range of fVC.
Even though the frequency is limited to a narrow range (about 22 MHz), as can be seen from the formula for α, what is the precept in which only discrete frequencies can be selected at equal intervals? In, R. In order to achieve phase synchronization after mixing the multiplied frequency with the target oscillation frequency foc, it is necessary to absorb the effect within the frequency variable range of fIF. In other words, in the conventional structure, in order to obtain the frequency r esc of 100, as can be seen from equation (2), the frequency rvco set by the frequency division ratios N and M is set to a frequency of 10 MHz or more, fvc, such as f■ sets the remaining frequencies below 10MHz. Even though the frequency divisions handled by fIF and fIF were clearly separated, in this configuration fVc.

There is the above limit on the frequency that can be set, and even if you try to set it in units of IOMHz or higher, there will be a frequency where a setting error will occur, and it is necessary to compensate for it with fIF *The frequency variable range of fIF is 20MHz, so among these 10
Up to 10 MHz is used for this compensation, and f is used for the remaining 10 MHz range.
If 03e can be set to less than 10 MHz, the above theory will be confirmed. The frequency required for the above compensation out of f■ is fIFE
If the set frequency below 10MHz is f;2, then α
From the ω formula, f IF− f IFg + f
? FC-30~50MHz) ”・Q
@However, 30MHz≦f Ivt < 4 0 MHz
O≦f; r<10 MHz. Here αa+. (If we rearrange the 2S formula, fos
c ”=Rx ・fveo +f+rt +f<r, so fosc f<r=Rx−fvco+f+.

...(2l) ...(22) ...(23)? Yes, (23). From equation (24), to obtain the frequency f03, set Rl4 fvco + f Ivw to IQMI{z unit or more, and set fIF to a frequency less than 10 MHz.

Based on the above idea, it will be explained that equation (24) can be realized in this configuration. The important elements for formula (24) to be effective are the frequency variable ranges of fvcct and fl4 and their discrete and equal frequency setting intervals (hereinafter referred to as frequency steps). R. Since is an integer, it is natural that the frequency steps of fVco and f■1 must be the same. First, fV.

The frequency variable range of is described below. Frequency of f03? The range is wideband, and the biggest factor that makes this possible is that the multiplication order (R) can be changed at any time. fVc. The frequency variable range of R. is rather an integer. The frequency is discrete and coarse due to changes in the frequency. It is narrow compared to the change,
Considering the relationship in equation (24), the idea is that if the error for f0, . can be varied to the extent that the change is within 10 MHz, the remaining error can be absorbed by setting fIFE. For this purpose, from equation (24), f. ll
! When near the lower limit frequency of c, R is the minimum multiplication order (=
13), and the fVC due to the change in R around this point. Since the frequency variable range of fVco is required to be the widest, the necessary variable range of fVco is:
lMinimum 10N ・lfvcol lower limit frequency ≦1 0 M
It turns out that it is good if it becomes Hz - (25). Here, 290M}lz is substituted from equation (3) as the Ifvcol upper limit frequency.

13X290 MHz- (13+IL l fvc
o Lower limit frequency ≦10MHz? ．． Since the l f vco I lower limit frequency is 268 MHz, it can be proven that the variable range of r vco shown in equation (15) is sufficient. In contrast to the above, even if 268 MHz is first determined as the lfvcof lower limit frequency and the upper limit frequency is similarly determined, it is found that it is within the variable range of equation (15).

Next, we will discuss how fine the f vCo frequency step is required. As above, f
Since it is based on the assumption that 10MHzL is not allowed as the variable range of IFE, from equation (24), when the frequency step of r vco is changed by the minimum unit, the frequency change after multiplication is 1.
If it is within 0 MHz, it can be set within the range that can be compensated by fIFt. Therefore R. The larger the multiplication order, the larger the rate of change due to the frequency step, so the IR
II+What kind of f is it if it settles within 10MHz at maximum? This means that it can also deal with e. Therefore, if the frequency step is Δfvco, 10 MHz≧IRMI maximum・Δf veo=68
・△fVc.

...(26)?゜． △r vco≦147MIlz. In order to realize @, it is convenient to use a frequency that is easy to separate, so let's use 100KHz, for example. This result is (1
This matches the frequency step of r vco shown in equation 9). Also, as mentioned above, the thinness of fVeO and fIF must match, so the following equation can be obtained. Δfvco! From the result of △f+yt-100KHz or more, the frequency of fosc shown in equation (24) in units of 1QMHz or more can be set to R by setting the frequency of rvco to an appropriate value. The frequency after multiplication is always f shown in equation (21)
IF! It can be set within the range of . Therefore, in order to obtain the desired oscillation frequency fo*c, the corresponding Rs.
fvco (or frequency division ratio N,), fIFE+f'l
Regarding F (15). (19). (21), (2
2). It is necessary to calculate it by calculation from equation (24). If you do this incorrectly, the actual device will have rvc
. Since a large number of harmonics are output, it is possible to accidentally synchronize the phase to another multiplication order that is not desired.
Next, we will explain this calculation method. Naturally, at a frequency where fosc is high, the multiplication order is also high, so fVc.

(24) at multiple frequencies within the variable frequency range of (24)
It becomes possible for there to be an r vco that satisfies the equation. Any frequency is fine as long as it is satisfied, but the values will vary depending on how you calculate it (or how you think about the calculation). Nowadays, the performance of computers has improved, so for example, r vco
Using equation (24), we sequentially calculate whether there is a multiplication order: R8 that satisfies equation (15) at a frequency step of Δr vco over a variable frequency range of , and extract all matching results. Although this method requires a huge amount of calculation, it is quite feasible.

However, there is also a method that can perform calculations using the computing power of a personal computer without relying on brute force.

The point is that even if there are multiple answers, you only need to know one of them, so we will introduce an example of how to find it.

As mentioned above, R. fVc other than Since the frequency variable range for and f IFt is narrow, first f VCQ and fI
Ft is temporarily set, and from now on, R. 4 is more convenient in determining r osc from equation (24). In other words, f VCO and f IF! If f is set to be the center of the frequency range, the desired oscillation frequency f. Depending on C, there may be cases where R4 cannot be an integer from equation (24). R. must be an integer, so if you round off the calculation result, you get fVC. and R. which is closest to the center frequency of r+rx. should be able to be determined. Expressing this in the formula, RM-...(27). '． I fesc 1 1 0MHz= fo
sc f'+r ''{2B).The reason why 0.5 is added in equation (27) is to round it off.The lf+rtl center frequency is 35MHz, and lf
Since the vcol center frequency is 279Mllz, it can be obtained as ...(2b). Once Rl4 is determined, similarly, f VCO has a wider frequency variable range than f IF, so it is decided to decide first. This time it's R. Since it is known that
f fFl! Determining afVl:0, which only needs to be assumed as the center frequency, is equivalent to finding the frequency division ratio N8 from equation (19), so it can be found as follows.

? ...(30) Since RX and NM (that is, fvco) have been determined from the above, fIFt and f'■ can be calculated from equation (24). The process of these calculations is summarized and shown in a flowchart in Figure 5. ROM15 and 16 reflect these results in the configuration shown in FIG. Target frequency 1 f osc l fV corresponding to 10MHz in 10MHz units
C.

Calculate the frequency of N. in advance using equation (30) using a computer or the like, and use the obtained frequency division ratio N. To set by RO
The calculation result is input into M15.

Similarly, if the compensation frequencies f and ■ are stored in the ROM 16, the frequencies f and r can be set by calculating the frequency f′lF below 10 MHz and the output of the ROM 16 using the adder 17 as shown in equation (20). Become.

Although the above embodiment is characterized in that no mixer is used, as in the fifth embodiment of the present invention shown in FIG. 6, the mixer 2b can produce 300 M! The circuit configuration may be such that the signal is mixed with the reference signal of z.

In the structure shown in Figure 4, the division ratio is N. = 2680 to 2900, but in the configuration shown in Figure 6, after frequency conversion, it was 10 to 32M.
}lz, so the frequency division ratio by the frequency divider 12a is 100~
Since it can be set to a small value of 320, r vco
This has the advantage of speeding up the feedback loop that creates the frequency. This configuration is similar to the conventional configuration, but unlike the conventional configuration in which the frequency of the VCOL could not be changed arbitrarily, it is not subject to this restriction and can provide flexibility in design. FIG. 7 is a diagram showing a phase synchronized oscillation circuit according to a sixth embodiment of the present invention. This configuration shows that the circuit can be easily constructed using only one reference signal, and the low-frequency synthesizer is omitted and replaced with a single reference signal. This is the case where the frequency is divided by K by the frequency divider 18. As mentioned above, r vco and fIFE are the same frequency step, and if fIF is also the same frequency step, the 100 KHz reference signal shown in the example can be used, so K = (f + vt + fly) / 1 0 0
It is possible to have a simple configuration in which fIF is directly frequency-divided according to the frequency division ratio calculated in KHz. In this case, a circuit that divides the frequency by K is added, so the response, output spectrum, etc. are slightly inferior. [Effects of the Invention] As described above, according to the present invention, in a phase-locked oscillator circuit based on multiplication, in a plurality of multiplication orders in which the frequency range of the desired output frequency fosc extends beyond the frequency range of the VCO frequency fvca. Since it is configured to be phase synchronized, it is possible to eliminate the need for a mixer in the hardware configuration of the fwco production loop, and it is also possible to configure the fwco to obtain fvca with only one type of frequency division ratio. What is the unique image of a phase-locked circuit that includes a mixer in the circuit? It is possible to prevent erroneous phase synchronization with the side frequency, and it is possible to eliminate f vco frequency limitations.

Further, according to the present invention, in order to obtain the above-mentioned circuit configuration, means for setting discrete values at equal intervals as the frequency of the fvco, and a frequency f, for compensating the discrete value, are provided. (2) A means for setting the above-mentioned f VC6 frequency and discrete frequencies f' at equal intervals or narrower intervals.
Means for setting IF and the above f IF! and f'lF to obtain the above fIF, the fundamental wave generation circuit has a simple configuration, the device can be made inexpensive, and the phase synchronized oscillation circuit can be realized over a wide frequency band. It has the effect of obtaining

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a phase-locked oscillation circuit according to a first embodiment of the present invention, and FIG. Figure 3 is the second example of this invention.
, a block diagram showing a third embodiment, FIG. 4 a block diagram showing a phase synchronized oscillation circuit according to a fourth embodiment of the present invention, FIG. 5 a block diagram showing a ROM-embedded embodiment, and FIG. 1 is a block diagram showing a conventional phase-locked oscillation circuit. 1 is a voltage control circuit that requires multiplication, 7 is a multiplier, 8 is a microwave band voltage controlled oscillator, 12 is a frequency divider, 14 is a low frequency band synthesizer oscillator, 15.16 is a read-only memo. the law of nature,
17 is an adder. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

[Claims] (1) After mixing the frequency obtained by multiplying the output frequency f_v_c_o of the voltage controlled oscillator by a multiplier and the output frequency f_o_s_c from the desired oscillator, another signal frequency f_I
_F. A phase-locked oscillator circuit that is configured to perform phase synchronization with f_o_s_c in a plurality of multiplication orders over a frequency range of f_v_c_o. (2) After mixing the frequency obtained by multiplying the output frequency f_v_c_o of the voltage controlled oscillator by a multiplier and the output frequency f_o_s_c from the desired oscillator, another signal frequency f_I
In a phase-locked oscillator circuit that is phase-synchronized with _F, the frequency range of the f_o_s_c is configured to be phase-synchronized at a plurality of multiplication orders extending beyond the frequency range of f_v_c_o, and discrete values are set at equal intervals as the frequency of the f_v_c_o. and a frequency f_I_F_E for compensating the discrete values.
means for setting a discrete frequency f'_I_F at equal intervals or narrower intervals than the frequency of said f_v_c_o; and means for adding said f_I_F_E and f'_I_F to obtain said f_I_F. A phase-locked oscillation circuit characterized by comprising: