JPH0341882A - Time axis conversion circuit and in-line polyphase split pre-stage prediction coding circuit - Google Patents

Abstract

PURPOSE:To save the line memory capacity, to reduce the propagation delay time and to improve the real time performance of signal transmission by adding a picture element data to after or before both end picture element data to apply time axis conversion. CONSTITUTION:A picture element data read from a readout memory group and retarded via one picture element delay circuits 58-76 corresponding to memory groups at each readout clock is selected by a picture element selection selector control signal supplied from a ROM 96 to each selector. A picture element data string OUT 1 is outputted from the selector 78 and used for pre- stage prediction coding in a pre-stage prediction coding circuit 84, a picture element data string OUT 2 is outputted from the selector 80 and used for pre- stage prediction coding in a pre-stage prediction coding circuit 86, and a picture element data string OUT 3 is outputted from the selector 82 and used for pre- stage prediction coding in a pre-stage prediction coding circuit 88.

Description

[Detailed Description of the Invention] [Summary] Regarding a time axis conversion circuit that performs polyphase division within a line and an intraline polyphase division pre-prediction coding circuit that uses the same, the present invention provides a time base conversion circuit that performs polyphase division within a line, and an intraline polyphase division pre-predictive coding circuit that uses the same, while enjoying the benefits obtained from polyphase division. , in order to eliminate the disadvantage of converting a pixel data string into predictive code B in the case of intra-line polyphase division, all pixel data in each image line is stored in N memories with a capacity of 1/N the number of pixel data. pair and the first
a write circuit for alternately writing N pixel data of an image line into both memory groups in the memory pair in response to a speed clock; A pixel data delay circuit for each memory pair that generates each pixel delay output from 1 pixel delay to N pixel delay for each pixel data, and a pixel data delay circuit for each memory pair that generates each pixel delay output from 1 pixel delay to N pixel delay for each pixel data, and a pixel data delay circuit for each memory pair in the read-side memory group in response to a second speed clock. a readout circuit that generates a readout address to cause the readout; N selectors that receive each of the phase formation delay outputs of each pixel data delay circuit; The configuration includes a selection control circuit that provides output selection control of delayed outputs that become each pixel data string in the phase.

[Industrial Application Field] The present invention relates to a time axis conversion circuit that performs polyphase division within a line, and an intraline polyphase division pre-predictive coding circuit that uses the same.

In digital transmission of high-definition TV (HDTV) signals, compression encoding such as pre-predictive encoding is applied to the image signal, and then the compressed encoded data is transmitted. In compression encoding, since the amount of information to be transmitted in the image signal is large, it is necessary to sample the image signal at high speed.

This means that the encoding circuit must be constructed of high-speed circuit elements.

[Conventional technology]

Techniques for configuring pre-predictive coding circuits without using high-speed circuit elements are known in the art. FIG. 5 shows an inter-line polyphase division pre-predictive coding circuit that uses this technique. This circuit is an example of three-phase splitting. A/D conversion circuit 2
The image data A/D converted at 0 is processed by a serial/parallel conversion circuit (
S/P) 200, each of the lines corresponding to each of the memories belonging to one of the 3-line memory pairs (201, 203, 205 in FIG. 5) is sequentially written ( Wl in (2) and (3) of Figure 5.

W2EW3. ···reference. This sequentially written three-line memory pair is hereinafter referred to as a phase. ), the selector 2E0 sequentially selects each line written in the previous time from each memory belonging to the other of the three-line memory pair (see 202E204, 206 in FIG. 5) during the writing time. to select and read out pixels (R1, R2iR3, . . . in (2) and (3) of Fig. 5).
and (4), (5), (6) in Figures 5 and 6.
reference). Each line of time-series pixel data that is sequentially read out is subjected to pre-predictive coding by conventional pre-predictive coding circuits 84, 86, 88) provided corresponding to each phase. 116 is a subtraction circuit, 11B is a quantization circuit, 120 is an addition circuit, and 122 is a one-pixel delay circuit.

[Problem to be solved by the invention]

In this way, the pixel data of each line extended to three times the time period is processed by the corresponding pre-prediction encoding circuits 84 and 86.
．． By performing pre-prediction encoding at 88, the operating speed of the circuit elements used for the encoding can be adjusted without performing the pre-processing.
The operating speed of the circuit elements in the case of direct pre-predictive coding is reduced to one-third.

This line-to-line 3-phase split pre-predictive coding circuit requires a memory capacity of 2 x 3 lines for each phase, which increases the propagation delay time of coded data in the 3-line memory of each phase. There is. This large propagation delay time results in poor real-time signal transmission.

The present invention was created in view of such problems, and provides a time axis conversion circuit that can perform time axis conversion with a significant reduction in line memory capacity, and an intra-line multiphase division pre-prediction using the same. Its purpose is to provide an encoding circuit.

[Means for Solving the Problems] FIG. 1 shows a block diagram of the principle of the present invention. As shown in this figure, the time axis conversion circuit of the present invention converts all pixel data in each image line into N memory pairs 2z (i=1.2E . . . N) each having a pixel data number capacity of 1/N. , a write circuit 4 for alternately writing N pixel data of an image line into both memory groups 2E and 2O in the memory pair 2 in response to a clock at a first speed; and a read-side memory in the memory pair 2E. Each memory 2O of group 2O or 2v, or 26. 1 for each pixel data to be read out.
a pixel data delay circuit 6 for each memory pair that generates each pixel delay output from pixel delay to N pixel delay; and the readout side memory group 2O or 2 in response to a second speed clock.
a readout circuit 8 that generates a readout address to each memory 2O or 2Ei in E and causes the readout, and N selectors 10 that receive each of the phase formation delay outputs of the respective pixel data delay circuits 61 as inputs. and a selection control circuit 12 that provides output selection control for each of the phase formation delay outputs to each selector to form a delay output that becomes each pixel data string in the phase. The read address is generated by adding a required number of encoding pixels to the phase edge pixels of the formed phase, and a prefix code added to the phase edge pixels of each phase. The time axis conversion circuit of the present invention is configured such that the second speed is faster than the first speed by the amount of pixel data for conversion. The intra-line polyphase division pre-prediction coding circuit includes a time-base conversion circuit 1 and a pre-prediction coding circuit 14 . provided for each phase output of the time-base conversion circuit 1 . (1=
1.2E...,N) A time axis conversion circuit 1 of a multiphase division pre-predictive coding circuit was constructed from the following components. The components include N memory pairs 2i having a pixel data number capacity of 1/N for storing all pixel data in each image line, and storing N pixel data of the image line in response to a clock at a first speed into the memory pairs 2i. A write circuit 4 for alternately writing to both memory groups 2E or 2O in the memory pair 2E, and a write circuit 4 connected to the output of each memory 2O or 22 of the read-side memory group 2O or 2E in the memory pair 2. , a pixel data delay circuit for each memory pair, which generates each pixel delay output from 1 pixel delay to N pixel delay for each pixel data to be read;6. and each memory 20i or 2E in the read-side memory group 2O or 2E in response to the second speed clock.
a readout circuit 8 that generates a readout address to readout and causes the readout; and each of the pixel data delay circuits 6. 6. Each phase forming delay output circuit 6. N selectors 10. receiving each of the phase delay outputs as inputs. and a selection control circuit 12 that provides output selection control for each of the phase formation delay outputs to each selector to form a delay output that becomes each pixel data string in the phase, and generation of the read address is performed by the formation of the phase formation delay output. The second speed is generated by adding a required number of encoding pixel data to the phase edge pixels of each phase, and the second speed is generated by adding a required number of encoding pixel data to the phase edge pixels of each phase. The circuit is configured such that the speed is faster than the first speed.

[For production]

Each of the pixel data in each pixel line is alternately written to the memory group 2E or 2O which is the write side of the memory pair 2E, and the memory 2 of the memory group 20 or 2E which is not in the write operation.
Pixel data is read from O1 or 2O. The readout is performed in such a manner that a required number of encoding pixels are added to the phase edge pixels formed as described below.

In this way, each of the pixel data read from each memory pair 2E is transmitted to the pixel data delay circuit 6. N pixel delays are given to the pixel delay, and the output pixel data of each pixel delay is output therefrom.

Those, pixel data delay circuit 6. Each of the phase-corresponding phase delay outputs from the selector 10 is selectively output under the control of the selection control circuit 12 at the corresponding selector 10. Each of the pixel data of the relevant phase is output from each of them.

For example, the pixel data strings for each phase are stored in the pre-prediction encoding circuit 14. It is pre-predictively encoded and output.

As mentioned above, since the pixel data for predictive encoding is added to the end pixels of each phase, when these pixel data sequences are subjected to pre-predictive encoding, etc., the intra-line polyphase division is performed. It is also possible to prevent image quality deterioration due to multiphase division.

This effect can be obtained while preserving the effect that can be enjoyed by multiphase partitioning. In other words, a smaller line memory capacity, ie, a reduction in the circuit scale, is achieved, which also shortens the propagation delay time of pixel data, and improves the real-time nature of signal transmission.

〔Example〕

FIG. 2 shows an embodiment of the invention. In this figure, an analog/digital conversion circuit (A/D) 20 converts each pixel of an analog image signal into a bit-parallel digital signal. One pixel delay circuit (D) in analog/digital conversion circuit 20
A 22E1 pixel delay circuit 24 and a 1 pixel delay circuit 26 are connected in series. One pixel delay circuit 26 is connected to memory pair 34
Memory (MEMI)40. or memory (ME
M2) Connected to the data write input of 42. The 1-pixel delay circuit 24 is connected to the memory (MEM3) 4 of the memory pair 36.
4 or the data write input of memory (MEM4) 4'6. One pixel delay circuit 22 is connected to memory pair 38
Memory (MEM5) 48. or memory (MEM6) 5
Connected to the 0 data write input. Memory (ME
M1)40. Memory (MEM3) 44. Memory (M
The write address of EM5)4B is the address output from the write counter 9o at the same time as the selector 98. selector 102, selector 106, and write address lines 98W, 102W, and 106W, respectively.
I-17 (MEMI)40. Memo+) (MEM3)4
4°JMo+) (MEM6) 48 is supplied to the write address input. Write address lines 98W, 102W.

106W is not shown in the figure to avoid congestion in the figure. A read address line 100R, which will be described later.

104R, 108R1 or write address line 100W, 1
04W, 108W, read address lines 98R, 102R
, 106R are also similar. The write counter 90 is reset by the vertical synchronization signal. This memory (
MEMI)40. Memory (MEM3) 44. memory(
While writing to the MEM6) 48 is being performed, readout control by the readout counter 94 is performed by the memory (MEM2).
) 42E memory (MEM4) 46. Memory (MEM6)
50, and the address output from the ROM 96 under the read control is sent to the selector 100. Selector 104. selector 108, and read address lines 100R, 104R, 10, respectively.
Memory (MEM2) through 8R 42E memory (MEM
4)46. It is supplied to the read address input of the memory (MEM6) 50. These writing and reading are completed,
Memory vs. 34. Memory vs. 36. Writing and reading to and from the memory pair 38 are performed using the memory (MEMI) as in the past.
40', memory (MEM3) 44. Memory (MEM5)
48 and memory (MEM2) 42O memory (MEM4
)46. When switching between memory (MEM6) 50, memory (MEM2) 42, memory (MEM4) 46.
The same write address supplied to the memory (MEM6) 50 is written to the memory (MEM1) as described above.
40. Memory (MEM3) 44. Memory (MEM5) 4
The addresses from the next address simultaneously supplied to the write address inputs of 8 and 8 are input from the write counter 90 to the selectors 100. Selector■04. Selector 108
and write address lines 100W, 104W, 108W
Memory (MEM2) 42 Memory (MEM4
)46. It is supplied to the write address input of memory (MEM6) 50. In addition, in this alternation, the memory (MEMI) 40, the memory (MEM3) 44 . The readout address input of the memory (MEM5) 48 is controlled by the readout counter 94 so that the ROM 9
The addresses sequentially output from .6 to selector 98. Selector 102E Selector 106 read line 98R
, 102R, 106R to memory (MEMI) 4
0. Memory (MEM3) 44°Memory (MEM
5) Provided to the 4B read address input. These selectors 98. Selector 102, selector 106, and selector 100. Selector 104. The switching control of the selector 10B is performed by the memory (MEMI) 40. Memory (MEM3
) 44 memory (MEM5) 4B enable input and memory (MEM2) 42E memory (MEM4) 46,
This is generated in synchronization with switching control of the enable input of the memory (MEM6) 50, which will be described later. The switching control is RO
Performed by M96.

Further, the relationship between the address registered in advance in the ROM 96 and the address supplied from the read counter 94 is set as described below.

From the ROM 96, memory (MEMI) 40°, memory (MEM2) 42E memory (MEM3) 44, memory (MEM4) 46. A write control signal is sent to the write enable (chip enable) of the memory (MEM5) 48 and memory (MEM6) 50 via the write control line 92W, and read to the read enable (chip enable) via the read control line 92R. control signals are supplied. A write operation is performed on the memory to which the write control signal is supplied (schematically, switch circuits 2i and 3
0.32), the memory to which the read control signal is supplied performs a read operation (schematically indicated by switch circuits 52i54, 56). The write control line 92W and the read control fffU line 92R are not shown as separate lines to avoid congestion in the figure.

Memory of memory pair 34 (MEMI) 40. or memory (
The data readout output of MEM2) 42 is connected to the input of one pixel delay circuit 58 among one pixel delay circuit 58, one pixel delay circuit 60, and one pixel delay circuit 62 connected in series. Memory of memory pair 36 (MEM3) 44. Alternatively, the data readout output of the memory (MEM4) 46 is connected to the input of one pixel delay circuit 64 among the one pixel delay circuit 64, one pixel delay circuit 66.1 pixel delay circuit 68 connected in series. Memory pair 38 memory (MEM5) 4B,
Alternatively, the data readout output of the memory (MEM6) 50 is output from the 1 pixel delay circuit 72E1 pixel delay circuit 74 connected in series.
, and connected to the input of one pixel delay circuit 72 of one pixel delay circuit 76.

The three inputs of the selector 78 are connected to the outputs of the one-pixel delay circuit 62E, the one-pixel delay circuit 68, and the one-pixel delay circuit 76, respectively. The three inputs of the selector 80 are connected to the outputs of a 1-pixel delay circuit 60, a 1-pixel delay circuit 66, and a 1-pixel delay circuit 74, respectively. One pixel delay circuit 58 is connected to each of the three inputs of the selector 82.
．． The outputs of the 1-pixel delay circuit 64 and the 1-pixel delay circuit 72 are connected. Selector 78. Switching control of the selector 80° selector 82 is caused by a selection control signal for pixel selection output from the ROM 96 under read control of the successive counter 94. The selection control signal for pixel selection is transmitted from the ROM 96 to the selector 78. Selector 80. Two bits are read out for each selector 82 and are applied to the selection input of the corresponding selector via lines 110.112i114. As before, lines 110, 112i114 are not shown as separate lines to avoid cluttering the drawing.

The output of the selector 78 is supplied to a forward predictive encoding circuit 84, and the output of the selector 80 is supplied to a forward predictive encoding circuit 86.
The output of the selector 82 is supplied to a pre-prediction encoding circuit 88 . As will become clear from the description below, the output of the selector 78 is the first phase output obtained by dividing one image line into three phases, the output of the selector 80 is the second phase output, and the output of the selector 82 is the first phase output. It has 3 phase output. Pre-prediction encoding circuit 84. Pre-prediction encoding circuit 86. The pre-prediction encoding circuit 88 includes a subtracter 116, a quantization circuit 118, an adder 120.1 and a pixel delay circuit 122.

In FIG. 2, memory pair 34. Memory pair 36°Memory pair 38 corresponds to memory pair 2□ in FIG.
MI)40. Memory (MEM3) 44, memory (MEM3)
5) 48, memory (MEM2) 42, memory (MEM4)
)46. The memory (MEM6) 50 corresponds to the memory groups 2E and 2E in FIG. Memory (MEMI) 40. Memory (MEM3) 44 and memory (MEM5) 4B are the first
Figure memory 2! I+ 2E2E ...corresponds to +2EN, memory (MEM2) 42E memory (MEM4
)46. The memory (MEM6) 50 is the memory 20 in FIG.
++ corresponds to 202E..., 2O. 1 pixel delay circuit 22 to 1 pixel delay circuit 26, writing counter 90, ROM 92, selector 98 to selector 10
8 corresponds to the write circuit 4 in FIG. The one-pixel delay circuit 58 to the one-pixel delay circuit 76 correspond to the pixel data delay circuit 6i in FIG. Read counter 94, ROM
96 and selectors 98 to 108 correspond to the readout circuit 8 in FIG. Selector 7B, 80.82 corresponds to selector 10 in FIG. Read counter 9
4. The ROM 96 corresponds to the selection control circuit 12 in FIG. Pre-predictive coding circuit 84 to pre-predictive coding circuit 88
is the pre-prediction encoding circuit 14 in FIG. corresponds to

The operation of the embodiment of the present invention having the above configuration will be described below.

The bit-parallel pixel data digitally converted for each pixel by the analog/digital conversion circuit 20 is processed by pixel delay 1 pixel delay circuit 22i1 pixel delay circuit 24.1 pixel delay circuit 2
6 and memory vs. 34. Memory vs. 36. It is distributed to memory pairs 38. Each of the distributed pixel data is alternately switched between Memo JJ and 34. Memory vs. 36. memory pair 38
Memory in (MEM 1) 40. Memory (M
EM3) 44° memory (MEM5) 48, or memory (
MEM2) 42, memory (MEM4) 46. Memory (M
EM6) 50. This alternating switching is caused by alternately outputting the memory 40 . Memory 44. A control signal for writing to memory 48, memory 42 memory 46 . memory 5
control signal for writing to zero. Those memories (MEMl)40. Memory (MEM3) 44
．． Memory (MEM5) 48 (hereinafter referred to as odd numbered memory group), or memory (MEM2) 42E memory (MEM2)
M4) 46, memory (MEM6) 50 (hereinafter referred to as even numbered memory group), odd numbered write clock times (WCI, WC3WC5, . . .
), and for even-numbered memory groups at even-numbered write clock times (WC2iWC4WC6i...), a write control signal (write enable signal or The selector 102 corresponds to the odd-numbered memory group, the selector 102O selector 106, or the selector 100 corresponds to the even-numbered memory group.
．． Selector 104. The count values (write addresses) sequentially output from the write counter 90 via the selector 108 are stored in the memory (MEMl) 40. Memory (MEM3
)44. Memory (MEM5) 48 or memory (MEM2)
) 42E memory (MEM4) 46. Memory (MEM6)
50 write address inputs simultaneously. In this way, the write example memory group [memory (MEM 1) 40. Memory (ME
M3)44. Memory (MEM5) 48 or memory (
MEM2) 42E Memory (MEM4) 46. memory(
Each pixel (3 pixels in this embodiment since the number of phases is 3) input in parallel to each memory in MEM6) 50) is simultaneously written to those memories.

For example, write clock time W at which this writing is performed.
At the read clock time RCl corresponding to CI, the read-side memory group (even-numbered memory group or odd-numbered memory group) [For example, in the leftmost column in FIG. MEMI)40. Memory (M
EM3) 44°Memory (MEM5) Since it is shown as 48, it is an even numbered memory group, that is, memory (MEM2)
42. Memory (MEM4) 46. Memory (MEM6) 5
It becomes 0. Same below. ] To read pixel data from
Reading is performed from each of the storage areas specified by each of the read addresses supplied as will be described later. Then, when the above-mentioned writing and reading are completed, the writing side and the reading side are switched. That is, the odd numbered memory groups become the read side at the successive clock RC2 time, and the even numbered memory groups become the write side at the write clock WC2 time. In this case, each memory of the write side memory group (even numbered memory group) [i.e., memory (MEM2) 42O memory (MEM2)
EM4)46. The write address input of the memory (MEM6) 50) is connected to the selector 100 .
The signals are simultaneously supplied from the write counter 90 via the selector 104 and the selector 108 in the same manner as described above. Further, reading of pixel data from the odd-numbered memory group in parallel with this write clock time is also caused by supplying successive addresses similar to the case of read clock time RC2. At the end, the write clock time WC1
Similarly to the read clock time PCI, the odd numbered memory groups return to the write side at the write clock WC3 time, and the even numbered memory groups return to the read side at the read RC3 time. below,
By repeating similar alternate writing and reading, the memory (MEMI) 40 to memory (MEM6) 5
Writing and reading pixel data to and from 0 continues.

These alternating memory pairs 34. Reading of pixel data from memory pair 36° memory pair 38 occurs as follows.

That is, the read addresses corresponding to the pixel data shown in the respective clock times RCI, RC2iRC3, . . . in the column indicated as the read side in FIG.
At the same time, a count value [read address] specifying the storage area of the read address is output from the continuous reading counter 94. Then, the odd numbered memory group becomes the read side.

The three read addresses read from the ROM 96 at the time of the continuous output clock are sent to the selector 98. which corresponds to the odd numbered memory group. Memory (MEMI) 40. via selector 102E selector 106. Memory (MEM3) 44. memory(
When the read clock is supplied to the read address input of MEM5) 48 and the even numbered memory group is on the read side, R
The three read addresses read out simultaneously from the OM 96 are transferred to the selector 100 corresponding to the even numbered memory group. Memory (MEM2) 4 via selector 104 and selector 108
2. Memory (MEM4) 46. Memory (MEM6) 50
read address input.

At this time, from the ROM 96, the read control line 96R
A read control signal is supplied to the gate enable of these memories 42i, 46, and 50 through.

Pixel data is read from the storage area designated by the read address of each memory in each successive memory group that receives these read addresses.

When writing and reading of the memory pair 34, 36, 38 are switched and the memory 40, 44, 48 becomes the reading side, the supply of the read address in that case is from the ROM 9.
6 to the read address inputs of the memories 40, 44, 48 via the selectors 98, 102O106, and to the read enable of these memories 40, 44, 48 from the ROM 96 via the read control line 96R. A read control signal is supplied.

As described above, each of the pixel data read out from the readout side memory group is processed by one pixel delay circuit 58, one pixel delay circuit 64, one pixel delay circuit 64, one
After 1 pixel time has elapsed since the input to the pixel delay circuit 72, the 1 pixel delay circuit 64.1 is output from the 1 pixel delay circuit 72, and the same 1 pixel delay time is 1 pixel delay circuit 64.
1 pixel delay circuit 60 for the output of pixel delay circuit 58
゜In each of the 1 pixel delay circuits 62, for the output of the 1 pixel delay circuit 64, the 1 pixel delay circuit 64, the 1 pixel delay circuit 6
8, and 1 for the output of the 1 pixel delay circuit 72.
Pixel delay circuit 74.1 is given to pixel data by pixel delay circuit 76. The selection control input of the selector 78 is supplied from the ROM 96 in chronological order to the memory (ME
The output of the 1-pixel delay circuit 76 read from M6) 50, the 1-pixel delay circuit 62 read from the memo IJ (MEM2) 42, and the 1-pixel delay circuit 68 read from the memory (MEM4) 46. A 2-bit selection signal for sequential selection is repeatedly supplied from the ROM 96 for each successive clock, and a 1-pixel delay circuit read out from the memory (MEM5) 4B in time series is supplied to the selection control input of the selector 80. 74 outputs, memory (MEMI)
A 2-bit selection signal for sequentially selectively outputting the output of the 1-pixel delay circuit 60 read from the memory (MEM3) 44 and the output of the 1-pixel delay circuit 66 read from the memory (MEM3) 44 is sent to the ROM for each successive clock. 96, and the selection control input of the selector 82 receives the output of the 1-pixel delay circuit 72 read out from the memory (MEM6) 50 and the 1 pixel read out from the memory (MEM2) 42 in time series. The output of the delay circuit 58 and the one-pixel delay circuit 6 read out from the memory (MEM4) 46
A 2-bit selection signal for sequentially selectively outputting the outputs of 4 is repeatedly supplied from the ROM 96 for each successive clock. As a result, the output of the selector 78 includes the necessary information for pre-predictive coding in each phase when each line is divided into three phases, as shown in the time axis conversion examples of FIGS. 4 and 3. The pixel data stream to which pixel data has been added (pixel data string of each phase) is passed through a conventionally known pre-predictive coding circuit 84 and pre-predictive coding circuit 86 . It can be supplied to a pre-prediction encoding circuit 88 . This prevents discontinuities from being created at the joints of lines formed by combining these divided phases, which helps to prevent deterioration in image quality.

An example of the operation of the above-mentioned time axis conversion of the image signal will be described below.

For example, as shown in the leftmost column of the write side column in FIG. 2, in response to the write clocks WCI...WC440,
Pixel 1, 2i3. ..., ■318.1319.1
320, sequential write addresses from the write counter 90 are assigned to the selector 98. Selector 102E selector 106
Memory via (MEMI)40. Memory (MEM3
)44. It is supplied to the write address of the memory (MEM5) 48 and written to the storage area specified by the write address. During this time, a write control signal is supplied from the ROM 92 to the write enable of the memories 40, 44, and 48. Also, the memory (MEM2) 42E memory (MEM4) 46. which is read out in parallel during this write operation. A read counter 94 (D system?Iff d) is input to the read address input of the memory (MEM6) 50.
Three read addresses are provided that are sequentially read from 96. The read clock at that time is performed by the clock Rel~442 faster than the write clock, and the read enable of the memory 42E46.50 is set to ROM
This is done by a read control signal from 96.

Their read addresses are stored in the memory (M
A read address for reading out the pixel data l of the previous line from the EM2) 42, and any pixel data from the memory (MEM4) 46 (shown as D (dummy) in the figure).

) and memory (MEM6
) 50 becomes the read address for reading out the pixel data 440 of the previous line. Therefore, at the clock time, the ROM
The three read addresses read from selector 100 . Memory (MEM2) 42E memory (MEM4) 4 via selector 104 and selector 108
6. It is supplied to the read address input of the memory (MEM6) 50.

Therefore, memory (MEM2) 42E memory (MEM4)
46. Pixel data of the previous line read from the memory (MEM6) 50 1. D, 440 is a 1-pixel delay circuit 58
．． The signal is supplied to a 1-pixel delay circuit 64 and a 1-pixel delay circuit 72.

Thereafter, in the same manner, the writing side and the reading side are alternately switched line by line, and pixel data is written and read out as shown in FIG. 3.

As described above, the pixel data that is read out from the readout side memory group every readout clock and is being delayed through the one pixel delay circuit corresponding to each memory group is indicated by the dotted line arrow in the readout side column in Fig. 3. The selection of pixel data as shown in R
Since it is generated by the selector control signal for pixel selection supplied from OM96 to each selector, selector 78
A pixel data string 0UTI as shown in the example of time axis conversion in FIG. A pixel data string ○UT2 as shown in the example of FIG. The output signal is then subjected to pre-predictive coding in a pre-predictive coding circuit 88.

〔Effect of the invention〕

As is clear from the above description, according to the present invention,
In time axis conversion to the required number of phases for each line of a raster scan image signal, the pixel data required for pre-prediction encoding of the edge pixels of the pixel data string of each phase is placed after or before the edge pixel data. Since the time axis conversion is performed in an additional manner, for example, the line memory capacity required for time axis conversion can be significantly reduced and the propagation delay time of pixel data can be significantly reduced while preventing image quality deterioration due to pre-predictive coding. It is possible to enjoy significant reduction in time and improvement in real-time performance of signal transmission.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a diagram showing an embodiment of the present invention, Fig. 3 is a diagram showing a time chart of an example of time axis conversion operation in the present invention, and Fig. 4 is a diagram showing the inside of the line. A diagram showing an example of time axis conversion for pre-prediction of phase edge pixels in three-phase division, FIG. 5 is a diagram showing a conventional inter-line three-phase division pre-prediction encoding circuit, and FIG. FIG. 3 is a diagram showing an example of time axis conversion in phase division. 1 and 2, 2i is a memory pair (memory pair 34, memory pair 36°, memory pair 38), 2E. 2O is a memory group (memory (MEM 1) 40
゜Memory (MEM3) 44. Memory (MEM5) 4
8. Memory (MEM2) 42E memory (MEM4) 46
, memory (MEM6) 50), 2□, 2EZ+ ..., 2EN is memory (memory (MEMI) 40. memory (MEM3) 44.
Memory (MEM5) 48), 20++ 202+ ” '+ 2ON is memory (Memory (MEM2) 42E Memory (MEM4) 4
6. Memory (MEM6) 50), 4 is a write circuit (1 pixel delay circuit 22 to 1 pixel delay circuit 26, write counter 90, ROM 92, selector 98 to selector 108), 6 is a pixel data delay circuit (1 pixel delay circuit 58 to 1 pixel delay circuit 76), 8 is a readout circuit (continuation counter 94, ROM 96,
Selector 98 to selector 108.10° are selectors (
12 is a selection control circuit (sequential output counter 94, ROM 96); 142 is a pre-predictive coding circuit (pre-predictive coding circuit 84);
to a pre-prediction encoding circuit 88).

Claims (2)

[Claims] (1) All pixel data in each image line is stored in N memory pairs (2_i) (i=1, 2,
..., N), and N pixel data of the image line in response to a first speed clock are transferred to both memory groups (2_E,
a write circuit (4) that causes data to be written alternately to the memory group (2_O) on the read side of the memory pair (2_i);
O or 2_E) each memory (2_O_i or 2_E_i
) and responsive to a clock at a second speed; and each memory (2_O_i or 2_O_i or 2_E) in the read-side memory group (2_O or 2_E).
a readout circuit (8) that generates a readout address to the pixel data delay circuit (6_i) and causes the readout; and N selectors (10_i) that receive each of the phase formation delay outputs of the respective pixel data delay circuits (6_i) as inputs. , a selection control circuit (12) is provided for each of the selectors to control the output selection of each of the phase formation delay outputs to become each pixel data string in the phase; The second speed is generated by adding a required number of encoding pixel data to the phase edge pixels of each phase, and the second speed is generated by adding a predetermined number of encoding pixel data to the phase edge pixels of each phase. A time axis conversion circuit characterized in that the speed is faster than the first speed. (2) Time axis conversion circuit (1) and the time axis conversion circuit (1)
) is provided for each phase output of the pre-predictive coding circuit (14
_i) In a multiphase division pre-predictive coding circuit having (i=1, 2, ..., N), all pixel data in each image line is stored in N memories each having a capacity of 1/N pixel data. pair (2
_i) and a write circuit (4) for alternately writing N pixel data of an image line into both memory groups (2_E or 2_O) in the memory pair (2_i) in response to a first speed clock; and the memory. Reading side memory group (2_i) of pair (2_i)
O or 2_E) each memory (2_O_i or 2_E_i
) and responsive to a clock at a second speed; and each memory (2_O_i or 2_O_i or 2_E) in the read-side memory group (2_O or 2_E).
a readout circuit (8) that generates a readout address to the pixel data delay circuit (6_i) and causes the readout; and N selectors (10_i) that receive each of the phase formation delay outputs of the respective pixel data delay circuits (6_i) as inputs. , and a selection control circuit (12) that provides output selection control for each of the phase formation delay outputs to each of the selectors as a delay output that becomes each pixel data string in the relevant phase, and the time axis conversion circuit (1) is configured with the selection control circuit (12). , the generation of the read address is generated by adding a required number of encoding pixel data to the edge pixels of the phase to be formed, and pre-encoding added to the edge pixels of each phase. The predictive coding circuit for intra-line polyphase division is characterized in that the second speed is made faster than the first speed by an amount of pixel data.