JPH0340684A - Write clock generator for time axis correction device - Google Patents

Abstract

PURPOSE:To attain digital configuration of the circuit and large scale integration by providing a feed forward system using phase modulation to a write clock generator comprising a conventional PLL system and applying phase modulation to a write clock while eliminating the effect of the forward system onto the PLL. CONSTITUTION:A video signal given to an input terminal A is converted into a digital code by a digital processing means 1. A phase error signal is inputted to a delay means 3 through an adder means 4, subject to a delay equivalent to one line of the video signal and the retarded signal is returned to the adder means 4. An output of the adder means 4 is subject to correction of the frequency phase characteristic by a loop filter 8, the result is fed to a variable frequency oscillation means 5, whose oscillating frequency is controlled. As a result, a write clock is phase-locked to the input video signal. Moreover, an output signal of the adder means 4 is given to a phase modulation means 6 to modulate the phase of a write clock to trace a time axis fluctuation component in a high frequency not traced by only a feed back loop.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a write clock generation device for a time axis correction device that generates a write clock that follows time axis fluctuations of a video signal.

When playing back a video signal recorded on a conventional recording medium such as a video disc, the video signal generally has a time axis error (
jitter). If there is such jitter in the reproduced signal, the effect will be a direct synchronization disturbance with respect to the video signal, and at the same time, if the video signal is a composite color signal, color unevenness will occur and the image quality will deteriorate.

Therefore, in this type of playback device, a clock that follows the fluctuation of the time axis of the video signal is generated, the video signal is temporarily written to the memory in synchronization with this clock, and the video signal is read out from the memory using a stable reference clock. Time base correction devices are often used to remove jitter from the signal. There is a method using a phase locked loop (PLL) as a write clock generating device for such a time axis correction device.

FIG. 7 shows a block diagram of such a write clock generating device. The clock generated by the variable frequency oscillation means 5 is frequency-divided by the frequency dividing means 7 and supplied to the phase comparison means 2. The phase comparison means 2 compares the phases of the horizontal synchronization signal and the internal horizontal synchronization signal. The phase error signal obtained by the phase comparison means has its frequency phase characteristic corrected by the loop filter 8, and then is given to the variable frequency oscillation means 5 to control its output frequency, and the clock is set on the time axis of the input video signal. It follows the fluctuations. (For example, Japanese Patent Application Laid-open No. 51-93817) Also,
For example, as stated in Japanese Patent Application Laid-Open No. 53-148317,
A configuration is also known in which a phase modulation system called automatic phase control (APC) is further added to the above system to improve followability.

Problems to be Solved by the Invention In a system using a PLL, the interval at which an error signal is obtained is limited to the interval between horizontal synchronization signals due to the nature of the video signal, so it is difficult to increase the loop gain at high frequencies. As a result, it has been difficult to sufficiently follow time-axis fluctuations in particularly high frequencies of the input video signal.

Furthermore, in the case of a configuration in which an APC is further added to the PLL system in cascade, there is a problem that the configuration becomes complicated. Furthermore, in order that the operation of the APC does not affect the PLL, phase comparison must be performed on the analog signal before the video signal is digitized. As a result, there was a problem in that it was difficult to digitize the circuit and convert it into an LSI.

Means for Solving the Problems In order to solve the above problems, a write clock generation device for a time axis correction device according to the present invention includes a variable frequency oscillation means for generating a signal with a frequency corresponding to a control input, and the variable frequency oscillation means. phase modulation means for applying phase modulation to the output signal of the output signal and outputting it as a write clock; digitization means for digitizing the video signal based on the write clock; and frequency division means for dividing the frequency of the write clock;
a phase comparison means for comparing the output of the frequency dividing means and the phase of the burst signal or horizontal synchronization signal of the digitized video signal and outputting a phase error signal;
a delay means having a delay time equivalent to a line; an addition means for adding the output of the delay means and the phase error signal and supplying the addition result to the delay means; It is equipped with an additional loop filter.

Further, the write clock generation device of the time axis correction device of the present invention includes variable frequency oscillation means for generating a write clock signal of a frequency according to a control input, and digitization means for digitizing a video signal based on the write clock. and frequency dividing means for dividing the frequency of the write clock, and comparing the output of the frequency dividing means with the phase of the burst signal or horizontal synchronization signal of the digitized video signal and outputting a phase error signal. a phase comparison means; a delay means having a delay time equivalent to one line of the video signal; a first addition means for adding the output of the delay means and the phase error signal and supplying the addition result to the delay means; a loop filter that corrects the frequency phase characteristic of the output of the first addition means; a pulsing means that converts the output of the first addition means into a pulse having a pulse width or pulse height according to the value of the first addition means; The second adding means adds the output of the first adding means and the output of the pulsing means.

Function: With the above-described configuration, the present invention can generate a write clock that follows high-frequency time axis fluctuations that cannot be followed by PLL, that is, feedback loops alone. Moreover, it can be easily digitized.

In addition to the above-mentioned effects, the feedforward system can be realized with a simple configuration suitable for digitalization.

Embodiment Hereinafter, a write clock generating device for a time axis correction device according to an embodiment of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of a write clock generation device of a time axis correction device according to an embodiment of the present invention. In Figure 1,
1 is a digitizing means, 2 is a phase comparison means, 3 is a delay means, 4 is an addition means, 5 is a variable frequency oscillation means, 6 is a phase modulation means, 7 is a frequency division means, and 8 is a loop filter.

The clock signal outputted from the variable frequency oscillation means 5 undergoes phase modulation by the phase modulation means 6, and then is outputted as a write clock. A video signal applied to input terminal A is converted into a digital code by digitizing means 1 in synchronization with a write clock. Further, the frequency dividing means 7 divides the write clock to a horizontal synchronization frequency and outputs an internal horizontal synchronization signal. The phase comparator 2 detects the phase difference between the internal horizontal synchronizing signal and the horizontal synchronizing signal in the digitized video signal and outputs a phase error signal. The phase error signal is input to the delay means 3 through the addition means 4, and is returned to the addition means 4 after being delayed by one line of the video signal.

After the output of the adding means 4 undergoes frequency phase characteristic correction in a loop filter 8, it is supplied to a variable frequency oscillation means 5 to control its oscillation frequency. As a result, the write clock becomes phase-synchronized with the input video signal. Further, the output signal of the addition means 4 is applied to the phase modulation means 6 to modulate the phase of the write clock, thereby making it follow a high frequency time axis fluctuation component which cannot be followed by the feedback loop alone. However, since this phase modulation is a form in which a feedforward system is inserted into the PLL loop, the loop characteristics change. Therefore, the delay means 3 and the addition means 4
This effect is removed by

That is, the characteristics of the loop are not changed from the conventional write clock generation device, and only the followability of the generated write clock is improved by the amount of phase modulation.

FIG. 2 is a signal waveform diagram for explaining the functions of the delay means 3 and the addition means 4. In FIG. 2, the horizontal axis represents time, and the vertical axis represents time axis fluctuations. Waveform a shown by a solid line represents the time axis error of the video signal input manually at point A in FIG. In contrast, a conventional time axis correction device using a PLL, that is, the delay means 3 in FIG.
, the time axis fluctuation of the write clock generated by the write clock generation device without the addition means 4 and the phase modulation means 6 is already shown with a broken line. Now, phase comparison is performed by the phase comparison means 2 at time tl, and the phase error (a
1-bl) is detected. The output of delay means 3 is O
Then, this phase error passes through the adding means 4 as it is,
On the other hand, the variable frequency oscillation means 5 is controlled through a loop filter, and its time axis fluctuation follows the dashed line. At the same time, the phase error is also given to the phase modulation means, (al-bl)
Since the phase modulation corresponding to the amount of time is added to the output of the variable frequency oscillation means 5, the time axis fluctuation of the write clock after the phase modulation follows the dotted line C.

After one line of the input video signal, a new phase error is detected using the next horizontal synchronization signal at time t2, but this is different from the conventional write clock generator, and due to the influence of phase modulation (a2- c2). This essentially means that the loop gain has decreased, and if the phase error is used as is, the residual error of the loop will increase instead. However, at this time, since the delay means 3 outputs the phase modulation amount (al-bl) l line before, that is, (c2-b2), the output of the addition means 4 becomes (a2-b2), which is This is the same value as the conventional write clock generator. As a result, the loop gain no longer decreases, and the time axis fluctuation of the output of the variable frequency oscillation means 5 follows the broken line as in the conventional write clock generator, and the followability of the output write clock is improved by the amount of phase modulation. It becomes what it is.

Next, a write clock generating device of a time axis correction device according to another embodiment will be described with reference to the drawings. FIG. 3 is a block diagram of a write clock generating device of a time axis correction device according to another embodiment of the present invention. In Figure 3, 10
1 is the first adding means, 9 is the pulsing means, 11 is the second adding means, and the others are the same as in FIG. 1, and the first adding means IO
This also corresponds to the addition means 4 in FIG. Operationally, this embodiment is the same as the embodiment shown in FIG. 1, except for the part related to phase modulation. The pulsing means 9 generates a pulse having a pulse height corresponding to the signal supplied from the first adding means 10, for example. The second addition means 11 adds this pulse and the output of the loop filter 8 and supplies the result to the variable frequency oscillation means 5. FIG. 4 shows the response of the variable frequency oscillation means 5 at this time.

In FIG. 4, a represents a control signal applied to the variable frequency oscillation means 5, and b represents the phase of a write clock generated by the control signal. Variable frequency oscillation means 5
generates a write clock with a frequency proportional to the applied control signal, so the phase of the write clock is given by the integral of the control input signal. In other words, in Figure 4, the slope (2) is proportional to the value of the control signal shown in (1).
The phase of the write clock indicated by changes. Therefore, when the pulse superimposed on the control signal is input at time 3, the slope of the pulse period changes depending on the pulse height. As a result, the phase of the write clock changes in proportion to the product of the pulse height and pulse width before and after the pulse input. Therefore, by appropriately selecting the conversion gain of the input to the pulse height in the pulsing means 9, the write clock can be phase modulated to follow the time axis fluctuations that cannot be responded to by PLL. Since there is no particular need to provide phase modulation means, the configuration can also be simplified.

As is clear from the operation, the pulsing means 9 not only converts the input signal value into a pulse height as described above, but also converts it into a pulse width, which is the product of the height and width of the generated pulse. That is, if the pulse area corresponds to the input signal, exactly the same effect can be obtained.

FIG. 5 is a circuit diagram showing a specific example of a configuration in which the pulsing means 9, second addition means 11, and variable frequency oscillation means 5 shown in FIG. 3 are realized by digital circuits. In FIG. 5, 51 is an adder, 52 is a register, 53 is a clock generation circuit, 91 is an R-3 (set/reset) flip-flop, 92 is an AND gate 5, and 93 is a multiplier that provides a constant cane. Further, portions corresponding to the variable frequency oscillation means 5 and the pulsing means 9 are shown surrounded by broken lines.

The operation of this circuit will be explained below with reference to the signal waveform diagram in FIG. However, E, FG, H, 1 in Figure 5
The signals at the points are shown at e, f, g, and hi in FIG. 6, and in particular, i shows the digital code converted into an analog value. The variable frequency oscillation means 5 is composed of an integrating circuit 1 consisting of a register 52 and an adder 51, and integrates the input value at the rate of the clock signal g from the clock generating circuit 53. Since the register repeatedly overflows at intervals proportional to the input value, its output becomes a sawtooth wave with a frequency proportional to the input value. On the other hand, the pulse input to the input terminal TR at time t4 is a signal phase-synchronized with the horizontal synchronization signal of the video signal, and indicates the timing at which the sample value of the phase error in the 5-phase comparator 2 is updated.

This pulse sets the R-S set reset flip-flop 91 and opens the gate 92. The output signal of the first addition means 10 is inputted to the input terminal F, and the output of the loop filter 8 is inputted to the input terminal J. These are added in the second addition means 11, and the variable frequency oscillation means 5 given to. Thereafter, when a new lock pulse is output from the clock generation circuit 53, the signal input to the variable frequency oscillation means 5 is incorporated into the integration, and at the same time, the R-S set reset flip-flop 91 is inverted and the gate 92 is activated. Close.

That is, the output of the loop filter 8 is normally supplied to the variable frequency oscillation means 5, but every time a new error signal is obtained from the phase comparison means 2 in conjunction with the horizontal synchronization signal of the input video signal, the first addition means The output of 10 is superimposed on the output of the loop filter 8 and taken into the integration of the variable frequency oscillation means 5 only once. In this case, the pulsing means 9 can be equivalently regarded as generating an impulse proportional to the output value of the first adding means 10 and supplying it to the integrating circuit of the variable frequency oscillation means 5. can. As a result, the phase of the output of the variable frequency oscillation means 5 is shifted according to the value given from the input terminal r. Therefore, by appropriately selecting the gain in the multiplier 93, the residual error detected by the phase comparator 2 can be corrected in the same way as in the embodiment shown in FIG.

Incidentally, a signal indicating tying synchronized with the horizontal synchronizing signal applied to the terminals in FIG. 5 can be easily obtained by decoding the output of the counter included in the frequency dividing means 7.

Alternatively, it is also possible to detect the horizontal synchronization signal of the input video signal and generate it separately based on this. Similarly, the frequency dividing means 7 can also have the function of the clock generation circuit 53.

Of course, FIG. 5 is just an example, and the circuit configuration is not limited to this.

Further, here, a case has been described in which the pulsing means 9 converts the input signal into a pulse having a pulse height corresponding to the input signal, but the same effect can be obtained when converting into a pulse width.

Further, in each embodiment, an example was shown in which the phase comparison means 2 compares the phase of the horizontal synchronization signal, but the configuration is not limited to the above as long as the phase error between the video signal and the write clock is detected. For example, it may be possible to use a burst signal for phase comparison, to use both a burst signal and a horizontal synchronization signal, or to switch between them. In that case, the frequency division ratio of the frequency dividing means 7 is also changed accordingly.

Effects of the Invention Since the present invention is configured as described above, it produces the effects described below.

By including a feedforward system using phase modulation in the conventional write clock generator using a PLL system and applying phase modulation to the write clock while removing the influence of the feedforward system on the PLL, it is possible to generate high frequencies that cannot be tracked by the PLL alone. It is possible to generate a write clock that also follows time axis fluctuations. Further, since the phase comparison is performed after the video signal is digitized, it is easy to digitize the circuit and implement it into an LSI, thereby achieving lower costs and higher reliability.

By directly applying phase modulation to the variable frequency oscillation means using the pulsing means, a feedforward system can be constructed without providing a special phase modulation means, so in addition to the above effects, the circuit can be further simplified. Cost reduction can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a write clock generator of a time axis correction device according to the present invention, FIG. 2 is a signal waveform diagram explaining the operation of FIG. 1, and FIG. 3 is a time axis correction according to the present invention. A block diagram of another embodiment of the write clock generating device of the device, FIG. 4 is a signal waveform diagram explaining the operation of FIG. 3, FIG. 5 is a circuit diagram of the main part of FIG. 3, and FIG. FIG. 5 is a signal waveform diagram explaining the operation, and FIG. 7 is a block diagram of a write clock generator of a conventional time axis correction device. 1...Digitization means, 2...Phase comparison means, 3...Delay means, 4...Addition means, 5...Variable Frequency oscillation means, 6...
...Phase modulation means, 7... Frequency division means, 8...
...Loop filter, 9...Pulsing means, 10...First addition means, 11...
Second addition means.

Claims (2)

[Claims] (1) variable frequency oscillation means that generates a write clock signal with a frequency according to a control input; a phase modulation means that applies phase modulation to the output signal of the variable frequency oscillation means and outputs it as a write clock; a digitizing means for digitizing the video signal based on the frequency of the write clock, a frequency dividing means for dividing the frequency of the write clock, and an output of the frequency dividing means and a phase of a burst signal or a horizontal synchronization signal of the digitized video signal. a phase comparison means for comparing and outputting a phase error signal; a delay means having a delay time equivalent to one line of the video signal; an output of the delay means and the phase error signal are added together, and the addition result is supplied to the delay means. and a loop filter that corrects the frequency and phase characteristics of the output of the addition means, and the variable frequency oscillation means is controlled based on the output of the loop filter to add a phase characteristic to the digitized video signal. A write clock generating device for a time axis correction device, wherein the clock is synchronized and the phase modulation means performs phase modulation according to the output of the addition means. (2) variable frequency oscillation means for generating a write clock signal with a frequency according to a control input; digitization means for digitizing a video signal based on the write clock; and frequency division means for dividing the frequency of the write clock; ,
a phase comparison means for comparing the output of the frequency dividing means and the phase of the burst signal or horizontal synchronization signal of the digitized video signal and outputting a phase error signal;
a delay means having a delay time equivalent to a line; a first addition means for adding the output of the delay means and the phase error signal and supplying the addition result to the delay means; and an output of the first addition means; a loop filter for correcting frequency phase characteristics; a pulsing means for converting the output of the first adding means into a pulse having a pulse width or pulse height according to the value thereof; and an output of the first adding means. and a second addition means for adding the output of the pulsing means, and the variable frequency oscillation means is controlled based on the output of the second addition means and phase-locked to the video signal. A writing clock generation device for a time axis correction device.