JPH0338711A - Memory back-up system - Google Patents

Abstract

PURPOSE:To attain the effective use of a back-up battery power supply and at the same time to prevent the overdischarge by detecting the voltage of a battery of a back-up power supply and controlling the supply of power to plural divided memory blocks. CONSTITUTION:The detection voltage levels V1 and V2 of the voltage detecting circuits 4 and 6 of a battery 15 are increased with reduction of the DC output Vm of a power unit 11. Then the detection signals Da and Db of both circuits 4 and 6 are set at high levels. Therefore the transistors TR Q2 and Q4 are turned on and then the TR Q1 and Q3 are also turned on. Then the power of the battery 15 is supplied to the memory blocks 13a and 13b. When the battery power supply is carried on and the voltage of the battery 15 drops down to the level V2 of the circuit 6, the signal Db of the circuit 6 is set at a low level. Thus, the supply of power is stopped to the block 13b. As a result, the overdischarge is prevented and at the same time a back-up period can be increased.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a memory backup method, and in particular, to extending the backup time of memory (volatile memory) and preventing over-discharge of a battery during power cut-off or power outage. The present invention relates to a memory backup method suitable for.

[Conventional technology]

Conventionally, various backup methods have been proposed for volatile memory to provide power backup in case of power cut-off or power outage. A typical example is a system that detects a voltage drop in the DC power source and switches to the battery power source when the voltage falls below a predetermined voltage value, as described in Japanese Patent Application Laid-open No. 6F-3221. There is. Also,
In order to prevent over-discharging of the battery, some devices are equipped with a timer and stop supplying power from the battery after a certain period of time.

[Problem to be solved by the invention]

By the way, the memory power backup method mentioned above is
It is assumed that the backup battery is always well charged, and the system detects a drop in the voltage of the main DC power source and switches to the battery power source if the voltage falls below a predetermined voltage value. . Therefore, if the battery is not properly charged, or if the power is cut off intermittently and the battery is discharged,
There is a problem that a sufficient power backup function may not be provided.

Further, such a memory backup method uniformly supplies power to the memory, and there is a problem in that no consideration is given to minimizing battery consumption and maximizing backup time. That is, no consideration is given to detecting the voltage of the battery and stopping power supply to the memory when the voltage falls below a predetermined voltage to prevent overdischarge.

The present invention has been made to solve the above problems.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory back method that detects battery voltage and stops power supply to a memory based on the result to prevent over-discharge and extend backup time.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

In order to achieve the above object, the present invention includes a power supply device that obtains a DC output from a commercial power supply, a battery to which the DC output of the power supply device is connected via a charging circuit, and a battery that detects the voltage of the battery and sets a predetermined voltage. A voltage detection circuit that generates a detection signal when the voltage exceeds a voltage value, a switch circuit that switches the memory power supply to the DC output of the power supply device or the battery, and a switch circuit that switches the power supply to the memory to the DC output of the power supply device or the battery when the DC output of the power supply device is at a normal voltage. The present invention is characterized by comprising power supply control means for supplying power to the memory by means of a battery while a detection signal of the voltage detection circuit is being generated when the DC output decreases.

[Effect]

According to the above means, a power supply device that obtains DC output from a commercial power supply, a battery to which the DC output of the power supply device is connected via a charging circuit, and a power supply detection circuit that detects the voltage of the battery are provided. The voltage detection circuit detects the voltage of the battery and generates a detection signal when the voltage is equal to or higher than a predetermined voltage value. When the DC output of the power supply device is at a normal voltage, the power supply control means supplies power to the memory using the DC output, and when the DC output decreases, while the detection signal of the voltage detection circuit is being generated, Power is supplied to the memory by a battery. In other words, when the DC output from the power supply device decreases, the power supply to the memory is switched to the battery side using a switch circuit, but the conditions for supplying battery power at this time are determined by the voltage detection circuit that detects the battery voltage. It is assumed that the detection signal is being output.

Therefore, when the voltage detection circuit no longer outputs a detection signal, the power supply from the battery to the memory is stopped.
Eliminate unnecessary discharge from the battery. This is particularly effective when the power supply to the memory is divided into a plurality of memory blocks and supplied to each of them. By stopping the supply of battery power to some memories, surplus power is created for supplying power to other memories, making it possible to continue backing up battery power to other memories for a long period of time. .

7. That is, the memory is divided into a plurality of blocks, a power supply order is set for each block, and a plurality of voltage detection circuits are provided corresponding to the plurality of blocks. The plurality of voltage detection circuits output a detection signal to each one as the battery voltage decreases, and sequentially stop power supply to each memory.

Since the data stored in the memory has different degrees of importance depending on its contents, the memory is divided into a plurality of blocks and stored according to the degree of importance of the data. The voltage detection circuit has a voltage level set to control the supply of battery power to the divided memory (according to the importance of the data).
Detects the battery voltage and uses the detection output of the voltage detection circuit.

Stops supplying battery power to the memory.

As a result, as the battery voltage decreases, power supply is stopped sequentially starting from the memory where data of low importance is stored, stopping unnecessary discharge and reducing power consumption. Therefore, it is possible to extend the backup time of the memory block 8- in which highly important data is stored, and furthermore, the battery voltage is lowered to below the required voltage to prevent memory data from volatilizing. In this case, power supply to all memories is stopped, preventing unnecessary over-discharge.

(Example) Hereinafter, an example of the present invention will be specifically described using the drawings.

FIG. 1 is a block diagram showing the circuit configuration of a main part of a power supply control circuit that performs a memory backup method according to an embodiment of the present invention. In FIG. 1, 11 is a power supply device, 12
is the battery charging circuit.

13 is a memory, and the memory 13 includes a first memory block (memory A) 13a and a second memory block (memory A).
The memory B) 13b is divided and power is supplied to each of them through separate power supply lines. Further, 14a and 14b are battery power supply control circuits, and 15 is a battery.

The power supply device 11 converts AC power input from a commercial power source into DC and obtains DC output Vm. The DC output Vm of the power supply device 11 is connected to the battery charging circuit 1 via the diode D1.
2. At the same time, the DC output Vm is supplied to the first memory 13a via the diode D2, and is supplied to the second memory 13b via the diode D3. The output of the battery charging circuit 12 is supplied to a battery 15 connected between the battery 1 and ground.
Charge 5.

The battery 15 is connected to battery power supply control circuits 14a and 14b to supply battery power to the memory.

In the battery power supply control circuit 14a, the battery 15
The + side of the transistor Q1 is connected to the emitter of a PNP transistor Q1 that functions as a switch circuit, and the collector of the transistor Q1 is connected to the first memory block 13a. In order to control the switching operation of the transistor Q1, an NPN transistor Q2 is connected to the base of the transistor Q1 via a resistor R1.
The output signal of the voltage detection circuit 4 is connected via the resistor R2.

As the voltage detection circuit 4, for example, a commercially available voltage monitoring circuit with high voltage accuracy and hysteresis characteristics of the detected voltage can be used.
C is used. This voltage detection circuit 4 is connected to a battery 15.
The voltage value to be detected is determined by the variable resistor VR connected between the + side of the battery 15 and the ground.
I is set to a predetermined value.

In the battery power supply control circuit 14b, a similar circuit configuration connects the + side of the battery 15 to the emitter of a PNP transistor Q3 that functions as a switch circuit.
The collector of transistor Q3 is connected to the second memory block 1
3b. In order to control the switching operation of the transistor Q3, a transistor Q4 (NPN) is connected to the bases of the transistors 1 to Q3 through a resistor R3, and a voltage detection circuit 6 is connected to the base of the transistor Q4 through a resistor R4. Output signal is connected. The voltage detection circuit 6 is connected between the + side of the battery 15 and ground, and the voltage value to be detected is set to a predetermined value by a variable resistor VH2 connected between the + side of the battery 15 and the ground. Furthermore, in this battery power supply control circuit 14b11, the base of the transistor Q4 is connected to a P
The emitter of NPh transistor Q5 is connected, and the collector of transistor Q5 is connected to ground. Although not shown, the base of the transistor Q5 is connected via a resistor R5 to a POFF signal that becomes low level when a power-off operation is performed.

As described above, the memory 13 is divided into the first memory block 13a and the second memory block 13b, each of which is supplied with power through a separate power supply line. The power consumption ratio of the memory block 13a and the second memory block 13b is 1:
The memory is divided into memory blocks at a ratio of about 5 to 1:10, and power is supplied. The detection voltage of the voltage detection circuits 4 and 6 is the voltage when the battery 15 is well charged. , the detection voltage of the voltage detection circuit 4 is 1, the detection voltage of the voltage detection circuit 6 is v2, and the backup limit voltage of the memory is 2, then the following relationship is set.

12-v,>v2>v,=vL Next, the circuit operation of the power supply control circuit shown in FIG. 1 will be explained.

FIG. 2 is a timing chart of each part explaining the circuit operation of the power supply control circuit. FIG. 2 shows the timing relationships between battery voltage, backup time, and control signals.

Referring to FIG. 2, during power-on, the power supply 11 outputs a DC output Vm, and the first memory block 13
Power is supplied to a via the diode D2, and
Power is supplied to the second memory block 13b via a diode D3. Generally, the voltage of the battery 15 is set lower than the output voltage Vm of the power supply device 11 because the memory generally requires a low voltage during standby during operation.

Therefore, while the DC output is being supplied from the power supply 11, a reverse voltage is applied to the transistor Ql and the transistor Q3 (reverse biased), and the battery 15 supplies the first memory block 13a and the second memory block 13a to the transistor Q3.
No power is supplied to the memory block 13b. Also, during this period, the DC output Vm of the power supply device 11 is applied to the charging circuit 12 via the diode D1, and the battery 15 is charged by the output voltage of the charging circuit 12.

In this state, if the commercial AC power supply is turned off due to a power outage or the like, the DC output Vm of the power supply device 11 decreases, so the power supply is switched to the battery 15. The power supply to the first memory block 13a is switched by the switching action of the diode D2 and the transistor Q1. That is, in this case, the voltage of the battery 15 is ■.

is higher than the detection voltage Vl of the voltage detection circuit 4, and the detection signal Da of the voltage detection circuit 4 is at a high level, so the transistor Q2 is turned on, the transistor Q1 is turned on, and the power of the battery 15 is transferred to the memory. Block 13
supplied to a. Similarly, the detection signal D of the voltage detection circuit 6
b is also at a high level due to the above-mentioned conditions, transistor Q4 is turned on, transistor Q3 is turned on, and power from battery 15 is supplied to memory block 13b. Note that in this case, the DC output Vm of the power supply device 11 is in a reduced state, but since the operation is performed during power-on, the power-off signal POFF is at a high level, and the transistor Q5 is turned off. . Therefore, transistor Q4 and transistor Q3 are turned on, and power from battery 15 is supplied to memory block 13b.

In this way, when the commercial AC power supply is turned off due to a power outage, etc., the DC output Vm of the power supply device 11 decreases, so that
Although the power supply is switched to the battery 15, the power outage continues and the battery continues to supply power, and as shown in FIG. 2, after t1 hours, the voltage of the battery 15 becomes ■. When the voltage decreases from V2 to the detection voltage V2 of the voltage detection circuit 6,
The detection signal Db of the voltage detection circuit 6 becomes low level. As a result, transistor Q4 is turned off, transistor Q3 is turned off, and power supply to memory block 13b is stopped. At this time, the load on the battery 15 becomes lighter, so the voltage of the battery 15 rises slightly, but since the voltage detection circuit 6 has hysteresis characteristics, the detection signal Da does not change to high level again. .

If the power outage continues and the battery power supply continues, the voltage of the battery 15 will reach the detection voltage Vl of the voltage detection circuit 4 after t2 hours. At this point, the detection signal Da of the voltage detection circuit 4 becomes low level, the transistor Q2 and the transistor Ql are turned off, and the battery power supply to the first memory block 13a is also stopped.

Next, a case where the power is turned off due to normal operation will be explained. In this case, the power-off signal POFF becomes low level. Therefore, transistor Q5 is turned on, the base voltage of transistor Q4 is pulled to a low level, transistor Q4 is turned off, and transistor Q3 is also turned off. Therefore, in this case, power from the battery 15 is not supplied to the second memory block 13b. However, in the first memory block 13a,
In the same manner as in the case of the power outage described above, battery power supply is performed by the same operation.

=16 As explained above, since the memory backup operation of this embodiment is performed, for example, the first memory block 13a of the memory 13 is used as a memory for storing system management data necessary when restarting the system. In addition, if the second memory block 13b is used as a memory for storing user data to be transferred to an external storage device such as a floppy disk when the power is turned off, it is possible to save power when there is no time to save data to the external storage device. In the event of a power outage while the device is on, system management data and user data can be backed up. Note that since the user data is stored in the second memory block 13b, the guaranteed backup time is short, but the backup time for system management data, which is highly important data, can be increased accordingly. can. Furthermore, if a power-off operation is performed after data has been saved to an external storage device, the second memory block 13b will not receive battery power, so only the system management data will be backed up for a long time. This makes it possible to effectively utilize the limited electric power of the bath battery.

Furthermore, in the memory backup by the power supply control circuit of this embodiment, when performing memory backup for each memory block divided into a plurality of blocks, the data stored in each memory block is Therefore, the backup time may be changed. In this case, for example, by performing a power-off operation, the central processing unit of the system determines which memory blocks are in use before the power is turned off, and when the power is turned off, only the memory blocks in use are supplied with backup power.

Next, other embodiments and modifications of the present invention will be described.

FIG. 3 is a block diagram showing the configuration of main parts of a data processing system using a power supply control circuit according to another embodiment of the present invention. In FIG. 3, 30 is a power supply unit, 31a and 31b are batteries, 32 is a battery power supply control unit,
33 is a memory element, 34 is a central processing unit, 35 is a power control processing section, 36 is a display section, and 37 is a keyboard. The power supply unit 30 converts AC power input from a commercial power source into DC and supplies DC output power. Battery power supply control section 3
2 is a power supply unit 3 for the memory element 33 during normal operation.
0, and in the event of a power outage, battery power is supplied from the batteries 3, 1a and 31b.

Batteries 31a and 3 for battery power supply
1b is provided with a plurality of systems, each of which is used individually, and both of which are used while being switched to each other.

One may be used as a main system, and the other may be used as a backup system. The memory element 33 is divided into a plurality of memory blocks, each of which is provided with a power supply line. The battery power supply control unit 32 controls power supply to each memory block. Central processing unit 3
The power supply control processing unit 35 in No. 4 performs control processing for the battery power supply control unit 32 in response to a power-on operation or power-off operation instruction from the keyboard 37, and also displays a message regarding the power supply control processing on the display unit 36.
Displays warnings to the operator.

In other words, if battery power is supplied during a power outage, and the power supply to a specific memory is stopped due to a drop in battery voltage, the memory power supply information to that effect is stored in a backup memory, etc., and then used again. At startup, the memory power supply information is sent to the power supply control processing unit 3 of the central processing unit 34.
5 reads out the message and outputs the message to the display section 36.

Furthermore, when a normal power-off operation is performed using the keyboard 37, the power supply control processing unit 35 detects the battery voltage and detects the battery voltage before performing power-off control under control from the central processing unit. If it has decreased, a message to that effect is displayed on the display section 36 to warn the operator.

FIG. 4 is a block diagram illustrating in detail the structure of the memory element in FIG. 3. As shown in FIG. 4, the memory element 33 is divided into a plurality of memory blocks A''n, and each memory block is provided with a power line A-n that can individually control power supply. With such an individual power supply line for each memory block, each memory block can be individually backed up for each divided memory block.
Furthermore, the memory elements are individually usable in correspondence with each memory block.

FIG. 5 is a flowchart illustrating an example of power control processing by a power control processing section that performs battery power supply control. Fifth
This will be explained with reference to the figures. In this power supply control process, for example, in step 51, when the operator performs a power-off operation using the keyboard, in the next step 52, a process for determining the memory block in use is performed, and only for the memory block in use, A battery connection instruction is sent to the battery power supply control section. And step 5
4, a power-off operation is performed according to instructions from the central processing unit. As a result, only the memory blocks in use are backed up by battery power supply, making it possible to effectively utilize backup battery power and prevent over-discharge.

FIG. 6 is a flowchart showing another example of the power control processing of the power control processing section that performs battery power supply control.

This will be explained with reference to FIG. In the power supply control process of this example, first, in step 61, the operator performs a power-off operation using the keyboard, and in the next step 62, the battery voltage is detected. Then, in a determination step of step 63, it is determined whether the detected battery voltage is OK. If the battery voltage does not indicate a sufficient charging potential, the process proceeds to step 64, where a message indicating that the power will not be turned off for charging is displayed, and the process returns to step 62, where the battery voltage detection in step 62 is repeated. Further, in step 63, if the detected battery voltage indicates a sufficient charging potential and the battery voltage is OK, step 6
5, a series of termination processes including a power-off operation are performed, and in the next step 66, the power is turned off.

In this manner, when a power-off operation is performed, the battery voltage is checked and appropriate power control processing is performed accordingly.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As explained above, according to the memory backup method of the present invention, the voltage of the battery of the backup power source is detected and the power supply to the plurality of divided memory blocks is controlled, so the backup battery power source is effectively used. It is possible to prevent over-discharge. Furthermore, since the memory is divided into multiple blocks and the memory blocks storing highly important data are backed up preferentially, the backup time for important data can be longer than when the entire memory is backed up.

[Brief explanation of drawings]

1 is a block diagram showing the circuit configuration of the main parts of a power supply control circuit that performs a memory backup method according to an embodiment of the present invention. FIG. 2 is a block diagram showing the circuit operation of the power supply control circuit. 3 Timings of each part 3 is a block diagram showing the configuration of main parts of a data processing system using a power supply control circuit according to another embodiment of the present invention, and FIG. 4 shows a detailed structure of the memory element in FIG. 3. FIG. 5 is a flowchart showing an example of the power control processing of the power supply control processing section that performs batch power supply control, and FIG. 6 is a flowchart of the power supply control processing of the power supply control processing section that performs batch power supply control. It is a flowchart which shows another example. In the figure, 4, 6... voltage detection circuit, 11... power supply device, 12... battery charging circuit, 13... memory,
13a, first memory block, 13b, second memory block, 14a, 14b, battery power supply control circuit, 15° 31a, 31b, battery, 30, power supply unit, 32, battery Power supply control unit, 3
3...Memory element, 34...Central processing unit, 35.
...Power control processing unit, 36...Display unit, 37...Keyboard. 24- Yasa 5 Kokusaku 6th

Claims (1)

[Claims] 1. A power supply device that obtains DC output from a commercial power supply, a battery to which the DC output of the power supply device is connected via a charging circuit, and a voltage of the battery that is determined to be at least a predetermined voltage value. A voltage detection circuit that sometimes generates a detection signal, a switch circuit that switches the memory power supply to the DC output of the power supply device or the battery, and when the DC output of the power supply device is at a normal voltage, power is supplied to the memory using the DC output. 1. A memory backup system comprising: power supply control means for supplying power to the memory using a battery while the detection signal of the voltage detection circuit is being generated when the DC output decreases. 2. The memory backup method according to claim 1, wherein the memory is divided into a plurality of blocks, and the power supply control means individually controls power supply to each memory block. 3. In the memory backup method according to claim 2, a power supply order is predetermined for each memory block divided into a plurality of blocks, and the power supply order is determined in advance for each memory block divided into a plurality of blocks, and the power supply order is sequentially applied starting from the lowest power supply order according to the detected voltage of the battery. A memory backup method characterized by comprising a battery power supply control means for stopping power supply. 4. In the memory backup method according to claim 1,
A memory backup method characterized by having a plurality of battery units, and supplying power to the memory by sequentially switching the batteries in each unit. 5. In the memory backup method according to claim 3,
When the power supply to a specific memory is stopped due to a drop in battery voltage, a memory circuit is provided to store memory power supply information to that effect, and a means is provided to transmit the memory power supply information of the memory circuit to the central processing unit upon restart. A memory backup method characterized by: 6. A power supply device that obtains DC output from a commercial power supply, a battery to which the DC output of the power supply device is connected via a charging circuit, and detects the voltage of the battery, and generates a detection signal when the voltage is above a predetermined voltage value. A voltage detection circuit that switches the memory power supply to the DC output of the power supply device or the battery, and a switch circuit that switches the power supply to the memory to the DC output of the power supply device or the battery. In this case, while the detection signal of the voltage detection circuit is being generated, the memory backup method is equipped with a power supply control means that supplies power to the memory using a battery, and if a normal power-off operation is performed, the central Before performing power-off control under control from the processing device, the battery voltage is detected, and if the battery voltage has decreased, a message to that effect is displayed to alert the operator. Memory backup method. 7. By the memory backup method according to claim 2,
A memory element that divides memory into multiple blocks and enables memory backup for each block of each memory, wherein the memory element can be used by dividing the inside of the memory into multiple blocks, and each block A memory element that is provided with a power supply line that can individually control power supply. 8. In the memory backup method according to claim 2, when memory backup is performed for each memory block divided into a plurality of blocks, the memory block in use is transferred to the central processing unit by a power-off operation before power-off. A memory backup method that is characterized by determining the power and supplying power by backing up only the memory blocks that are in use when the power is turned off.