JPH0334577A - Nonvolatile semiconductor storage device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enlarge the coupling capacity between a floating gate and a control gate so as to realize high integration by providing a trench at the side face of the floating gate, and forming a second gate insulating film at the inner face of the trench as well as the side face, and arranging a control gate in opposition to the topside, the side face, and the trench inner face of the floating gate. CONSTITUTION:A floating gate 5 is processed in fin shape, with a trench 10 cut at the whole periphery of the side face. A second gate insulating film 6 is formed all over the topside and the side face of the floating gate 5 and the inner face of the trench 10. A control gate 7 is so formed as to not only oppose the topside of this floating gate 5 but also oppose the side face and the inner face of the trench 10 formed here. N<+>-type diffusion layers 8 and 9 to become a drain and a source are formed in a substrate with these gate regions in between. The floating gates 5 are independent with every memory cell, and the control gates 7 are arranged continuously in common to memory cells usually in one direction thereby constituting a word line.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a nonvolatile semiconductor memory device using a rewritable memory cell having a floating gate and a control gate, and a method for manufacturing the same.

(Prior Art) As a nonvolatile semiconductor memory device, one using a memory cell having a MOS (MOS) transistor structure having a floating gate and a control gate is known. Among them, the one that can be electrically rewritten is known as EEFROM.

FIG. 9 shows the structure of an FETMOS type memory cell, which is one of the conventional EEFROM memory cells. (a)
are plan views, and (b) and (e) are respectively A of (a).
-A' and BB' sectional views. An element isolation insulating film 32 is formed on a p-type silicon substrate 31, and a p + -type layer 33 is formed thereunder as a channel stopper. A thin first gate insulating film 34 through which a tunnel current can flow is formed over the entire channel region on such an element-isolated substrate, a floating gate 35 is formed on this, and a second gate insulating film 36 is further formed on this. A control gate 37 is formed through the gate. The edges of the floating gate 35 and the control gate 37 are aligned by sequentially etching them using the same mask in the channel length direction. Using these laminated gates as a mask, impurity ions are implanted to form n+ type layers 38 and 39 which become sources and drains.

This FETMO3 type memory cell has a control gate.

Since the floating gate, source, and drain are formed in a self-aligned manner, miniaturization is possible, but there are the following problems.

FIG. 110 shows the capacitance relationship of the FETMOS type memory cell. As shown in the figure, this memory cell mainly has a capacitance CGG between the control gate and the floating gate, a capacitance HkCcs between the floating gate and the substrate, and a capacitance cos between the floating gate and the source and drain.

Now, consider the case where a high positive voltage is applied to the control gate in order to inject electrons from the substrate into the floating gate.

For simplicity, assuming that the floating gate has no charge, the substrate is at zero potential, and the potential applied to the control gate is VCG, the floating gate potential vP6 is Vpc = Cca - Vcc/ (Cos + Cco + Ccc
). As is clear from this equation, the capacitive coupling ratio Ca
The larger the value of c/ (Cos + CCH + Ccc), the
The potential VPG of the floating gate becomes high. That is,
In order to efficiently write by reducing the potential VCO applied to the control gate, it is desirable to make the above-mentioned capacitance ratio as large as possible. However, in the miniaturized FETMOS type memory cells currently in practical use, the above-mentioned capacity ratio is about 1/2, and in order to write, a high voltage of about 20V must be applied to the control gate. is necessary. In order to increase the coupling capacitance between the floating gate and the control gate, the floating gate is usually patterned so that it partially extends onto the element isolation insulating film, as shown in FIGS. 9(a) and 9(b). be done. However, in order to integrate memory cells at a high density, it is not possible to extend the device isolation region that much, and therefore there is a limit to increasing the coupling capacitance between the floating gate and the control gate using this method. Since a high voltage of 20V is required for the control gate, a voltage of 20V or more is also required for the device isolation voltage and the device isolation voltage of the peripheral circuit.As a result, even if the memory cell is processed to sub-μm dimensions, the device The isolation region requires several micrometers, which hinders high integration of the memory array as a whole. Furthermore, since a high voltage of 20V is required, there is a problem in the reliability of peripheral circuits such as MOS (MOS) transistors and selection gates. Furthermore, EE
Regarding FROM, the power supply (5V) used for ultraviolet erasable EPROM, which has been widely used so far.

Although it would be desirable for users to have compatibility with 12.5V), this is not the case.

(Question 8 to be solved by the invention) As described above, the conventional FETMOS type memory cell is
High integration is difficult because high voltage is required for writing.
There were also problems with reliability.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile semiconductor memory device and a method for manufacturing the same that solves the zero problem by effectively increasing the coupling capacitance between the floating gate and the control gate.

[Structure of the Invention] (Means for Solving the Problems) A memory cell of a nonvolatile semiconductor memory device according to the present invention includes:
A floating gate formed on a semiconductor substrate via a first gate insulating film has a groove formed on its side surface, and a second gate insulating film is also formed on the upper surface, side surface, and inner surface of the floating gate, The control gate is characterized in that it is formed so as to face not only the top surface of the floating gate but also the side surfaces and the inner surface of the groove. The groove on the side surface of the floating gate may be formed over the entire circumference, or may be formed partially, for example, only on the side surface in the channel width direction of the cell.

In manufacturing such a nonvolatile semiconductor memory device, the method of the present invention first forms a laminate of a first layer polycrystalline silicon film and an insulating film on a substrate from which elements are isolated, with a first gate insulating film interposed therebetween. Then, the insulating film of this stacked structure is selectively etched to form a fine opening in the gate region. Then, a second polycrystalline silicon film is deposited to contact the first polycrystalline silicon film through this opening, and a mask covering the gate region is used to transfer the second polycrystalline silicon film to the first polycrystalline silicon film. The floating gate is selectively etched to form a floating gate. Then, the insulating film sandwiched between the first layer polycrystalline silicon film and the second layer polycrystalline silicon film exposed on the side surface of the floating gate is removed by etching, thereby forming a groove on the side surface of the floating gate. After that, a second gate insulating film is formed on the upper surface, side surfaces, and inner surface of the trench of the floating gate, and then a third layer polycrystalline silicon film is deposited and patterned to form a control gate.

Another method of the invention forms the floating gate and control gate in self-alignment. For this purpose, after forming a laminate of a first layer polycrystalline silicon film and an insulating film, first, a fine opening is made in the insulating film in the gate region, and then a second layer polycrystalline silicon film is deposited. A second layer is placed on the element isolation region.
It penetrates from the first layer polycrystalline silicon film to the first layer polycrystalline silicon film.

A striped floating gate isolation trench running in the channel length direction is formed. After removing the insulating film exposed in the floating gate isolation trench, the first polycrystalline silicon film and the second polycrystalline silicon film are removed.
A second gate insulating film is formed on the exposed surface of the layered polycrystalline silicon film. After that, a third polycrystalline silicon film is deposited, the gate region is covered with a mask running in stripes in the channel width direction, and this is used to etch from the third polycrystalline silicon film to the first polycrystalline silicon film. A control gate and a floating gate are formed separately.

(Function) According to the present invention, a groove is cut into the side surface of the floating gate, and the control gate is formed facing from the top surface of the floating gate to the side surface and also to the inner surface of the groove on the side surface. This can be achieved by increasing the coupling capacitance between the gates. As a result, the control potential applied to the control gate during writing or erasing can be lowered, and higher integration can be achieved by reducing the element isolation region.

Furthermore, reliability of the storage device including peripheral circuits can be improved. When configuring EEPROM, ultraviolet erase type EEF
It is also possible to achieve compatibility with the ROM in terms of power supply.

According to the method of the present invention, as a step of obtaining a floating gate with grooves formed on the side surfaces, a stacked body of a first layer polycrystalline silicon film and an insulating film is formed, fine openings are made in the insulating film, and a first layer is formed. A process is used in which a two-layer polycrystalline silicon film is deposited, and then etching is performed to penetrate from the second-layer polycrystalline silicon film to the first-layer polycrystalline silicon film, and the insulating film exposed on the side surfaces is etched away. . Therefore, the shape and depth of the groove on the side surface can be arbitrarily set with good controllability depending on the thickness of each layer and the dimensions of the opening formed in the insulating film. As a result, even if the floating gate has a small area, the coupling area between the control gate and the floating gate can be increased, and a memory cell having the above-mentioned excellent advantages can be obtained.

(Example) The present invention will be explained in detail below.

FIG. 1 shows the structure of an FETMOS type memory cell of an EEFROM according to an embodiment. (a) is a plan view, and (b) and (e) are respectively A- in (a).
They are A' and BB' sectional views. p-type silicon substrate 1
A thick element isolation insulating film 2 is formed in the element isolation region of
A p++ layer 3 is formed below as a channel stopper. A thin first gate insulating film 4 through which a tunnel current can flow is formed in the device-isolated substrate region, and a floating gate 5 is formed on this thin first gate insulating film 4. The floating gate 5 has a groove 10 cut into the entire circumference of its side surface and is processed into a fin shape. A second gate insulating film 6 is formed over the entire upper surface and side surfaces of the floating gate 5 and the inner surface of the groove 10 . The control gate 7 is formed not only to face the top surface of the floating gate 5 but also to face the side surface and the inner surface of the groove 10 formed here. There is a drain on the substrate across these gate regions.

An n+ type scattering layer 89 that serves as a source is formed. Although only one memory cell section is shown in the figure, a large number of such memory cells are arranged and formed to form a memory cell array. The floating gate 5 is independent for each memory cell, and the control gate 7 is normally disposed continuously in common with the memory cells in one direction to form a word line.

FIGS. 2(a) to 3(f) and 3(a) to 3(f) are cross sections corresponding to FIGS. 1(b) and 1(c), respectively, showing the manufacturing process of the memory cell of this example. It is a diagram.

The specific manufacturing process will be explained with reference to these figures.
First, an element isolation insulating film 2 is formed on a p-type silicon substrate 1 using the usual LOCOS method. A p++ layer 3 serving as a channel stopper is formed under the element isolation insulating film 2. After performing ion implantation into the channel portion of the thus element-isolated substrate, if necessary, a first gate insulating film 4 of about 50 to 100 layers is formed by thermal oxidation (FIG. 2(a)).

Figure 3(a)). Next, a first layer polycrystalline silicon film 51 of about 200 nl, which will become a part of the floating gate, is deposited on the entire surface, and after doping this with impurities such as phosphorus or arsenic, a silicon oxide film of about 100 na+ is deposited using the CVD method. An insulating film 11 is deposited (FIGS. 2(b) and 3).
Figure (b)).

Thereafter, the insulating film 11 is selectively etched using a PEP process and a reactive ion etching method to open a fine opening located in the gate region of the cell (Fig. 2 (C), Fig. 3 (C)). Two-layer polycrystalline silicon film 5 □ 400
The layer is deposited to a thickness of about nm, and this layer is also doped with impurities in the same manner as the first layer (FIGS. 2(d) and 3(d)). The second polycrystalline silicon film 52 contacts the first polycrystalline silicon film 51 through an opening made in the insulating film 11 .

Next, the second layer polycrystalline silicon film 52. Insulating film 11 below
, and the first layer polycrystalline silicon film 51 thereunder is patterned by a PEP process and reactive ion etching so as to remain in the gate region, thereby obtaining the floating gate 5. The insulating film 11 exposed on the side surface of the floating gate 5 is removed by etching using hummonium fluoride, and grooves 1 are formed on the side surface.
0 is formed (Fig. 2 (e), Fig. 3 (e)
)).

A second gate insulating film 6 is thus formed on the entire surface of the floating gate 5 with the groove 10 formed on the side surface. Then, a third layer polycrystalline silicon film is deposited and patterned to form the control gate 7. The second gate insulating film 6 is desirably a triple layer of an oxide film, a nitride film, and a monoxide film in consideration of withstand voltage. Specifically, for example, oxidation is performed for 30 minutes in a steam atmosphere at 950° C., a silicon nitride film of about 10 ns+ is deposited thereon by CVD, and then thermal oxidation is further performed for 30 minutes in a steam atmosphere at 950° C. If plasma CVD is used to deposit the polycrystalline silicon film, the control gate 7 is formed to wrap around the groove 10 on the side surface of the floating gate 5 and to face the upper surface, the side surface, and the inner surface of the groove 10 of the floating gate 5. Then, using these gates as a mask, impurity ions are implanted into the substrate to form drain and source diffusion layers 8.
9 (Fig. 2(f), Fig. 3(r)).These diffusion layers 8.9 are formed by patterning the floating gate 5 of Fig. 2(e), Fig. 3(e). It may be formed later.

Finally, although not shown, the unnecessary second gate insulating film is removed using the control gate 7 as a mask, and an interlayer insulating film is deposited on the entire surface by CVD, and then contact holes are opened to form metal wiring such as bit lines. Thus, an EEFROM memory cell array is completed.

According to this embodiment, the floating gate 5 is formed in the shape of a fin, and the control gate 7 is also embedded in the groove on the side surface of the floating gate 5. Therefore, compared to the conventional structure, the opposing area of the floating gate and the control gate becomes larger, and the coupling capacitance between them becomes larger.

Therefore, electrical rewriting can be performed by applying a lower voltage to the control gate than in the past, leading to higher integration and improved reliability of the memory cell.

Furthermore, with the method of this embodiment, it is possible to form a groove on the side surface of the floating gate in a relatively U1-intensive process with few PEP processes, and effectively realize a state where the coupling capacitance between the floating gate and the control gate is large. be able to.

Figure 4 (a) (b) (c) shows the EEFR of other embodiments.
FIG. 2 is a plan view showing a memory cell structure of an OM, and its AA' and BB' cross-sectional views. Portions corresponding to those in FIG. 1 are designated by the same reference numerals as in FIG. 1, and detailed description thereof will be omitted. As is clear from a comparison with FIG. 1, in this embodiment, the floating gate 5 has a groove 10 formed only on the side surface in the channel width direction of the cell. This structure is effective when the floating gate is patterned in the channel length direction at the same time as the control gate so that both are self-aligned.

Figures 5(a) to (f) and Figures 6(a) to (f)
2A and 2B are cross-sectional views showing the manufacturing process of the memory cell of this example.

To explain the manufacturing process of Kojimono, first, a first gate insulating film 4 is formed on a substrate from which elements have been isolated in the same manner as in the previous embodiment (FIGS. 5(a) and 6(a)). , a first layer polycrystalline silicon film 51 is deposited on the entire surface, and then an insulating layer 51 is deposited on the entire surface.
(Fig. 5 (b), Fig. 6 (b)). Next, the insulating film 11 is selectively etched to open an opening (Fig. 5 (C), Fig. 6 (C)). When the opening is at least longer than the gate length of the floating gate in the channel length direction,
For example, a continuous stripe pattern is formed across a plurality of memory cells. Next, a second layer of polycrystalline silicon Jlli5□ is deposited in the same manner as in the previous embodiment (FIG. 5(d)).

Figure 6(d)). Thereafter, using a mask having an opening above the element isolation region, the second polycrystalline silicon film 52, the insulating film 11, and the first polycrystalline silicon film 5I are selectively etched to form a floating gate isolation trench. The insulating film 11 exposed in this isolation groove is removed by etching with ammonium fluoride (FIGS. 5(e) and 6(e)). As a result, a state is obtained in which a full 10 is formed only on the side surface in the channel width direction of the floating gate, which will be separated and separated later.

Thereafter, as in the previous embodiment, a second gate insulator [6] is formed, and a third layer polycrystalline silicon film is deposited. Then, using a striped mask continuous in the channel width direction,
By selectively etching the layers from the third layer polycrystalline silicon film to the first layer polycrystalline silicon film, a control gate 7 that is continuous in the channel width direction and becomes a word line is self-aligned with the control gate 7 in the channel length direction for each cell. A floating gate 5 separated into two is obtained.

Finally, source and drain diffusion layers 8.9 are formed to complete the memory cell (FIG. 5 (), FIG. 6 (r)).

In this embodiment, in the steps of FIG. 5 (C) and FIG. 6 (C) in which openings are formed in the insulating film 11, it is not necessarily necessary to form the openings into continuous stripes across a plurality of cells. For example, each cell may have an independent opening. The size of the opening in the channel length direction is also arbitrary. In the embodiment, this opening is made larger than the channel length, and therefore, as shown in FIG. 6(C). As is clear from ~(f), no groove is formed on the side surface of the floating gate 5 in the channel length direction, but when an opening smaller than the channel length is opened, the channel of the floating gate 5 is formed as in the previous embodiment. Grooves are also formed in the longitudinal direction.In this case, a structure similar to that of the previous embodiment is obtained, with the only difference being the separation process in the channel direction of the floating gate.

This embodiment also provides the same effects as the previous embodiment.

In the above embodiment, only one groove is provided on the side surface of the floating gate, but a plurality of grooves may be provided.

7(a) (b)) are cross-sectional views showing the memory cell structure of such an embodiment, and FIG. 1(b) (C
). Again, parts corresponding to those in the previous embodiment are given the same reference numerals. In this embodiment, two grooves 10 are provided on the side surface of the floating gate 5. It is possible to form a larger number of trenches, thereby increasing the coupling capacitance between the control gate and the floating gate.

The EEFROM according to the present invention can be of the NOR type, in which a plurality of memory cells connected to a word line are connected to different bit lines, as well as a NAND type, in which a plurality of memory cells are connected in series and connected to the bit line. It can also be applied in the case of

FIG. 8 shows a cross-sectional structure of one NAND cell portion when the present invention is applied to a NAND type EEFROM. Here, eight memory cell materials 1 to M8 are connected in series with adjacent ones sharing the source and drain to form one NAND.
An example of how cells are configured is shown. Each memory cell is of the same structure as obtained by the embodiment of FIG. 1, for example.

Selection gates 21 and 22 are provided at both ends of the NAND cell, and n+ diffusion layers 23 and 24, which become the drain and source of the NAND cell, are formed outside the selection gates. The whole is C
It is covered with a VD insulating film 25, a contact hole is opened in this, and a bit line 26 made of Ajl is arranged.

The present invention is not limited to the embodiments described above, and can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, it is possible to effectively increase the coupling capacitance between the floating gate and the control gate even in a fine structure, and to lower the potential applied to the control gate during rewriting. This makes it possible to obtain a nonvolatile semiconductor memory device that is highly integrated and has improved reliability.

[Brief explanation of drawings]

FIGS. 1(a), (b), and (c) are a plan view and a cross-sectional view showing the memory cell structure of an EEPROM according to an embodiment of the present invention, and FIGS. 2(a) to (f) are specific manufacturing steps thereof. FIGS. 3(a) to 3(r) are sectional views corresponding to FIG. 1(e), which also shows the specific manufacturing process, and FIG. 4( a) (
b) (c) is a plan view and a cross-sectional view showing the memory cell structure of an EEFROM according to another embodiment, and FIGS. 5(a) to (f) are FIG. Corresponding sectional views, FIGS. 6(a) to (f) are sectional views corresponding to FIG. 4(e), which also shows the specific manufacturing process, and FIG. 7(a) (
b) is a sectional view showing a memory cell structure of an EEFROM according to another embodiment, FIG. a), (b), and (c) are plan views and cross-sectional views showing the memory cell structure of a conventional EEFROM, and FIG. 10 is a diagram showing the capacitance relationship for explaining the problems of the conventional memory cell. 1...p-type silicon substrate, 2...element isolation insulating film,
3...p+ type layer, 4...first gate insulating film, 5...
・Floating gate, 5I...first layer polycrystalline silicon film, 5
2... Second layer polycrystalline silicon film, 6... Second gate insulating film, 7... Control gate, 8.9... N+ type scattering layer 10... Groove, 11...・Insulating film.

Claims (5)

[Claims] (1) A floating gate is formed on a semiconductor substrate with a first gate insulating film interposed therebetween, and a control gate is laminated on top of this floating gate with a second gate insulating film interposed therebetween. In a nonvolatile semiconductor memory device in which memory cells are integrated and are electrically rewritten by sending and receiving,
The floating gate has a groove on a side surface, a second gate insulating film is also formed on the side surface and the inner surface of the groove, and the control gate is disposed to face the upper surface, the side surface and the inner surface of the groove of the floating gate. A nonvolatile semiconductor memory device characterized by: (2) The nonvolatile semiconductor memory device according to claim 1, wherein the groove on the side surface of the floating gate is formed over the entire circumference of the side surface. (3) The nonvolatile semiconductor memory device according to claim 1, wherein the groove on the side surface of the floating gate is formed only on the side surface in the channel width direction of the cell. (4) A step of sequentially depositing a first layer polycrystalline silicon film and an insulating film on the device-isolated semiconductor substrate via a first gate insulating film to obtain a laminate, and an insulating film in the obtained laminate. A process of selectively etching to form a micro-opening in the gate region, depositing a second layer polycrystalline silicon film on the entire surface, and using a mask covering the gate region, from the second layer polycrystalline silicon film to the first layer polycrystalline silicon film. A process of selectively etching up to the silicon film and etching away the insulating film left between the first layer polycrystalline silicon film and the second layer polycrystalline silicon film to form a floating gate with grooves formed on the sides. and a second layer on the top surface, side surface and inner surface of the groove of the resulting floating gate.
forming a gate insulating film; and depositing a third layer polycrystalline silicon film on the entire surface and patterning it to form a control gate facing the top surface, side surfaces, and inner surface of the trench of the floating gate. A method of manufacturing a nonvolatile semiconductor memory device, characterized in that: (5) A step of sequentially depositing a first layer polycrystalline silicon film and an insulating film on the device-isolated semiconductor substrate via a first gate insulating film to obtain a laminate, and an insulating film in the obtained laminate. A process of selectively etching to form a microscopic opening in the gate region, depositing a second layer polycrystalline silicon film on the entire surface, and using a mask covering the element area to separate the second layer polycrystalline silicon film from the first layer polycrystalline silicon film. A step of selectively etching up to the silicon film to form a floating gate isolation trench on the element isolation region, and a first layer polycrystalline silicon film and a second layer polycrystalline silicon film exposed on the side surfaces of the formed floating gate isolation trench. A step of etching away an insulating film sandwiched between silicon films, and forming a second gate insulating film on the exposed surfaces of the first layer polycrystalline silicon film and the second layer polycrystalline silicon film, and then etching a third gate insulating film on the entire surface. A step of depositing a third layer polycrystalline silicon film, forming a striped mask running in the channel width direction on the deposited third layer polycrystalline silicon film, and using this to form a third layer polycrystalline silicon film.
selectively etching the layer polycrystalline silicon film to the second layer polycrystalline silicon film and the first layer polycrystalline silicon film to separately form a control gate continuous in the channel width direction and a floating gate self-aligned thereto; A method for manufacturing a nonvolatile semiconductor memory device, comprising: