JPH0334032B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for detecting failures in logic circuits that operate periodically.

A watchdog timer is generally used as a failure detection method for logic circuits that operate periodically. This method uses a set of counter circuits to count the time intervals of periodic operations in a logic circuit, and when the value exceeds a predetermined periodic operation interval, that is, the watchdog timer times up, abnormality processing starts. However, when the logic circuit is normal, the counter is initially set each time a periodic operation occurs, so the watchdog timer does not reach time-up, and therefore the circuit does not operate after time-up. Therefore, it was not possible to determine the failure of the circuit that would trigger the start of abnormal processing.

As mentioned above, if a failure occurs in the logic circuit without being detected in the part of the watchdog timer that is not always operating, it is necessary to quickly suppress the output or fix the output to a predetermined state. Fail-safe functions were difficult to obtain, and there were major restrictions on its introduction into security equipment.

The present invention has been made to eliminate the above-mentioned drawbacks, and embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a circuit configuration for implementing the method of the present invention, in which a processing result H of a logic circuit 1 is connected to an output circuit 5, and a logic operation end signal A from the logic circuit 1 is connected. It is connected to a monitoring circuit 4, and an activation signal B and an output inhibit signal G from the monitoring circuit 4 are connected to the logic circuit 1 and the output circuit 5, respectively.

Further, the time-up signal F of the timer circuit 2 of the watchdog timer consisting of the timer circuit 2, the counter circuit 3, and the monitoring circuit 4 is connected to the counter circuit 3, and the count-up signal C and counting output of the counter circuit 3 are connected. It is constructed by connecting the signal D to the monitoring circuit 4 and the counter counting control signal E from the monitoring circuit 4 to the counter circuit 3.

FIG. 2 is for explaining the operation in the specific embodiment of FIG. 1 when the logic circuit 1 operates normally and when the timer circuit 2 or the counter circuit 3 is out of order.

The counter circuit 3 is set to an initial value when the start signal B from the monitoring circuit 4 is output, and is timed up by the time up signal F of the timer circuit 2 which times up periodically or by preset. It is incremented each time. In this state, the logic operation end signal A of the logic circuit 1 causes the monitoring circuit 4 to
When activated, the monitoring circuit 4 inputs the count output signal D of the counter circuit 3 as shown in FIG. It is determined that the circuit 2 and the counter circuit 3 are operating normally, and the operation cycle of the logic circuit 1 is determined to be normal.

Next, the monitoring circuit 4 controls the counter circuit 3
The counter circuit 3 is controlled by the count control signal E by the number obtained by subtracting the count value 1 from the count up value n.
After the counter circuit 3 is incremented by
It is checked whether the counting output signal D from the circuit has reached the count-up value n, and if it has reached n, the counter circuit 3 is initially set by the counting control signal E, and the logic circuit is activated by the logic circuit activation signal B. 1, but if the counter circuit 3 does not reach n, it is determined that the counter circuit 3 is malfunctioning, and the external output information I of the output circuit 5 is activated by the output suppression signal G.
is forcibly output to a predetermined state (for example, logic "0") and the logic circuit 1 is not activated.

Further, if the count value i of the counter circuit 3 is not within a predetermined value range, it is determined that there is an abnormality in the logic operation cycle of the logic circuit 1, and the output suppression signal G is used to control the output circuit 5. The external output information I is forced to be output in a predetermined state and the logic circuit 1 is not activated. Note that when the logic circuit 1 is activated by the logic circuit activation signal B, output information H is outputted from the result of the determined processing operation to the output circuit 5, and upon completion of the processing, the logic circuit operation end signal A is sent to the monitoring circuit. Output to 4.

FIG. 3 is for explaining the operation when the logic circuit 1 fails and the logic operation end signal A is no longer generated.

In the figure, when the logic circuit 1 fails and the logic operation completion signal A is no longer generated, the counter circuit 3 continues to count, so that after a certain period of time, the count-up value n is reached and the count-up signal C is reached. Accordingly, the monitoring circuit 4 is activated.
The monitoring circuit 4 forces the output circuit 5 to output external output information in a predetermined state using the output inhibit signal G, and does not activate the logic circuit 1.

In this embodiment, the monitoring circuit 4 monitors the count output signal D of the counter circuit 3 to monitor the periodic operation of the timer circuit 2.
In addition to detecting failures including the above, abnormal operation of the logic circuit 1 can also be detected by monitoring the periodic operation time interval of the logic circuit 1.

Furthermore, since the count-up operation of the counter circuit 3 is checked even during normal operation, failures in the counter circuit 3 can be detected in advance, and the external output information of the output circuit 5 can be immediately forced to a predetermined state. It can be output.

On the other hand, the monitoring circuit 4 monitors the counter circuit 3 when a failure such as a stoppage of the logic circuit 1 occurs.
Failure can be detected by time-up signal C from
Moreover, since it is possible to detect a failure in the watchdog timer according to the present invention, it is possible to detect a failure in the logic circuit 1 with an extremely high probability, and also to detect a failure in the output circuit 1.
External output information can be forced to be output in a predetermined state.

Therefore, conventionally, digital logic circuits using general-purpose logic components were thought to be difficult to introduce into security devices, but by using the method of the present invention, they can be easily introduced, and can be used as security devices with improved functionality and small size. This makes it possible to reduce costs, improve reliability, and improve reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a circuit configuration for implementing the method of the present invention, FIG. 2 is a flowchart for explaining the operation of the circuit configuration in FIG. The flowchart for this case is shown below. 1...Logic circuit, 2...Timer circuit, 3...Counter circuit, 4...Monitoring circuit, 5...Output circuit.

Claims (1)

[Claims] 1. A watchdog timer for monitoring the periodic operation of a logic circuit is composed of a timer circuit consisting of a periodic timer or a preset timer, a counter circuit, and a monitoring circuit, and the counter circuit is connected to the timer circuit and the monitoring circuit. the monitoring circuit to a logic circuit and an output circuit, and the logic circuit to the output circuit;
The monitoring circuit inputs the counted value of the counter circuit every time the periodic operation end signal from the logic circuit is input, and if the counted value is within a predetermined range below the full count, the monitoring circuit inputs the counted value of the counter circuit. The operation of the counter circuit and the counting operation of the timer circuit and the counter circuit are determined to be normal, and when the counter circuit is incremented or added by a known number until the full count is reached, the count up operation of the counter circuit is determined to be normal. Then, an initial value for monitoring the next periodic operation of the logic circuit is set in the counter circuit, and the logic circuit is activated to ensure normal operation of the logic circuit and the watchdog timer. If the count value of the counter circuit is outside a predetermined range, it is determined that the logic circuit has failed, and if the counter circuit does not reach a full count, the counter circuit performs a count-up operation. is determined to be a failure, the output of the output circuit is forcibly output to a predetermined state and the logic circuit is stopped, and furthermore, when the counter circuit continuously counts and reaches a full count, it is A method for detecting a failure in a logic circuit, characterized in that the failure is determined to be a failure in the logic circuit, the output of the output circuit is forcibly outputted in a predetermined state, and the logic circuit is not activated.