JPH0328951A - Input/output controller - Google Patents
Input/output controllerInfo
- Publication number
- JPH0328951A JPH0328951A JP16328289A JP16328289A JPH0328951A JP H0328951 A JPH0328951 A JP H0328951A JP 16328289 A JP16328289 A JP 16328289A JP 16328289 A JP16328289 A JP 16328289A JP H0328951 A JPH0328951 A JP H0328951A
- Authority
- JP
- Japan
- Prior art keywords
- level
- interrupt
- interruption
- circuit
- central processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012544 monitoring process Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Bus Control (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、データ処理システムの入出力制御装置に関し
、特に、中央処理装置に対し割込みを発生する入出力制
御装置に関する.
従来の技術
従来、この種の入出力制御装置において、中央処理装置
に対して割込みを発生する際には入出力制御装置内では
割込みレベルと中央処理装置の走行レベルとの比較は行
われなかった.
入出力制御装置は割込み要因が発生すると、中央処理装
置の状態に関係なく中央処理装置に対し割込みを実行す
る.中央処理装置は割込みレベルと自らのレベルとを比
較し、割込みが受付け可能か不可能かを判別する.そし
て中央処理装置は入出力制御装置に対し割込みが受付け
られたか否かを通知する.
発明が解決しようとする課題
上述した従来の入出力制御装置では、中央処理装置の走
行レベルの方が割込みレベルより優先度が高くても割込
みが発生してしまう.その為に、共通バス上で不要なバ
ス転送が発生し、共通バスの使用効率が低下する.
本発明は従来の上記実情に鑑みてなされたものであ一力
、従って本発明の目的は、従来の技術に内在する上記課
題を解決し、中央処理装置に対する無効な割込みの発生
を抑止し、共通バスの使用効率を向上させることを可能
とした新規な入出力制御装置を提供することにある.
課題を解決するための手段
上記目的を達成する為に、本発明に係る入出力制御装置
は、共通バスの専用ラインから中央処理装置の走行レベ
ルを入力する走行レベル監視回路と、前記走行レベルと
自装置に予め割当てられている割込みレベルとを比較し
割込みの可否を判定する割込みレベル判定回路と、中央
処理装置に対して割込みを発生する割込み回路とを備え
て構成され、中央処理装置の走行レベルが自らの割込み
レベルより優先度が低い場合にのみ割込みを実行するこ
とを特徴としている.
実施例
次に、本発明をその好ましい一実施例について図面を参
照して具体的に説明する.
第1図は本発明の一実施例を示すブロック楕戒図である
.
第1図を参照するに、本発明に係る入出力制御装置10
0は,共通バス101を介して中央処理装置102と接
続されている.
入出力制御装置100において割込み要因が発生すると
、主制御回路111は、割込み回路112に対して割込
みの起動を行うと共に、割込みレベル判定回路114に
対して割込みの可否を判定するように要求する.
割込みレベル判定回路114は、走行レベル監視回路1
13を介して中央処理装置102が共通バス101に出
力している走行レベルを取込み、自らの割込みレベルと
比較する.比較の結果、割込みレベルの方が走行レベル
より優先度が高いときには、割込みレベル判定回路11
4は割込み回路112に対し割込み実行を許可する.
割込み回路112はバスインタフェース回路110を制
御して中央処理装置102に対し割込みを発生する.
割込みレベル判定回路114の比較結果、割込みレベル
の方が走行レベルより優先度が低かった堝合には、割込
みレベル判定回路114は割込み回路112に対して割
込み実行の保留を指示する.この場合には、中央処理装
置102が走行レベルを変更し、入出力制御装置100
の割込みレベルより低い走行レベルになるまで、入出力
制御装置100は割込みを保留する.
また、割込みレベル判定回路114が割込み可否を判定
した時点では、走行レベルが低かったが、割込みが発生
した時点では走行レベルが変更されて割込みレベルより
優先度が高くなった場合には、中央処理装置102は割
込みを拒否しその旨入出力制御装置100に通知する.
拒否通知を受取った入出力vi御装置100は、割込み
を保留し、中央処理装置102の走行レベルが再び割込
みレベルより低くなったときに割込みを保留する.
発明の効果
以上説明したように、本発明によれば、入出力制御装置
が中央処理装置の走行レベルを自らの割込みレベルと直
接比較できるようにすることにより、中央処理装置への
無効な割込みの発生を抑止し,共通バスの使用効率を向
上させる効果が得られる.DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an input/output control device for a data processing system, and more particularly to an input/output control device that generates an interrupt to a central processing unit. Conventional technology Conventionally, in this type of input/output control device, when generating an interrupt to the central processing unit, the input/output control device did not compare the interrupt level with the running level of the central processing unit. .. When an interrupt factor occurs, the input/output control unit issues an interrupt to the central processing unit regardless of the state of the central processing unit. The central processing unit compares the interrupt level with its own level and determines whether the interrupt can be accepted or not. The central processing unit then notifies the input/output control unit whether or not the interrupt has been accepted. Problems to be Solved by the Invention In the conventional input/output control device described above, an interrupt occurs even if the running level of the central processing unit has a higher priority than the interrupt level. As a result, unnecessary bus transfers occur on the common bus, reducing the efficiency of using the common bus. The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to solve the above-mentioned problems inherent in the conventional technology, suppress the occurrence of invalid interrupts to the central processing unit, The purpose of this project is to provide a new input/output control device that makes it possible to improve the efficiency of using a common bus. Means for Solving the Problems In order to achieve the above object, an input/output control device according to the present invention includes a driving level monitoring circuit that inputs the driving level of the central processing unit from a dedicated line of a common bus, and a driving level monitoring circuit that inputs the driving level of the central processing unit from a dedicated line of a common bus. It is configured with an interrupt level determination circuit that compares the interrupt level assigned in advance to the own device and determines whether or not an interrupt is allowed, and an interrupt circuit that generates an interrupt to the central processing unit. The feature is that an interrupt is executed only when the level has a lower priority than its own interrupt level. Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings. FIG. 1 is a block elliptical diagram showing one embodiment of the present invention. Referring to FIG. 1, an input/output control device 10 according to the present invention
0 is connected to the central processing unit 102 via a common bus 101. When an interrupt factor occurs in the input/output control device 100, the main control circuit 111 activates the interrupt to the interrupt circuit 112, and requests the interrupt level determination circuit 114 to determine whether or not the interrupt is allowed. The interrupt level determination circuit 114 is connected to the running level monitoring circuit 1.
13, the running level output from the central processing unit 102 to the common bus 101 is taken in and compared with its own interrupt level. As a result of the comparison, if the interrupt level has higher priority than the running level, the interrupt level determination circuit 11
4 permits the interrupt circuit 112 to execute an interrupt. An interrupt circuit 112 controls the bus interface circuit 110 to generate an interrupt to the central processing unit 102. If the comparison result of the interrupt level determining circuit 114 indicates that the interrupt level has a lower priority than the running level, the interrupt level determining circuit 114 instructs the interrupt circuit 112 to suspend execution of the interrupt. In this case, the central processing unit 102 changes the driving level, and the input/output control unit 102 changes the driving level.
The input/output control device 100 suspends interrupts until the running level becomes lower than the interrupt level of . In addition, if the running level was low at the time when the interrupt level determination circuit 114 judged whether or not the interrupt was possible, but the running level was changed at the time when the interrupt occurred and the priority became higher than the interrupt level, the central processing The device 102 rejects the interrupt and notifies the input/output control device 100 accordingly. The input/output VI control device 100 that receives the rejection notification suspends the interrupt, and suspends the interrupt when the running level of the central processing unit 102 becomes lower than the interrupt level again. Effects of the Invention As explained above, according to the present invention, invalid interrupts to the central processing unit can be prevented by allowing the input/output control unit to directly compare the running level of the central processing unit with its own interrupt level. This has the effect of suppressing this occurrence and improving the efficiency of common bus usage.
第1図は本発明に係る入出力制御装置の一実施例を示す
ブロック構成図である.
100・・・入出力制御装置、101・・・共通バス、
102・・・中央処理装置、110・・・バスインタフ
ェース回路、111・・・主制御回路、112・・・割
込み回路、113・・・走行レベル監視回路、114・
・・割込みレベル判定回路FIG. 1 is a block diagram showing an embodiment of an input/output control device according to the present invention. 100... Input/output control device, 101... Common bus,
102... Central processing unit, 110... Bus interface circuit, 111... Main control circuit, 112... Interrupt circuit, 113... Driving level monitoring circuit, 114...
・Interrupt level determination circuit
Claims (1)
置に対して割込みを発生する入出力制御装置において、
中央処理装置に対して割込みを発生する為の割込み回路
と、共通バスの専用ラインから中央処理装置の走行レベ
ルを入力する走行レベル監視回路と、前記走行レベルと
自装置に予め割当てられている割込みレベルとを比較し
割込みの可否を判定する割込みレベル判定回路とを有し
、中央処理装置の走行レベルが自らの割込みレベルより
優先度が低い場合にのみ割込みを実行することを特徴と
した入出力制御装置。In an input/output control device that is connected to a central processing unit via a common bus and generates interrupts to the central processing unit,
An interrupt circuit for generating an interrupt to the central processing unit, a running level monitoring circuit that inputs the running level of the central processing unit from a dedicated line of the common bus, and an interrupt that is pre-assigned to the running level and the own device. An input/output device characterized in that it has an interrupt level determination circuit that compares the interrupt level with the interrupt level and determines whether or not an interrupt is allowed, and executes the interrupt only when the running level of the central processing unit has a lower priority than its own interrupt level. Control device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16328289A JPH0328951A (en) | 1989-06-26 | 1989-06-26 | Input/output controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16328289A JPH0328951A (en) | 1989-06-26 | 1989-06-26 | Input/output controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0328951A true JPH0328951A (en) | 1991-02-07 |
Family
ID=15770856
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16328289A Pending JPH0328951A (en) | 1989-06-26 | 1989-06-26 | Input/output controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0328951A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6581119B1 (en) | 1999-06-23 | 2003-06-17 | Denso Corporation | Interrupt controller and a microcomputer incorporating this controller |
US7676610B2 (en) | 2005-03-31 | 2010-03-09 | Fujitsu Limited | Device and method for optimization of target host device process handling according to the status and the priority of the target host device process |
-
1989
- 1989-06-26 JP JP16328289A patent/JPH0328951A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6581119B1 (en) | 1999-06-23 | 2003-06-17 | Denso Corporation | Interrupt controller and a microcomputer incorporating this controller |
US7676610B2 (en) | 2005-03-31 | 2010-03-09 | Fujitsu Limited | Device and method for optimization of target host device process handling according to the status and the priority of the target host device process |
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