JPH03286340A - Diagnostic device for cpu abnormality - Google Patents
Diagnostic device for cpu abnormalityInfo
- Publication number
- JPH03286340A JPH03286340A JP2087491A JP8749190A JPH03286340A JP H03286340 A JPH03286340 A JP H03286340A JP 2087491 A JP2087491 A JP 2087491A JP 8749190 A JP8749190 A JP 8749190A JP H03286340 A JPH03286340 A JP H03286340A
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- Prior art keywords
- input information
- cpu
- abnormality
- read
- cpus
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Links
- 230000005856 abnormality Effects 0.000 title claims abstract description 19
- 230000005540 biological transmission Effects 0.000 claims abstract description 19
- 238000003745 diagnosis Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 description 6
- 230000002159 abnormal effect Effects 0.000 description 3
- 230000001934 delay Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、2つのCPUを備え、共通の入力情報に対し
て2つのCPUの演算結果が相違するときに異常有りと
診断するC P Uの異常診断装置の改善に関する。[Detailed Description of the Invention] <Industrial Application Field> The present invention provides a CPU that is equipped with two CPUs and that diagnoses an abnormality when the calculation results of the two CPUs differ for common input information. This invention relates to improvement of an abnormality diagnosis device.
〈従来の技術〉
4輪操舵車両においては、前輪操舵時に前輪操舵方向と
同一方向又は逆方向に後輪を操舵制御するが、かかる後
輪の操舵方向及び操舵角は車両の各種運転情報に基づい
て設定され、後輪駆動用のモータ若しくは油圧回路に介
装される流量制御弁の開度を制御して後輪を操舵制御し
ている(実開昭63−158509号公報)。<Prior Art> In a four-wheel steering vehicle, when steering the front wheels, the rear wheels are steered in the same direction or in the opposite direction to the front wheel steering direction, and the steering direction and steering angle of the rear wheels are determined based on various driving information of the vehicle. The rear wheels are steered by controlling the opening degree of a flow control valve installed in a rear wheel drive motor or a hydraulic circuit (Japanese Utility Model Publication No. 158509/1988).
かかる後輪操舵制御は従来第5図に示すようにメイン及
びサブの2つのCPUI、2を用いて共通の入力情報に
対して制御量を演算し、メインのCPUIによる演算結
果をサブのCPU2に読み込み、サブのCPU2自身で
演算した結果と比較し、両者が一致する時には、そのま
ま演算結果を後輪操舵制御信号として出力するが、相違
するときには、いずれかのCPUが異常(暴走)と判断
して、サブのCPU2からフェールセーフ信号を出力停
止回路3へ出力して後輪操舵制御信号の出力を停止する
ようにしている。Conventionally, such rear wheel steering control uses two main and sub CPUs 2 to calculate a control amount based on common input information, as shown in FIG. It is read and compared with the result calculated by the sub CPU 2 itself, and if the two match, the calculation result is output as is as a rear wheel steering control signal, but if they differ, it is determined that one of the CPUs is abnormal (runaway). Then, the sub CPU 2 outputs a fail-safe signal to the output stop circuit 3 to stop outputting the rear wheel steering control signal.
〈発明が解決しようとする課題〉
しかしながら、このような従来のCPU異常診断装置に
おいては、2つのCPUI、2に入力信号を同一に入力
しているが、両者の入力情報の読み込み誤差によって出
力結果が異なったり、出力信号を出力するまでの時間的
遅れ等により入力タイミングの異なる入力情報に基づく
演算結果同士を比較したりすること等により正常時でも
両者の値が不一致となってフェールセーフが作動してし
まうことがあった。そのため、例えば8ビット信号とし
て出力される後輪制御信号を、出力前の比較の際には上
位4〜6ビツトのみで比較して一致。<Problems to be Solved by the Invention> However, in such a conventional CPU abnormality diagnosis device, the same input signal is input to the two CPUs, but the output result may vary due to an error in reading the input information of both. Even under normal conditions, when comparing calculation results based on input information with different input timings due to differences in input timing or time delays before outputting the output signal, the two values may not match even under normal conditions and a failsafe is activated. There were times when I ended up doing this. Therefore, for example, when comparing the rear wheel control signal output as an 8-bit signal before outputting it, only the upper 4 to 6 bits are compared to match.
不一致を判別しているが、当然診断精度は劣るものであ
った。Although discrepancies were detected, the diagnostic accuracy was naturally inferior.
本発明は、このような従来の問題点に鑑みなされたもの
で、CPUの異常診断を高精度に行えるようにした異常
診断装置を提供することを目的とする。The present invention has been made in view of such conventional problems, and an object of the present invention is to provide an abnormality diagnosis device that can perform abnormality diagnosis of a CPU with high accuracy.
〈課題を解決するための手段〉
このため本発明は第1図に示すように、2つのCPUを
備え、一方のCPUで読み込んだ入力情報を他方のCP
Uに伝送する入力情報伝送手段と、該入力情報伝送手段
に′よって伝送された入力情報と、他方のCPUが自ら
読み込んだ入力情報とを比較する比較手段と、該比較手
段によって比較された2つの入力情報が略一致している
とき入力情報伝送手段によって伝送された入力情報に基
づいて他方のCPUにより演算させる演算実行手段と、
前記演算実行手段によって他方のCPUにより演算され
た演算結果を、共通の入力情報によって一方のCPUに
より演算された演算結果と比較し、両者が一致しないと
きに異常有りと診断する判定手段と、を備えて構成する
。<Means for Solving the Problems> Therefore, as shown in FIG. 1, the present invention includes two CPUs, and input information read by one CPU is transferred to the other CPU.
an input information transmitting means for transmitting to U; a comparing means for comparing the input information transmitted by the input information transmitting means with the input information read by the other CPU; calculation execution means for causing the other CPU to perform calculations based on the input information transmitted by the input information transmission means when the two input information substantially match;
determining means for comparing the calculation result calculated by the other CPU by the calculation execution means with the calculation result calculated by one CPU using common input information, and diagnosing that there is an abnormality when the two do not match; Prepare and configure.
〈作用〉
入力情報伝送手段は、一方のCPU (例えばメインC
PU)が読み込んだ入力情報を他方のCPU(サブCP
U)に伝送する。<Operation> The input information transmission means is connected to one of the CPUs (for example, the main CPU
The input information read by the CPU (PU) is transferred to the other CPU (sub CPU).
U).
比較手段は、前記入力情報伝送手段によって伝送された
一方のCPUにより読み込まれた入力情報と、他方のC
PUが読み込んだ入力情報とを比較する。The comparison means compares the input information read by one CPU transmitted by the input information transmission means and the other CPU.
Compare the input information read by the PU.
そして、両者が略一致している場合には演算実行手段に
より、他方のCPUに入力情報伝送手段から伝送された
入力情報に基づいて演算を実行させる。If the two substantially match, the calculation execution means causes the other CPU to execute the calculation based on the input information transmitted from the input information transmission means.
前記他方のCPUによる演算結果と一方のCPUによる
演算結果とを比較し、両者が一致しない場合には判定手
段により異常があると判定される。The calculation result by the other CPU is compared with the calculation result by one CPU, and if the two do not match, the determining means determines that there is an abnormality.
これによれば、読み込み誤差を無くした全く共通の入力
情報に基づいて2つのCPUによる演算結果を比較して
異常診断が為されるため、診断精度が大幅に向上する。According to this, the abnormality diagnosis is performed by comparing the calculation results of the two CPUs based on completely common input information with no reading errors, so the diagnosis accuracy is greatly improved.
〈実施例〉 以下に、本発明の実施例を図面に基づいて説明する。<Example> Embodiments of the present invention will be described below based on the drawings.
第1図は従来例同様4輪操舵車両の後輪操舵制御装置に
本発明を適用した一実施例の構成を示す。FIG. 1 shows the configuration of an embodiment in which the present invention is applied to a rear wheel steering control device for a four-wheel steering vehicle, similar to the conventional example.
図において、メインのCP UllとサブのCPU12
には後輪制御用の各種の入力情報(車速、前輪の舵角、
舵角速度、舵角加速度及び後輪の舵角。In the figure, main CPU Ull and sub CPU12
includes various input information for rear wheel control (vehicle speed, front wheel steering angle,
Rudder angular speed, rudder angular acceleration, and rear wheel rudder angle.
舵角速度等の信号)が入力される。signals such as steering angular velocity) are input.
サブのCPU12は、D、 P、 RAM (デュア
ルポートラム)12Aを有し、該り、P、 RAM1
2Aを介してメインのCPUIIとの間で通信ライン1
3を介してデータの授受が行われ、特に異常#断に際し
てCPUIIによって読み込まれた入力情報及び該入力
情報に基づく演算の終了の表示が、CPU12のり、P
、RAM12Aに伝送されて記憶される。The sub CPU 12 has D, P, RAM (dual port RAM) 12A;
Communication line 1 with main CPU II via 2A
Data is exchanged through the CPU 12, and in particular, the input information read by the CPU II at the time of an abnormal # disconnection and the display of the completion of calculation based on the input information are displayed through the CPU 12, the P
, are transmitted to and stored in the RAM 12A.
CPUIIの出力(演算結果)がCPU12に読み込ま
れてモニターされ、異常と診断された時にフェールセー
フ信号を出力停止回路14に出力して出力を停止させる
ことは従来と同様である。The output (calculation result) of the CPU II is read into the CPU 12 and monitored, and when an abnormality is diagnosed, a fail-safe signal is output to the output stop circuit 14 to stop the output, as in the conventional case.
以下メインのCPUIIとサブのCPU12とによって
実行されるルーチンを第3図及び第4図に基づいて説明
する。The routine executed by the main CPU II and the sub CPU 12 will be described below with reference to FIGS. 3 and 4.
メインのCPUIIのルーチンを示す第3図において、
ステップ(図ではSと記す)1では、入力信号を読み込
む(データ算出)。In Figure 3, which shows the main CPU II routine,
In step 1 (denoted as S in the figure), an input signal is read (data calculation).
ステップ2では、ステップ1で読み込んだ入力情報を通
信ライン13を介してCPU12のり、P。In step 2, the input information read in step 1 is sent to the CPU 12 and P via the communication line 13.
RAM12Aに伝送する。Transmit to RAM 12A.
伝送が終了するとステップ3へ進んで入力伝送フラグを
1にセットする。When the transmission is completed, the process advances to step 3 and the input transmission flag is set to 1.
ステップ4では後輪操舵の制a値、具体的には駆動モー
タの極性と通電電流とを演算する。In step 4, the control a value for rear wheel steering, specifically the polarity and current of the drive motor, are calculated.
前記演算が終了するとステップ5へ進み、該演算結果に
応した制mtlX流を駆動モータに出力する。When the calculation is completed, the process proceeds to step 5, where a control mtlX flow corresponding to the calculation result is output to the drive motor.
ステップ6では、出力伝送フラグをlにセットする。In step 6, the output transmission flag is set to l.
サブのCPU12の制御ルーチンを示す第4図において
、ステップ11では入力信号を読み込む。In FIG. 4 showing the control routine of the sub CPU 12, in step 11 an input signal is read.
ステップ12では、前記メインのCPUIIで入力伝送
フラグが1にセットされたか否かを判定し、セットを待
ってステップ13に進む。In step 12, it is determined whether the input transmission flag is set to 1 in the main CPU II, and after waiting for the input transmission flag to be set, the process proceeds to step 13.
ステップ13では、入力伝送フラグを0にリセットする
。In step 13, the input transmission flag is reset to zero.
ステップ14では、D、P、RAM12Aに記憶された
メインのCPUIIによる入力情報をサブのCPU12
で読み込んだ入力情報と比較照合する。In step 14, input information from the main CPU II stored in the D, P, and RAM 12A is transferred to the sub CPU 12.
Compare and check with the input information read in.
そして、誤差範囲を超えて両者の値が相違する場合には
ステップ15へ進んでフェールセーフ信号を出力するが
、誤差範囲内で一致する場合にはステップ16へ進む。If the two values differ beyond the error range, the process proceeds to step 15 to output a failsafe signal, but if they match within the error range, the process proceeds to step 16.
ステップ16では、D、P、RAM12Aで読み込んだ
入力情報、即ちメインのCP Ullで読み込まれた入
力情報に基づいてサブのCPU12により後輪の制m値
を演算する。In step 16, the sub CPU 12 calculates the rear wheel control m value based on the input information read by the D, P, and RAM 12A, that is, the input information read by the main CPU Ull.
ステップ17では、前記メインのCPUIIで出力伝送
フラグが1にセットされたか否かを判定し、セットを待
ってステップ18へ進む。In step 17, it is determined whether or not the output transmission flag is set to 1 in the main CPU II, and the process waits for the output transmission flag to be set before proceeding to step 18.
ステップ18では、出力伝送フラグを0にリセットする
。In step 18, the output transmission flag is reset to zero.
ステップ19では、メインのCP Ullによる出力値
(ステップ4での演算結果)とサブのCPU12による
ステップ16での演算結果とを比較する。In step 19, the output value by the main CPU Ull (the calculation result in step 4) is compared with the calculation result in step 16 by the sub CPU 12.
そして、両者の値が一致しているときは正常と判断して
このルーチンを終了するが、不一致である場合は異常と
診断してステップ15へ進んでフェールセーフ信号を出
力し、制御信号の出力を停止する。If the two values match, it is determined to be normal and this routine ends; however, if they do not match, it is diagnosed as abnormal and proceeds to step 15, where a failsafe signal is output and a control signal is output. stop.
このようにすれば、メインのCP UllとサブのCP
U12とを同一の入力情報に基づく演算結果を比較して
異常診断が為されるので、入力情報の読み込み誤差や出
力遅れ等による相違を除いて高精度な診断を行える。In this way, the main CP Ull and the sub CP
Since abnormality diagnosis is performed by comparing the calculation results based on the same input information with U12, highly accurate diagnosis can be performed by eliminating differences due to input information reading errors, output delays, etc.
尚、ステップ2と通信ライン13とり、P、RAM12
Aとで入力情報伝送手段が構成され、ステップ14の機
能により比較手段が構成され、ステップ16の機能によ
り演算実行手段が構成され、ステップ1つの機能により
判定手段が構成される。In addition, step 2 and communication line 13, P, RAM 12
A constitutes an input information transmission means, the function of step 14 constitutes a comparison means, the function of step 16 constitutes an arithmetic execution means, and the function of one step constitutes a determination means.
〈発明の効果〉
以上説明したように本発明によれば、2つのCPUにお
いて全く同一の入力情報に基づいて演算した結果同士を
比較して異常診断を行う構成としたため、入力情報の読
み込み誤差や出力遅れ等による相違を除いて高精度な診
断を行え、車両の後輪操舵制御等の高度な信頼性の要求
に応えることができる。<Effects of the Invention> As explained above, according to the present invention, the abnormality diagnosis is performed by comparing the results calculated by two CPUs based on exactly the same input information, so that errors in reading input information and Highly accurate diagnosis can be performed by eliminating differences due to output delays, etc., and can meet the demands for high reliability in vehicle rear wheel steering control, etc.
第1図は、本発明の構成を示すブロック図、第2図は、
本発明の一実施例の構成を示す図、第3図及び第4図は
、同上実施例のメインのCPUとサブのCPtJとによ
るルーチンを示すフローチャート、第5図は、従来例を
示す図である。FIG. 1 is a block diagram showing the configuration of the present invention, and FIG. 2 is a block diagram showing the configuration of the present invention.
3 and 4 are flowcharts showing a routine by the main CPU and sub-CPtJ of the embodiment of the present invention, and FIG. 5 is a diagram showing a conventional example. be.
Claims (1)
報を他方のCPUに伝送する入力情報伝送手段と、該入
力情報伝送手段によって伝送された入力情報と、他方の
CPUが自ら読み込んだ入力情報とを比較する比較手段
と、該比較手段によって比較された2つの入力情報が略
一致しているとき入力情報伝送手段によって伝送された
入力情報に基づいて他方のCPUにより演算させる演算
実行手段と、前記演算実行手段によって他方のCPUに
より演算された演算結果を、共通の入力情報によって一
方のCPUにより演算された演算結果と比較し、両者が
一致しないときに異常有りと診断する判定手段と、を備
えて構成したことを特徴とするCPUの異常診断装置。An input information transmission means comprising two CPUs and transmitting input information read by one CPU to the other CPU, input information transmitted by the input information transmission means, and input information read by the other CPU by itself. a computation means for causing the other CPU to perform a computation based on the input information transmitted by the input information transmitting means when the two pieces of input information compared by the comparator substantially match; Comparing the calculation result calculated by the other CPU by the calculation execution means with the calculation result calculated by one CPU using common input information, and determining means for diagnosing that there is an abnormality when the two do not match. 1. A CPU abnormality diagnosis device characterized in that the CPU abnormality diagnosis device is configured as follows.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2087491A JPH03286340A (en) | 1990-04-03 | 1990-04-03 | Diagnostic device for cpu abnormality |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2087491A JPH03286340A (en) | 1990-04-03 | 1990-04-03 | Diagnostic device for cpu abnormality |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03286340A true JPH03286340A (en) | 1991-12-17 |
Family
ID=13916429
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2087491A Pending JPH03286340A (en) | 1990-04-03 | 1990-04-03 | Diagnostic device for cpu abnormality |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03286340A (en) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006043693A1 (en) | 2004-10-18 | 2006-04-27 | Toyota Jidosha Kabushiki Kaisha | Vehicle control apparatus for quickly dealing with communication abnormality in communication means between calculation control devices |
WO2009060953A1 (en) * | 2007-11-07 | 2009-05-14 | Mitsubishi Electric Corporation | Safety control device |
JP2009132281A (en) * | 2007-11-30 | 2009-06-18 | Mitsubishi Electric Corp | Steering control device |
JP2009298172A (en) * | 2008-06-10 | 2009-12-24 | Denso Corp | Electronic control unit for vgrs |
JP2010235116A (en) * | 2010-06-22 | 2010-10-21 | Mitsubishi Electric Corp | Steering control device |
JP2010287010A (en) * | 2009-06-11 | 2010-12-24 | Mitsubishi Electric Corp | Control system |
DE102011081640A1 (en) | 2010-08-26 | 2012-03-01 | Mitsubishi Electric Corp. | control system |
JP2013035510A (en) * | 2011-08-10 | 2013-02-21 | Toyota Motor Corp | System and method for controlling vehicle |
JP2013133767A (en) * | 2011-12-27 | 2013-07-08 | Bosch Corp | Engine control device for vehicle |
JP2014229198A (en) * | 2013-05-24 | 2014-12-08 | 株式会社ケーヒン | Multicore system |
JP2016032989A (en) * | 2014-07-31 | 2016-03-10 | 株式会社オートネットワーク技術研究所 | Load controller |
JP2018095203A (en) * | 2016-12-16 | 2018-06-21 | 株式会社クボタ | Automatic travel mobile vehicle |
JP2018136937A (en) * | 2017-02-16 | 2018-08-30 | インフィネオン テクノロジーズ アクチエンゲゼルシャフトInfineon Technologies AG | Alarm processing circuit and alarm processing method |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5525122A (en) * | 1978-08-11 | 1980-02-22 | Hitachi Ltd | Multiple digital control method |
JPS603001A (en) * | 1983-06-20 | 1985-01-09 | Mitsubishi Electric Corp | Input data processor |
JPS6091415A (en) * | 1983-10-24 | 1985-05-22 | Mitsubishi Electric Corp | Digital controller |
-
1990
- 1990-04-03 JP JP2087491A patent/JPH03286340A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5525122A (en) * | 1978-08-11 | 1980-02-22 | Hitachi Ltd | Multiple digital control method |
JPS603001A (en) * | 1983-06-20 | 1985-01-09 | Mitsubishi Electric Corp | Input data processor |
JPS6091415A (en) * | 1983-10-24 | 1985-05-22 | Mitsubishi Electric Corp | Digital controller |
Cited By (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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EP1803628A4 (en) * | 2004-10-18 | 2008-06-25 | Toyota Motor Co Ltd | Vehicle control apparatus for quickly dealing with communication abnormality in communication means between calculation control devices |
KR100866816B1 (en) * | 2004-10-18 | 2008-11-04 | 도요다 지도샤 가부시끼가이샤 | Vehicle control apparatus for quickly dealing with communication abnormality in communication means between calculation control devices |
US8478487B2 (en) | 2004-10-18 | 2013-07-02 | Toyota Jidosha Kabushiki Kaisha | Control device for vehicles to make rapid counter-measure against communication abnormality in communication means between calculation control devices |
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JP2009298172A (en) * | 2008-06-10 | 2009-12-24 | Denso Corp | Electronic control unit for vgrs |
JP4636125B2 (en) * | 2008-06-10 | 2011-02-23 | 株式会社デンソー | Electronic control unit for VGRS |
US8135515B2 (en) | 2008-06-10 | 2012-03-13 | Denso Corporation | Electronic control apparatus and method for a steering system |
JP2010287010A (en) * | 2009-06-11 | 2010-12-24 | Mitsubishi Electric Corp | Control system |
JP2010235116A (en) * | 2010-06-22 | 2010-10-21 | Mitsubishi Electric Corp | Steering control device |
JP2012048447A (en) * | 2010-08-26 | 2012-03-08 | Mitsubishi Electric Corp | Control system |
US8676353B2 (en) | 2010-08-26 | 2014-03-18 | Mitsubishi Electric Corporation | Control system |
DE102011081640A1 (en) | 2010-08-26 | 2012-03-01 | Mitsubishi Electric Corp. | control system |
JP2013035510A (en) * | 2011-08-10 | 2013-02-21 | Toyota Motor Corp | System and method for controlling vehicle |
JP2013133767A (en) * | 2011-12-27 | 2013-07-08 | Bosch Corp | Engine control device for vehicle |
JP2014229198A (en) * | 2013-05-24 | 2014-12-08 | 株式会社ケーヒン | Multicore system |
JP2016032989A (en) * | 2014-07-31 | 2016-03-10 | 株式会社オートネットワーク技術研究所 | Load controller |
JP2018095203A (en) * | 2016-12-16 | 2018-06-21 | 株式会社クボタ | Automatic travel mobile vehicle |
JP2018136937A (en) * | 2017-02-16 | 2018-08-30 | インフィネオン テクノロジーズ アクチエンゲゼルシャフトInfineon Technologies AG | Alarm processing circuit and alarm processing method |
US10467889B2 (en) | 2017-02-16 | 2019-11-05 | Infineon Technologies Ag | Alarm handling circuitry and method of handling an alarm |
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