JPH03285338A - Bonding pad - Google Patents
Bonding padInfo
- Publication number
- JPH03285338A JPH03285338A JP2084945A JP8494590A JPH03285338A JP H03285338 A JPH03285338 A JP H03285338A JP 2084945 A JP2084945 A JP 2084945A JP 8494590 A JP8494590 A JP 8494590A JP H03285338 A JPH03285338 A JP H03285338A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- pads
- pad
- semiconductor chip
- bonding pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 230000003071 parasitic effect Effects 0.000 abstract description 15
- 238000000034 method Methods 0.000 abstract description 6
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 4
- 230000002411 adverse Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05551—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的］
（産業上の利用分’Ｉｆ）
本発明は、例えば集積回路において、半導体チップの端
子と、この半導体チップを実装するパッケージのリード
との間をワイヤボンディングするために、上記半導体チ
ップに設けられるボンディングパッドに関する。Detailed Description of the Invention [Objective of the Invention] (Industrial Application 'If) The present invention provides a method for connecting wires between the terminals of a semiconductor chip and the leads of a package in which the semiconductor chip is mounted, for example in an integrated circuit. The present invention relates to a bonding pad provided on the semiconductor chip for bonding.
（従来の技術）
集積回路を製作する際に必要な丁：稈の一つとして、ワ
イヤボンディングがある。ワイヤボンディングとは、例
えば回路が作り込まれた十導体チップの電極、つまりボ
ンディングパッドと、上記半導体チップが実装されるパ
ッケージのリード電極との間を、金（Ａｕ）やアルミニ
ウム（Ａ１）等の細線を使用して接続する工程である。(Prior Art) Wire bonding is one of the methods necessary for manufacturing integrated circuits. Wire bonding refers to, for example, bonding between the electrodes of a ten-conductor chip on which a circuit is built, that is, the bonding pads, and the lead electrodes of a package on which the semiconductor chip is mounted, using a material such as gold (Au) or aluminum (A1). This is the process of connecting using thin wire.
ところで、上記ボンディングパッドとしては、従来では
一般に第４図に示すような正方形のものが使用されてい
る。By the way, as the above-mentioned bonding pad, a square bonding pad as shown in FIG. 4 has conventionally been generally used.
（発明が解決しようとする課題）
しかし、このような従来のボンディングパッドには次の
ような改善すべき課題があった。すなわち、半導体チッ
プにおけるボンディングパッド形成部分の断面構造は、
例えば第５図に示す如くｐ形すブスレート層１上にｎ形
エピタキシャル層２を形成する。そして、このｎ形エピ
タキシャル層２の上に熱酸化膜３を形成し、その上にボ
ンディングパッド４を形成したものとなっている。この
ため、ｐ形す−ブスレート層１とボンディングパッド４
との間には寄生容量が発生する。この寄生容量は、集積
回路がそれ程高くない周波数を扱う場合には問題になら
ないが、例えば４１）ＯＭＪＩｚ〜ＩＨＩｚというよう
に非常に高い周波数を扱う場合には、集積回路の特性に
悪影響を及ぼし極めて好ましくない。(Problems to be Solved by the Invention) However, such conventional bonding pads have the following problems that should be improved. In other words, the cross-sectional structure of the bonding pad forming portion of the semiconductor chip is as follows:
For example, as shown in FIG. 5, an n-type epitaxial layer 2 is formed on a p-type substrate layer 1. A thermal oxide film 3 is formed on this n-type epitaxial layer 2, and a bonding pad 4 is formed thereon. For this reason, the p-type substrate layer 1 and the bonding pad 4
A parasitic capacitance is generated between the two. This parasitic capacitance does not pose a problem when the integrated circuit handles frequencies that are not very high, but when it handles very high frequencies such as 41) OMJIz to IHIz, it adversely affects the characteristics of the integrated circuit and becomes extremely Undesirable.
一般に寄生容量の値は、主としてｐ形す−ブスレート層
１およびｎ形エピタキシャル層２の不純物濃度、熱酸化
［３の厚さ、ボンディングパッド４の面積により決定さ
れる。これらのうちｐ形す−ブスレート層１およびｎ形
エピタキシャル層２の不純物濃度と、熱酸化Ｈ３の厚さ
は、集積回路の各回路素子の定数や特性を決定する重要
な要素であるため容易に変えることはできない。Generally, the value of the parasitic capacitance is determined mainly by the impurity concentration of the p-type substrate layer 1 and the n-type epitaxial layer 2, the thickness of the thermal oxidation layer 3, and the area of the bonding pad 4. Among these, the impurity concentration of the p-type substrate layer 1 and the n-type epitaxial layer 2 and the thickness of the thermally oxidized layer H3 are important factors that determine the constants and characteristics of each circuit element of an integrated circuit, so they can be easily determined. It cannot be changed.
そこで、最近ではボンディングパッド４を形状を変えず
にそのまま小形化し、これによりパッドの面積を減らし
て寄生容量を低減することが考えられている。しかし、
この様にするとボンディングパッドの面積が小さくなっ
た分だけ、ワイヤボンディング装置の位置決め精度を高
めなければならなくなる。このため、ワイヤボンディン
グ装置の構成の複雑化やコストアップを招き、さらには
ボンディング速度の高速化を図れなくなるという別の問
題が発生し、白゛効な解決手段にはならなかった。Therefore, recently, it has been considered to reduce the size of the bonding pad 4 without changing its shape, thereby reducing the area of the pad and reducing the parasitic capacitance. but,
In this case, the positioning accuracy of the wire bonding device must be increased to the extent that the area of the bonding pad is reduced. For this reason, another problem occurred in that the configuration of the wire bonding apparatus became complicated and the cost increased, and furthermore, the bonding speed could not be increased, and this was not an effective solution.
そこで、本発明は上記事′情に着目し、ボンディング精
度を高めることなく寄生容量を低減することができるボ
ンディングパッドを提供することを目的とする。Therefore, the present invention has focused on the above-mentioned circumstances, and an object thereof is to provide a bonding pad that can reduce parasitic capacitance without increasing bonding accuracy.
［発明の構成］
（課題を解決するための手段）
本発明は、半導体チップの端子と、この半導体チップを
実装するパッケージのリードとの間をワイヤボンディン
グするために」７記半導体チップ上に設けられる方形の
ボンディングパッドにおいて、上記方形のボンディング
方形パッドの角部を切欠するようにしたものである。[Structure of the Invention] (Means for Solving the Problem) The present invention provides a method for wire bonding between terminals of a semiconductor chip and leads of a package on which this semiconductor chip is mounted. In the rectangular bonding pad, the corners of the rectangular bonding pad are cut out.
また他の本発明は、方形のボンディングパッドのパッド
面を、格子状あるいは網目状の導電パターンにより構成
したものである。In another aspect of the present invention, the pad surface of a rectangular bonding pad is configured with a grid-like or mesh-like conductive pattern.
さらに別の本発明は、方形のボンディングパッドの角部
を切欠し、かつパッド面を格子状あるいは網目状の導電
パターンにより構成したものである。In still another aspect of the present invention, the corners of a rectangular bonding pad are cut out, and the pad surface is formed with a grid-like or mesh-like conductive pattern.
（作 用）
この結果本発明によれば、方形パッドの角部を切欠する
ことによりパッドの面積を縮小するようにしたので、パ
ッドの対向する二辺間の長さを短くすることな（、つま
り実質的なパッドの大きさを縮小せずに、パッドの面積
を縮小することができる。したがって、ボンディング精
度を高めなくても歩留まりの良いボンディングを行なう
ことができ、しかもパッド面積の縮小により寄生容量を
減らして、回路に与える特性上の悪影響を低減すること
ができる。(Function) As a result, according to the present invention, the area of the rectangular pad is reduced by cutting out the corners of the pad, so the length between two opposing sides of the pad is not shortened ( In other words, it is possible to reduce the pad area without reducing the actual pad size.Therefore, it is possible to perform bonding with a high yield without increasing the bonding accuracy, and the reduction in the pad area also reduces parasitic By reducing the capacitance, it is possible to reduce the adverse effects on the characteristics of the circuit.
また他の本発明によれば、パッド面を格子状あるいは網
目状の導電部を残して他を切除した構造としたので、パ
ッドの大きさは従来と変わらず、パッドの面積のみを縮
小することができる。したがって、ボンディング精度を
高めなくても歩留まりの良いボンディングを行なうこと
ができ、しがも従来のパッドに比べて面積を約１／２に
減らすことができるため、寄生容量を大幅に減らすこと
が可能となる。According to another aspect of the present invention, the pad surface has a structure in which a lattice-like or mesh-like conductive part is left and the rest is removed, so that the size of the pad remains the same as before, and only the area of the pad can be reduced. I can do it. Therefore, high-yield bonding can be performed without increasing bonding precision, and the area can be reduced to about half that of conventional pads, making it possible to significantly reduce parasitic capacitance. becomes.
さらに別の本発明によれば、方形パッドの角部を切欠す
ると共に、パッド面を格子状あるいは網目状の導電部を
残して他を切除した構造としたので、パッドの大きさを
実質的に小さくせずに、パッドの面積をより一層縮小す
ることができる。According to still another aspect of the present invention, the corner portions of the square pad are cut out, and the pad surface has a structure in which a lattice-like or mesh-like conductive portion is left and the rest is cut away, so that the size of the pad can be substantially reduced. The area of the pad can be further reduced without reducing the size.
したがって、ボンディング精度を高めることなく、さら
に効果的に寄生容量を減少させるさせることができる。Therefore, parasitic capacitance can be further effectively reduced without increasing bonding accuracy.
（実施例）
第１図は、本発明の一実施例におけるボンディングパッ
ドの構成を示すものである。(Example) FIG. 1 shows the structure of a bonding pad in an example of the present invention.
同図において、１は集積回路が作り込まれた半導体チッ
プであり、この半導体チップ１の一辺部にはボンディン
グパッド２ ａ ＋ ２ ｂ ＋ ・・・が配設され
ている。これらのボンディングパッド２ａ。In the figure, 1 is a semiconductor chip in which an integrated circuit is built, and bonding pads 2 a + 2 b + . . . are provided on one side of the semiconductor chip 1. As shown in FIG. These bonding pads 2a.
２ｂ、・・・は、正方形をなすパッドの四角部を切欠す
るとともに、パッド面を格子状をなす導電パターンによ
り構成したものである。この導電パターンは、集積回路
本体を作り込む際に回路パターンの一つとして作成され
る。また、上記導電パターンの各格子間の間隔は、後述
するするボンディングワイヤの直径よりも小さく定めら
れる。尚、３ ａ 、３ ｂ ＊ ・・・は、上記ボン
ディングパッド２ａ。2b, . . . are square pads whose rectangular portions are cut out, and whose pad surfaces are constructed with conductive patterns in a lattice pattern. This conductive pattern is created as one of the circuit patterns when manufacturing the integrated circuit body. Further, the interval between each grid of the conductive pattern is determined to be smaller than the diameter of a bonding wire, which will be described later. Note that 3 a , 3 b * . . . are the bonding pads 2 a.
２ｂ、・・・と図示しない集積回路本体との間を接続す
るための回路パターンである。This is a circuit pattern for connecting between 2b, . . . and an integrated circuit main body (not shown).
一方４はパッケージであり、上記半導体チップ１はこの
パッケージ４内に実装される。このパッケージ４の一辺
部には、上記半導体チップ１の各ボンディングパッド２
ａ、 ２ｂ、・・・に１対１に対応してリード５ａ、
５ｂ、・・・が配設されており、これらのリード５ａ、
５ｂ、・・・の基端部はリード電極５ａ、６ｂ、・・・
に接続されている。そして、これらのリード電極６ａ、
６ｂ、・・・と、上記各ボンディングパッド２ａ、２ｂ
、・・・との間は、ワイヤボンディング工程においてボ
ンディングワイヤ７ａ、７ｂ、・・・により接続される
。On the other hand, 4 is a package, and the semiconductor chip 1 is mounted inside this package 4. On one side of this package 4, each bonding pad 2 of the semiconductor chip 1 is provided.
Lead 5a, in one-to-one correspondence with a, 2b,...
5b, . . . are arranged, and these leads 5a,
The base end portions of 5b, . . . are lead electrodes 5a, 6b, .
It is connected to the. And these lead electrodes 6a,
6b, . . . and each of the above bonding pads 2a, 2b.
, . . . are connected by bonding wires 7a, 7b, . . . in a wire bonding process.
このような構成であるから、各ボンディングパッド２ａ
、 ２ｂ、・・・はその四角部が切欠されており、し
かもボンディング面は格子状をなす導電パターンとなっ
ている。このため、ボンディングパッド２ａ、２．ｂ、
・・・のパッド面の面積は正方形の場合に比べて大幅に
小さくなる。したがって、ボンディングパッド２ａ、２
ｂ、・・・による寄生容量は正方形の場合に比べて減少
し、この結果集積回路の高周波特性を向上させることが
できる。With such a configuration, each bonding pad 2a
, 2b, . . . have their square portions cut out, and their bonding surfaces form a grid-like conductive pattern. For this reason, bonding pads 2a, 2. b,
The area of the pad surface of . . . is significantly smaller than that of a square pad. Therefore, bonding pads 2a, 2
The parasitic capacitance due to b, . . . is reduced compared to the square case, and as a result, the high frequency characteristics of the integrated circuit can be improved.
一方、ボンディングワイヤ７ ａ ＋ ７ ｂ ＋
・・・の溶着部の形状は、例えば第１図に示す如く一般
に半球状になる。このため、ボンディングパッド２ａ。On the other hand, bonding wire 7 a + 7 b +
The shape of the welded portion is generally hemispherical, as shown in FIG. 1, for example. For this reason, the bonding pad 2a.
２ｂ、・・の四角部分は、ボンディングにおいてそれほ
どｆｆ１ｆｆな部分とはならない。また、ボンディング
パッド２ａ、２ｂ、・・・の対向する二辺間の長さは従
来のものと変わっていない。このため、ボンディングに
寄与するパッドの実質的な大きさは従来と変わらない。The square portions 2b, . . . do not become very ff1ff portions in bonding. Further, the length between the two opposing sides of the bonding pads 2a, 2b, . . . is unchanged from the conventional one. Therefore, the actual size of the pad that contributes to bonding remains the same as before.
したがって、ボンディングパッド２Ｂ、２ｂ、・・・に
対する位置決め精度を高める必要はなく、従来の精度と
同じ精度で歩留まりの高いボンディングを行なうことが
できる。Therefore, there is no need to increase the accuracy of positioning the bonding pads 2B, 2b, . . . , and bonding can be performed with high yield with the same accuracy as the conventional technique.
すなわち、本実施例のボンディングパッド２ａ。That is, the bonding pad 2a of this embodiment.
２ｂ ・・・を使用することにより、ボンディング精度
を高めることなく寄生容量を減少させ、これにより安価
で高周波特性の優れた集積回路を提供することが可能に
なる。By using 2b..., parasitic capacitance can be reduced without increasing bonding accuracy, thereby making it possible to provide an inexpensive integrated circuit with excellent high frequency characteristics.
尚、本発明は上記実施例に限定されるものではない。例
えば、パッド面は第２図に示す如く網目状の導電パター
ンにより構成してもよい。Note that the present invention is not limited to the above embodiments. For example, the pad surface may be constructed of a mesh-like conductive pattern as shown in FIG.
また、パッド面の導電パターンは、例えば第３図に示す
如くパッド面の周辺部から中央部に向かうに従って格子
の間隔を狭くしたり、さらには第４図に示す如くパッド
面の中央部分のみを網目状の導電パターンにより構成す
るようにしてもよい。In addition, the conductive pattern on the pad surface may be arranged such that the grid spacing is narrowed from the periphery toward the center of the pad surface as shown in FIG. 3, or even only in the center of the pad surface as shown in FIG. It may also be configured with a mesh-like conductive pattern.
この様にすると、パッド面の中央部分における導電パタ
ーンの重度を高めることができ、これによりパッド面の
導電パターンの総面積をそれほど増やさずに、ボンディ
ングワイヤ７ａ、７ｂ、・・の溶青部に対するパッド面
の接触面積を増やすことができる。すなわち、寄生容量
を低減した上で、ボンディングワイヤの接続抵抗を減少
させることができる。In this way, it is possible to increase the weight of the conductive pattern in the central part of the pad surface, and thereby, the bonding wires 7a, 7b, etc. The contact area of the pad surface can be increased. That is, it is possible to reduce the connection resistance of the bonding wire while reducing the parasitic capacitance.
また、パッドの四角部を切欠するだけで寄生容量を十分
に低減できる場合には、パッド面を第５図に示す如く平
面導電パターンにより構成してもよい。さらに、ボンデ
ィングパッドの外形形状は長方形や台形、平行四辺形等
の他の形状でもよく、また切欠部の形状やパッド面の導
電パターンの形状等についても、本発明の要旨を逸脱し
ない範囲で種々変形して実施できる。Further, if the parasitic capacitance can be sufficiently reduced by simply cutting out the square portion of the pad, the pad surface may be constructed of a planar conductive pattern as shown in FIG. Furthermore, the external shape of the bonding pad may be other shapes such as a rectangle, trapezoid, or parallelogram, and the shape of the notch, the shape of the conductive pattern on the pad surface, etc. may be varied without departing from the gist of the present invention. It can be modified and implemented.
［発明の効果］
以上詳述したように本発明は、方形のボンディングパッ
ドの角部を切欠すること、ボンディングパッドのパッド
面を格子状あるいは網目状の導電パターンにより構成す
ること、および方形のボンディングバ・ソドの角部を切
欠し、かつパッド面を格子状あるいは網目状の導電パタ
ーンにより構成することをそれぞれ特徴とするものであ
る。[Effects of the Invention] As described in detail above, the present invention includes cutting out the corners of a rectangular bonding pad, configuring the pad surface of the bonding pad with a grid-like or mesh-like conductive pattern, and rectangular bonding. Each of these pads is characterized in that the corners of the pad are cut out, and the pad surface is constructed with a grid-like or mesh-like conductive pattern.
したがって本発明によれば、ボンディング精度を高める
ことなく寄生容量を低減することができるボンディング
パッドを提供することができる。Therefore, according to the present invention, it is possible to provide a bonding pad that can reduce parasitic capacitance without increasing bonding accuracy.
第１図は本発明の一実施例におけるボンディングパッド
およびその周辺部の構成を示す平面図、第２図乃至第５
図はそれぞれ本発明の他の異なる実施例におけるボンデ
ィングパッドを示す平面図である。
１・・・半導体チップ、２ａ、２ｂ、・・・ボンディン
グパッド、３ ａ ＊ ３ ｂ＋ ・・・回路パタ
ーン、４・・・パッケージ、５ａ、５ｂ、 ・・・リ
ード、６ａ、６ｂ、−・・リード電極、７ｍ、７ｂ、−
・・ボンディングワイヤ。FIG. 1 is a plan view showing the configuration of a bonding pad and its surrounding area in one embodiment of the present invention, and FIGS.
Each figure is a plan view showing bonding pads in other different embodiments of the present invention. DESCRIPTION OF SYMBOLS 1...Semiconductor chip, 2a, 2b,...Bonding pad, 3a*3b+...Circuit pattern, 4...Package, 5a, 5b,...Lead, 6a, 6b,-... Lead electrode, 7m, 7b, -
・Bonding wire.
Claims (3)
するパッケージのリードとの間をワイヤボンディングす
るために前記半導体チップ上に設けられる方形のボンデ
ィングパッドにおいて、 前記方形のボンディングパッドの角部を切欠したことを
特徴とするボンディングパッド。(1) In a rectangular bonding pad provided on the semiconductor chip for wire bonding between a terminal of a semiconductor chip and a lead of a package on which this semiconductor chip is mounted, a corner of the rectangular bonding pad is cut out. A bonding pad that is characterized by:
するパッケージのリードとの間をワイヤボンディングす
るために前記半導体チップ上に設けられる方形のボンデ
ィングパッドにおいて、 前記方形のボンディングパッドのパッド面を、格子状あ
るいは網目状の導電パターンにより構成したことを特徴
とするボンディングパッド。(2) In a rectangular bonding pad provided on the semiconductor chip for wire bonding between a terminal of a semiconductor chip and a lead of a package on which this semiconductor chip is mounted, the pad surface of the rectangular bonding pad is A bonding pad characterized by being constructed of a grid-like or mesh-like conductive pattern.
するパッケージのリードとの間をワイヤボンディングす
るために前記半導体チップ上に設けられる方形のボンデ
ィングパッドにおいて、 前記方形のボンディングパッドの角部を切欠し、かつパ
ッド面を格子状あるいは網目状の導電パターンにより構
成したことを特徴とするボンディングパッド。(3) In a rectangular bonding pad provided on the semiconductor chip for wire bonding between a terminal of the semiconductor chip and a lead of a package on which the semiconductor chip is mounted, a corner of the rectangular bonding pad is cut out. A bonding pad characterized in that the pad surface is constituted by a grid-like or mesh-like conductive pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2084945A JPH03285338A (en) | 1990-04-02 | 1990-04-02 | Bonding pad |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2084945A JPH03285338A (en) | 1990-04-02 | 1990-04-02 | Bonding pad |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03285338A true JPH03285338A (en) | 1991-12-16 |
Family
ID=13844786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2084945A Pending JPH03285338A (en) | 1990-04-02 | 1990-04-02 | Bonding pad |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03285338A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6414415B1 (en) | 1999-02-18 | 2002-07-02 | Murata Manufacturing Co., Ltd. | Surface acoustic wave device and method for manufacturing the same |
| JP2006228997A (en) * | 2005-02-18 | 2006-08-31 | Fujitsu Ltd | Printed circuit board |
| US7298629B2 (en) * | 2005-01-31 | 2007-11-20 | Kabushiki Kaisha Toshiba | Circuit board for mounting a semiconductor circuit with a surface mount package |
| JP2013200909A (en) * | 2012-03-23 | 2013-10-03 | Nitto Denko Corp | Wiring circuit board |
| JP2014503992A (en) * | 2010-11-15 | 2014-02-13 | テッセラ，インコーポレイテッド | Conductive pads defined by embedded traces |
| US8896397B2 (en) * | 2003-04-16 | 2014-11-25 | Intellectual Ventures Fund 77 Llc | Surface acoustic wave device and method of adjusting LC component of surface acoustic wave device |
| US9368476B2 (en) | 2010-12-02 | 2016-06-14 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
| US9548254B2 (en) | 2006-11-22 | 2017-01-17 | Tessera, Inc. | Packaged semiconductor chips with array |
| US9620437B2 (en) | 2010-12-02 | 2017-04-11 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages and carrier above chip |
| US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
| USRE47410E1 (en) * | 2003-04-16 | 2019-05-28 | Intellectual Ventures Holding 81 Llc | Surface acoustic wave device and method of adjusting LC component of surface acoustic wave device |
| US10354942B2 (en) | 2010-09-17 | 2019-07-16 | Tessera, Inc. | Staged via formation from both sides of chip |
-
1990
- 1990-04-02 JP JP2084945A patent/JPH03285338A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6414415B1 (en) | 1999-02-18 | 2002-07-02 | Murata Manufacturing Co., Ltd. | Surface acoustic wave device and method for manufacturing the same |
| US8896397B2 (en) * | 2003-04-16 | 2014-11-25 | Intellectual Ventures Fund 77 Llc | Surface acoustic wave device and method of adjusting LC component of surface acoustic wave device |
| USRE47410E1 (en) * | 2003-04-16 | 2019-05-28 | Intellectual Ventures Holding 81 Llc | Surface acoustic wave device and method of adjusting LC component of surface acoustic wave device |
| US7298629B2 (en) * | 2005-01-31 | 2007-11-20 | Kabushiki Kaisha Toshiba | Circuit board for mounting a semiconductor circuit with a surface mount package |
| JP2006228997A (en) * | 2005-02-18 | 2006-08-31 | Fujitsu Ltd | Printed circuit board |
| US9548254B2 (en) | 2006-11-22 | 2017-01-17 | Tessera, Inc. | Packaged semiconductor chips with array |
| US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
| US10354942B2 (en) | 2010-09-17 | 2019-07-16 | Tessera, Inc. | Staged via formation from both sides of chip |
| JP2014503992A (en) * | 2010-11-15 | 2014-02-13 | テッセラ，インコーポレイテッド | Conductive pads defined by embedded traces |
| US9368476B2 (en) | 2010-12-02 | 2016-06-14 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
| US9620437B2 (en) | 2010-12-02 | 2017-04-11 | Tessera, Inc. | Stacked microelectronic assembly with TSVS formed in stages and carrier above chip |
| JP2013200909A (en) * | 2012-03-23 | 2013-10-03 | Nitto Denko Corp | Wiring circuit board |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH03285338A (en) | Bonding pad | |
| US4754912A (en) | Controlled collapse thermocompression gang bonding | |
| JP2003110080A (en) | Semiconductor device | |
| JPH04123448A (en) | Semi-conductor mounting apparatus | |
| US10707153B2 (en) | Semiconductor device having die pad | |
| JPH07321160A (en) | Semiconductor device | |
| JPS63271944A (en) | Semiconductor device | |
| JPH097975A (en) | Semiconductor device and its manufacture | |
| JPH0661289A (en) | Semiconductor package and semiconductor module using same | |
| US3450956A (en) | Method for simultaneously contacting a plurality of electrodes of a semiconductor element | |
| JPH03109760A (en) | Semiconductor device | |
| US4425575A (en) | Base for encapsulating components with coplanar electrodes | |
| JPS61174659A (en) | Semiconductor device | |
| JP2600898B2 (en) | Thin package device | |
| JPH06132444A (en) | Semiconductor device | |
| KR200148753Y1 (en) | Semiconductor package | |
| JPH04237179A (en) | Semiconductor laser device | |
| JP2001244284A (en) | Semiconductor device and method of manufacturing the same | |
| JPH0214558A (en) | Semiconductor integrated circuit device | |
| JPH06196824A (en) | Manufacture of semiconductor element | |
| JPH05326736A (en) | Semiconductor device | |
| JPH09283690A (en) | Lead frame for semiconductor integrated circuit | |
| JPH04186755A (en) | Lead frame | |
| JP2000068404A (en) | Substrate for bga package | |
| JPH05218460A (en) | Semiconductor device and manufacture thereof |