JPH03284021A - System and instrument for receiving data signal - Google Patents

Abstract

PURPOSE:To improve correction capacity and to perform data transmission with high reliability by performing the error correction of a data signal transmitted on a communication line where intercode interference occurs by using a maximum likelihood system estimation equalizing system and an error correction code simultaneously. CONSTITUTION:An A/D-converted data signal is inputted to a branchmetric arithmetic circuit 102 via an input terminal 101. The circuit 102 computes branchmetric in accordance with each state transition based on an input signal, and outputs a result to an ACS circuit 103. The circuit 103 sets the busmetric of each state so as to obtain the highest likelihood of a survival bus arriving at the present state, and also, outputs a bus memory update control signal and a survival bus selection signal representing the survival bus that is the maximum likelihood survival bus at present to bus memory 104. The bus memory 104 updates the survival bus arriving at each state based on the bus memory update control signal, and outputs the oldest past value of maximum likelihood obtained from the survival bus selection signal to a soft decision error correction code decoder circuit 106 as an equalization result.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention uses a maximum likelihood sequence estimation equalization method and an error correction code at the same time to solve data signals transmitted over a communication path where code amount interference occurs. The present invention relates to a data signal receiving system and device that performs error correction and enables highly reliable data transmission.

(Prior Art) In order to perform data transmission with high reliability through a communication path where code amount interference occurs, it is necessary to eliminate code amount interference on the communication path. Various equalization methods such as linear equalization and decision feedback equalization are known as measures to eliminate code amount interference (Proakis, Digital Communications, McGraw-Hill, 1983).These equalization methods Among them, the maximum likelihood sequence estimation method is known as the optimal method that minimizes the error rate (Proakis, Digital Communications, McGraw-Hill,
(1983), this maximum likelihood sequence estimation method has high equalization ability, but the amount of calculation is enormous compared to other equalization methods. For this reason, a maximum likelihood sequence estimation method using the Viterbi algorithm, which requires a small amount of calculation, is well known as a maximum likelihood sequence estimation algorithm.

On the other hand, when decoding an error correction code, if the soft decision output of the received data signal is used for decoding (soft decision decoding),
It is known that the correction ability is much improved compared to the case of decoding using the hard decision output of the received data signal (hard decision decoding).

For example, 8-level soft-decision decoding can provide a coding gain of approximately 2 dB in S/N ratio compared to hard-decision decoding (Hide Samejima-1, "Soft-decision technology", Journal of the Institute of Electronics and Communication Engineers, vol.

67.5. pp, 564-568. (Showa 59).

Conventionally, several methods have been proposed for realizing soft-decision decoding in a data signal reception system that combines an equalization method other than maximum likelihood sequence estimation equalization and an error correction code6.
A method of creating a soft decision signal using received field strength information is known.

(Mitsuru Uesugi et al., “Compensation of frequency-selective fading in mobile uncontrolled using soft-decision vtterb+decoding” 198
Proceedings of the 9th IEICE Autumn National Conference B-519
) (Problem to be solved by the invention) However, in the maximum likelihood sequence estimation equalization method using the Viterbi algorithm, in principle, only hard decision results can be obtained as the equalization result. In a system that uses both equalization and error correction code at the same time, it is not possible to realize soft decision decoding in decoding the error correction code, and the correction ability of the error correction code cannot be fully utilized. The disadvantage is that the best methods cannot be used in combination.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a data signal receiving method and apparatus that make it possible to use soft-decision decoding to decode error correction codes even in a method that uses a maximum likelihood sequence estimation equalization method and an error correction code simultaneously. By doing so, the purpose is to improve the correction ability of the error correction code when data is transmitted on a communication path where code amount interference occurs. That is, an object of the present invention is to make it possible to use a combination of the best methods for both equalization and decoding, and to realize data transmission with higher reliability.

(Means for Solving the Problems) A data signal receiving system according to the present invention provides data that performs error correction of an input data signal using a maximum likelihood sequence estimation equalization means using a Viterbi algorithm and a soft-decision error correction code decoding means. Signal reception system The soft-decision error correction code decoding means includes:
The equalization result obtained from the maximum likelihood sequence estimation equalization means and the information on the equalization process in the maximum likelihood sequence estimation equalization means obtained by observing the internal state of the maximum likelihood sequence estimation equalization means. It is characterized by performing error correction on data signals.

A first data signal receiving device according to the present invention performs error correction of an input data signal based on a maximum likelihood sequence estimation equalization circuit using the Viterbi algorithm and information output from the maximum likelihood sequence estimation equalization circuit. A data signal receiving device comprising a soft-decision error correction code decoding circuit, wherein the maximum likelihood sequence estimation equalization circuit receives a data signal and calculates a likelihood between the data signal and an equalization result for each state transition. A branch metric calculation circuit that outputs the calculated branch metric, updates the path metric by inputting the technique metric and the path metric for each state, and stores the path metric and path memory for each state at the time the path metric is updated. an ACS circuit that outputs an update control signal; a path metric storage circuit that stores path metrics for each state at the time of the update; and a path metric storage circuit that inputs the path metrics for each state and calculates a maximum likelihood path metric from among the path metrics. a path metric comparison circuit that selects and outputs a state that gives the maximum likelihood path metric; and a path metric comparison circuit that stores a state sequence group or a transition sequence group based on the surviving paths of each state, and inputs the path memory update control signal. The state sequence group or transition sequence group based on the surviving path of each state is updated based on the path memory update control signal, and the state sequence group or transition sequence group based on the surviving path of each state is updated. a path memory that outputs an old state sequence group or a transition sequence group as an equalization result group; In addition to selecting and outputting the equalization result corresponding to the state output from the path metric comparison circuit, all of the surviving path groups from the equalization result group or predetermined equalization results from the equalization result group are selected and output. For multiple paths selected according to rules, count the number of equalization results that give the same result as the equalization result, convert the number of equalization results into numerical values according to predetermined rules, and equalize the numerical values. A second data signal receiving apparatus according to the present invention is characterized in that it comprises: an equalization result determination circuit that simultaneously outputs the equalization result as a process information signal; A data signal receiving device comprising a circuit and a soft-decision error correction code decoding circuit that performs error correction of an input data signal based on information output from the maximum likelihood sequence estimation equalization circuit, the data signal receiving device comprising: The equalization circuit includes a branch metric calculation circuit that inputs a data signal and outputs a branch metric calculated as the likelihood of the data signal and the equalization result for each state transition; an ACS circuit that inputs and updates the path metric and outputs a path metric and a path memory update control signal for each state at the time of updating the path metric; and an ACS circuit that stores the path metric for each state at the time of updating. A path metric storage circuit inputs the path metric for each state, selects the maximum likelihood path metric from among the path metrics, stores and outputs the state that gives the maximum likelihood path metric, and stores and outputs the state that gives the maximum likelihood path metric. a path metric comparison circuit that outputs information as to whether the most likely path has transitioned from the most likely state one point before the output time (continuity information of the most likely path); A state sequence group or a transition sequence group based on the above is stored, and the path memory update control signal is inputted to generate a state sequence group or a transition sequence group based on the surviving path of each state based on the path memory update control signal. and outputs the oldest state sequence group or transition sequence group as an equalization result group among the state sequence group or transition sequence group based on the surviving paths of each state; and the output from the path metric comparison circuit. The continuity information of the maximum likelihood path is stored, and the state for providing the maximum likelihood path metric output from the path metric comparison circuit and the equalization result group output from the path memory are input, and the Select and output the equalization result corresponding to the maximum likelihood path metric from the group of results, and simultaneously output the continuity information of the oldest maximum likelihood path as an equalization process information signal at that point simultaneously with the equalization result. It is characterized by comprising: an equalization result determination circuit; and an equalization result determination circuit.

A third data signal receiving device according to the present invention performs error correction of an input data signal based on a maximum likelihood sequence estimation equalization circuit using the Viterbi algorithm and information output from the maximum likelihood sequence estimation equalization circuit. A data signal receiving device comprising a soft-decision error correction code decoding circuit, wherein the maximum likelihood sequence estimation equalization circuit receives a data signal and calculates a likelihood between the data signal and an equalization result for each state transition. a branch metric calculation circuit that outputs a calculated branch metric, inputs the branch metric and a path metric for each state to update the path metric, and stores a path metric and a path memory for each state at the time the path metric is updated; an ACS circuit that outputs an update control signal, a path metric storage circuit that stores path metrics for each state at the time of the update, inputs the path metrics for each state, and selects a maximum likelihood path metric from among the path metrics. a path metric comparison circuit that outputs the maximum likelihood path metric; and a path metric comparison circuit that stores a state sequence group or a transition sequence group based on the surviving paths of each state, and inputs an update control signal to the path memory to output the maximum likelihood path metric. The state sequence group or transition sequence group based on the surviving path of each state is updated based on the path memory update control signal, and the oldest state sequence group among the state sequence group or transition sequence based on the surviving path of each state is updated. Alternatively, a path memory that outputs a transition sequence group as an equalization result group, a state giving a maximum likelihood path metric output from the path metric comparison circuit, and the equalization result group output from the path memory are input. Selecting and outputting the equalization result corresponding to the oldest point in time of the maximum likelihood path metric from the group of equalization results, and storing the state sequence at the oldest point in time corresponding to the equalization result; Equalizing information indicating whether or not the state series at the oldest point selected one point before the output time and the state series at the oldest point selected at the output point are continuous. It is characterized by comprising an equalization result determination circuit that simultaneously outputs the equalization result as a process information signal.

A fourth data signal receiving device according to the present invention a performs error correction of an input data signal based on a maximum likelihood sequence estimation equalization circuit using the Viterbi algorithm and information output from the maximum likelihood sequence estimation equalization circuit. A data signal receiving apparatus having a soft-decision error correction code decoding circuit that inputs a data signal and outputs a branch metric calculated as a likelihood between the data signal and an equalization result for each state WIN shift. a branch metric calculation circuit; and an ACS that updates the path metric by inputting the branch metric and the path metric for each state, and outputs the path metric for each state at the time of updating the path metric and a path memory update control signal. a path metric storage circuit that stores a path metric for each state at the time of the update; a path metric storage circuit that inputs the path metric for each state, selects a maximum likelihood path metric from among the path metrics, and stores the maximum likelihood path metric; a path metric comparison circuit that stores a state series Ha or a transition series group based on the surviving paths of each state, inputs the path memory update control signal, and performs a process based on the path memory update control signal. update the state sequence group or transition sequence group based on the surviving path of each state, and update the oldest state sequence group or transition sequence group among the state sequence group or transition sequence group based on the surviving path of each state. A path memory to be output as a group of equalization results, a state giving a maximum likelihood path metric output from the path metric comparison circuit, and the group of equalization results output from the path memory are input to calculate the group of equalization results. Select and output the equalization result corresponding to the maximum likelihood path metric from among them, and calculate the number of surviving paths that are continuous from the maximum likelihood path one point before the output time for the surviving paths at the output time. The number of surviving paths consecutive from the maximum likelihood path is converted into a numerical value according to a predetermined rule, and the numerical value is stored as the equalization process information signal at the output time, and the oldest equalization process information is It is characterized by comprising: an equalization result determination circuit that outputs a signal simultaneously with the equalization result.

A fifth data signal receiving device according to the present invention performs error correction of an input data signal based on a maximum likelihood sequence estimation equalization circuit using the Viterbi algorithm and information output from the maximum likelihood sequence estimation equalization circuit. A data signal receiving device with a soft-decision error correction code decoding circuit! a branch metric calculation circuit that inputs a data signal and outputs a branch metric calculated as the likelihood of the data signal and an equalization result for each state transition; an AC3 circuit that inputs and updates the path metric and outputs a path metric and a path memory update control signal for each state at the time of updating the path metric; and a path metric that stores the path metric for each state at the time of updating. A storage circuit that inputs the path metric for each state, selects the maximum likelihood path metric from among the path metrics, stores and outputs the state that gives the maximum likelihood path metric, and stores and outputs the maximum likelihood path metric at the time of output. Calculate the difference between the metric and the path metric of a path selected according to a predetermined rule, or the difference between the average value of all path metrics, and convert the calculated difference value into a numerical value according to a predetermined rule. a path metric comparison circuit that outputs the numerical value as an equalization process information signal at the output time; and a path metric comparison circuit that stores a state series group or a transition series group based on the surviving paths of each state, and controls the path memory update control. A state sequence group or a transition sequence group based on the surviving paths of each state is updated based on the path memory update control signal by inputting a signal, and a state sequence group or a transition sequence group based on the surviving paths of each state is updated. a path memory that outputs the oldest state sequence group or transition sequence group as an equalization result group; and a path memory that stores the equalization process information signal output from the path metric comparison circuit; inputting the state giving the maximum likelihood path metric and the group of equalization results output from the path memory, and selecting the equalization result corresponding to the maximum likelihood path metric from the group of equalization results. It is characterized by comprising an equalization result determination circuit that outputs the equalization result at the same time as the equalization process information signal at the earliest point in time.

A sixth data signal receiving device according to the present invention performs error correction of an input data signal based on a maximum likelihood sequence estimation equalization circuit using the Viterbi algorithm and information output from the maximum likelihood sequence estimation equalization circuit. A data signal receiving device having a soft-decision error correction code decoding circuit, the branch metric receiving a data signal and outputting a branch metric calculated as a likelihood between the data signal and an equalization result for each state transition. a calculation circuit; an AC3 circuit that updates the path metric by inputting the technique metric and the path metric for each state, and outputs the path metric for each state at the time of updating the path metric and a path memory update control signal; , a path metric storage circuit that stores a path metric for each state at the time of the update, inputs the path metric for each state, selects a maximum likelihood path metric from among the path metrics, and provides the maximum likelihood path metric. In addition to storing and outputting the state, calculating the variance value of the branch metric or path metric at the output point, converting the calculated variance value into a numerical value according to a predetermined rule, and applying the numerical value to the equalization process at the output point. A path metric comparison circuit that outputs an information signal, stores a state series group or a transition series group based on the surviving paths of each state, inputs the path memory update control signal, and inputs the path memory update control signal. update the state sequence group or transition sequence group based on the survival path of each state, and update the oldest state sequence group or transition sequence group among the state sequence group or transition sequence group based on the survival path of each state. a path memory that outputs a group of equalization results; a state that stores the equalization process information signal output from the path metric comparison circuit and provides a maximum likelihood path metric output from the path metric comparison circuit; and the path memory. , select the equalization result corresponding to the maximum likelihood path metric from the equalization result group, and select the equalization result from the oldest equalization process. It is characterized by comprising an equalization result determination circuit that outputs the information signal simultaneously.

A seventh data signal receiving device according to the present invention performs error correction on an input data signal based on a maximum likelihood sequence estimation equalization circuit using the Viterbi algorithm and information output from the maximum likelihood sequence estimation equalization circuit. A data signal receiving device comprising a soft-decision error correction code decoding circuit, wherein the maximum likelihood sequence estimation equalization circuit receives a data signal and calculates a likelihood between the data signal and an equalization result for each state transition. a branch metric calculation circuit that outputs a calculated branch metric, inputs the branch metric and a path metric for each state to update the path metric, and stores a path metric and a path memory for each state at the time the path metric is updated; an ACS circuit that outputs an update control signal; a path metric storage circuit that stores path metrics for each state at the time of the update; and a path metric storage circuit that inputs the path metrics for each state and calculates a maximum likelihood path metric from among the path metrics. Outputting the selected state to give the maximum likelihood path metric, storing the maximum likelihood path metric, and calculating the difference between the maximum likelihood path metric at the output point and the maximum likelihood path metric at a point before the output point. A path metric that calculates a difference between the calculated maximum likelihood path metrics according to a predetermined rule, and outputs the numerical value as an equalization process information signal at the output point at the same time as a state that gives the maximum likelihood path metric. a comparison circuit that stores a state sequence group or a transition sequence group based on the surviving paths of each state, inputs the path memory update control signal, and calculates the survival path of each state based on the path memory update control signal; Update the state sequence group or transition sequence group based on the path, and output the oldest state sequence group or transition sequence group among the state sequence group or transition sequence group based on the surviving path of each state as the equalization result group. a path memory; a state for storing the equalization process information signal output from the path metric comparison circuit and providing a maximum likelihood path metric output from the path metric comparison circuit; and a state for storing the equalization process information signal output from the path metric comparison circuit; Equalization in which a group of results is input, an equalization result corresponding to the maximum likelihood path metric is selected from the group of equalization results, and the equalization result is output simultaneously with the equalization process information signal at the oldest point in time. It is characterized by comprising a result judgment circuit.

(Operation) In order to realize the maximum likelihood sequence estimation equalization method using the Viterbi algorithm, a finite number of states determined by the form of code amount interference of the communication channel is required. In this maximum likelihood sequence estimation equalization method, values of path metrics defined for all states are compared and a state having a path metric indicating maximum likelihood is selected. Then, the past state series or state transition series (maximum likelihood path) leading to the selected state are traced back, and the past state or state transition determined by the length of the path memory is output as the equalization result.

The state with the highest likelihood is defined as the state where the value of the path metric is the maximum or the minimum, depending on the definition of the calculation required to realize maximum likelihood sequence estimation equalization. The definition of the state with the highest likelihood can be uniquely determined in advance by the definition of the operation. Furthermore, the maximum likelihood path can be uniquely expressed using either a state sequence or a state transition sequence. Although the case where a state sequence is used to express the maximum likelihood path will be mainly explained here, the case where the maximum likelihood path is expressed using a state transition sequence can be considered in the same way. Here, the state obtained as the equalization result from the maximum likelihood path will be referred to as the maximum likelihood state.

In the conventional method using maximum likelihood sequence estimation equalization, only the above-mentioned maximum likelihood state is output as the equalization result, so only hard-decision output can be obtained, and error correction decoding uses 0 channels where only hard-decision decoding is possible. If the distortion in is relatively small and the length of the path memory is long enough, the surviving paths that reach all states will be recombined, and the most recent states in each surviving path will match. Therefore, the equalization results obtained from all surviving paths are equal, and sufficient characteristics can be obtained even when hard-decision decoding is performed.

However, when the distortion in the communication path increases, there are cases where the surviving paths that reach all states do not recombine. At this time, the most past states of each surviving path obtained as the equalization result are different 0
In such a case, the present invention estimates the reliability of the maximum likelihood state output as an equalization result in the following manner.

(1) The first data signal receiving device according to the present M invention is characterized by the number of surviving paths that give the same equalization result as the maximum likelihood path among the current surviving paths (maximum likelihood path support rate); The second data signal receiving device determines whether the current maximum likelihood path is a path that has transitioned from the maximum likelihood state at the previous point in time (current continuity of the maximum likelihood path). The data signal receiving device No. 3 determines whether or not the state sequence at the oldest point selected at the present moment is continuous with the state sequence at the oldest point selected one point before the present moment (the transition of the oldest state). Continuity) (4) The fourth data signal receiving device according to the present invention determines the number of paths that have transitioned from the maximum likelihood state at the previous time among the current surviving paths. (5) The fifth data according to the present invention The signal receiving device detects the difference (6) between the path metric of the path with the maximum likelihood and the path metric of the path with the minimum likelihood, or the path metric of another path, or the average value of the path metrics of all surviving paths. The sixth data signal receiving device according to the present invention (a) calculates the branch metric variance value or the path metric variance value (7). therefore,
Converting not only the maximum likelihood state as an equalization result but also the degree of reliability of the maximum likelihood state obtained by each data signal receiving device described above into a numerical expression, and simultaneously providing the numerical expression as an input to an error correction code decoding circuit. By this, it is possible to achieve the same effect as soft decision decoding. Similarly, when expressing the maximum likelihood path using state transitions, soft-decision decoding is performed by providing a numerical representation of the reliability of the equalization result and the maximum likelihood state transition as input to the error correction code decoding circuit. It is possible to achieve a similar effect.

As described above, the equalization process of the maximum likelihood sequence estimation equalization circuit generally depends largely on the distortion that occurs in the data signal in the communication channel. Since the equalization result obtained as the output of the maximum likelihood estimation equalization circuit is only the result of a hard decision, its reliability varies greatly depending on the equalization process performed by the maximum likelihood sequence estimation equalization circuit. Therefore, not only the hard-decision equalization result (maximum likelihood state) is output as the output of the maximum likelihood estimation equalization circuit, but also information on the equalization process obtained from the internal state of the equalization circuit is simultaneously output to the soft-decision error correction decoding circuit. if,
Soft-decision error correction becomes possible, and the correction ability of the error correction code can be fully utilized.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data signal receiving system according to the present invention. The maximum likelihood sequence estimation equalization means using the Viterbi algorithm includes a branch metric calculation circuit 102 and AC9 (Ad(ICon+pare an
d5elect) circuit 103 and a path memory 104. In such a configuration, equalization results are obtained as follows. The AD-converted data signal is input to the branch metric calculation circuit 102 via the input terminal 101. The branch metric calculation circuit 102 calculates a branch metric corresponding to each state transition based on the input signal and outputs it to the ACS circuit 103. The ACS circuit 103 sets the path metric of each state so that the likelihood of the surviving path reaching each current state is the highest, and also sends a path memory update control signal to the path memory 104 and the current maximum likelihood surviving path. Survival path (
A surviving path selection signal indicating the maximum likelihood path) is output.

The path memory 104 updates the surviving paths that reach each state based on the path memory update control signal, and decodes the soft-decision error correction code using the oldest value of the maximum likelihood path obtained from the surviving path selection signal as an equalization result. circuit 106
Output to.

In the case of the configuration shown in FIG. 1, the following information is available as information on the equalization process necessary to perform the soft decision.

(1) Branch metric corresponding to each state transition (output of branch metric calculation circuit 102) (2) Path metric of each state (calculation result of ACS circuit 103) (3) Equalization result obtained from all surviving paths ( Past output of path memory 104) Additional information processing circuit 1
05 inputs the information (1) to (3) described above, processes it to indicate the reliability of the equalization result, and then outputs it to the soft-decision error correction code decoding circuit 106. The soft-decision error correction code decoding circuit 106 performs soft-decision error correction based on the outputs of the path memory 104 and the additional information processing circuit 105, and outputs the determination result to the output terminal 107.

FIG. 2 is a block diagram showing an embodiment of the first data signal receiving device according to the present invention.

An AD-converted burst data signal is input to the input terminal 201 . A memory 202 connected to the input terminal 201 stores all data signals input to the input terminal 201. When the memory 202 has stored all the input data signals, the control circuit 211 controls the switch 203 and converts the memory 202 and the communication channel characteristic estimation diagram at! ! 204
2 communication channel characteristic estimating circuit that establishes a connection with the communication channel characteristic estimation circuit 204, further supplies a clock signal to the memory 202, and outputs the data signal stored in the memory 202 to the communication channel characteristic estimation circuit 204! ! 204 estimates the channel characteristics using the data signal supplied from the memory 202, outputs the estimation result to the branch metric calculation circuit 205, and also outputs the estimation result to the branch metric calculation circuit 205.
An estimation completion signal is output to 11. When the control circuit 211 receives the estimation end signal from the channel characteristic estimation circuit 204, it controls the switch 203 to establish a connection between the memory 202 and the branch metric calculation circuit 205, and
A clock signal is supplied to 02. The memory 202 outputs a stored data signal to the branch metric calculation circuit 205 based on this clock signal. The branch metric calculation circuit 205 is a channel characteristic estimation circuit 204.
inputs the estimation result from 202 and the data signal from the memory 202, calculates the branch metric corresponding to each state transition based on these two signals, and outputs the branch metric corresponding to each state transition to the ACS @ path 206. do.

The ACS circuit 206 has a branch metric calculation port R2O.
5, and outputs the path metric and path memory update signal of each state to the path metric comparison circuit 207 and the path memory 208, respectively. The pathmetry/yield comparison circuit 207 compares the input pathmetrics, selects the state with the maximum value, and outputs it to the equalization result determination circuit 209. The path memory 208 updates the surviving paths in each state based on the path memory update signal from the ACS circuit 206, and updates the oldest state of each surviving path to the equalization result determination circuit 2.
Output on 09. The path memory 208 stores state transition sequences to identify each surviving path. For example, in the case of binary transmission in which 0 or 1 is transmitted, for each state, (1) Transition (2) Only two types of transitions occur: transitions due to input 1. Therefore, by storing only the input (1 bit) that causes a transition in the path memory 208, it is possible to uniquely specify the surviving path reached by each state. Here, assuming that the number of states is 16 and the length of the path memory is 32, the capacity of the path memory 208 is required to be 1 bit x 16 x 32 = 512 bits.

The equalization result determination circuit 209 includes the path metric comparison circuit 2
Based on the signal output from 07, the equalization result obtained from the maximum likelihood path and the number of surviving paths showing the same result as the equalization result obtained from the maximum likelihood path are output to the soft-decision error correction code decoding circuit 210. . Soft decision error correction code decoding circuit 2
For example, when binary transmission is performed and four-level soft decision error correction is used, 10 is the equalization result (1 bit) obtained from the maximum likelihood path using the signal output from the equalization result determination circuit 209. , using 2 bits of information (1 bit) to determine whether the equalization result obtained from the maximum likelihood path and the number of surviving paths giving equal equalization results exceed half of the total number of surviving paths. Performs four-level soft decision error correction. After performing error correction based on the input data, the soft-decision error correction code decoding circuit 210 transmits the decoding result to the output terminal 21.
Output to 2.

In the embodiment shown in FIG. 2, the information for performing the soft decision is the surviving path that gives an equalization result equal to the equalization result obtained from the maximum likelihood path, using a majority of the total number of surviving paths as a threshold value. Although information on whether the number exceeds a threshold is used, the threshold does not necessarily need to be set to a majority of the total number of surviving paths. In addition, in this example, the number of paths that give the same equalization result as the maximum likelihood path was counted among all surviving paths. The number of paths that give the same equalization result as the maximum likelihood path may be counted only for a plurality of paths selected according to the rule that only paths in .

3, 4, 5, 6, 7, and 8 show the second, third, fourth, fifth, sixth, and seventh data signal reception according to the present invention, respectively. FIG. 1 is a block diagram showing one embodiment of the device. In these six examples, the second
The difference from the embodiment of the first data signal receiving device according to the present invention shown in the figure is the function of the equalization result determination circuit. The equalization result determination circuit 209 in FIG. 2 calculates the equalization result and its reliability information based on the number of surviving paths that give the same equalization result as the maximum likelihood path (maximum likelihood path support rate) among the current surviving paths. In each of the embodiments of the second, third, fourth, fifth, sixth and seventh data signal receiving devices according to the invention, which are equalization result determination circuits that convert into numerical values, the following rules are used. The reliability information is digitized to give a soft-decision equalization result, and the soft-decision equalization result is created and supplied to the next located soft-decision error correction code decoding circuit (corresponding to 310 to 810, respectively).

The equalization result determination circuit R309 in FIG. 3 is an equalization result determination circuit that increases reliability when the current maximum likelihood path is a path that has transitioned from the maximum likelihood state at the previous time.

The equalization result determination circuit 409 in FIG. 4 has high reliability when the state series at the oldest point selected at the present time and the state series at the oldest point selected one point before the present time are continuous. This is an equalization result determination circuit.

The equalization result determination circuit 509 in FIG. 5 is an equalization result determination circuit that increases reliability as the number of paths that have transitioned from the maximum likelihood state at the previous point in time among the current surviving paths increases.

The equalization result determination circuit 609 in FIG. This is an equalization result determination circuit that increases reliability as the value increases.

The equalization result determination circuit 709 in FIG. 7 is an equalization result determination circuit that lowers the reliability as the branch metric variance value or the path metric variance value decreases.

The equalization result determination circuit 809 in FIG. 8 is an equalization result determination circuit that increases reliability as the increment value of the current path metric of the maximum likelihood path is larger than the increment value of other surviving paths.

Although the embodiments described above are applied to signals transmitted in bursts, the present invention can be similarly applied to signals transmitted continuously. In addition, each embodiment has been explained using binary transmission as an example, but
It is also possible to easily adapt to multilevel transmission.

In addition, in each of these embodiments, a case has been described in which a transition sequence group is stored in a path memory, but a case in which a state sequence group is stored in a path memory can also be realized in a similar manner.

FIG. 9 shows an example of the error rate characteristic limit of soft-decision decoding realized by the present invention and the error rate characteristic of a conventional method using hard-decision decoding. This is an example in which a convolutional code with a 21 constraint length of 7 and maximum likelihood sequence estimation equalization are used simultaneously, and the communication channel is a 2-wave Rayleigh model with a 3T delay. Curve 901 is the error rate characteristic immediately after maximum likelihood sequence estimation equalization, and curve 9.2 is the error rate characteristic during conventional hard decision decoding. For these, 3
The error rate characteristic in the case of ffi soft decision decoding is shown by a curve 903. Therefore, in this example, the soft decision decoding realized by the present invention can provide a maximum gain of 5 dB at an error rate of 1o-3.

(Effects of the Invention) As shown in the example of FIG. 9, according to the present invention, a maximum likelihood sequence estimation equalization method and an error correction code are simultaneously used to treat data signals transmitted over a communication channel where code amount interference occurs. When performing error correction, the correction ability can be improved and highly reliable data transmission may be possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a data signal receiving system according to the present invention, FIG. 2 is a block diagram showing an embodiment of a first data signal receiving device according to the present invention, and FIG. 3 is a block diagram showing an embodiment of a first data signal receiving device according to the present invention. FIG. 4 is a block diagram showing an embodiment of the second data signal receiving device according to the invention, FIG. 4 is a block diagram showing an embodiment of the third data signal receiving device according to the invention, and FIG. FIG. 6 is a block diagram showing an embodiment of the fourth data signal receiving device according to the present M invention, and FIG. 7 is a block diagram showing an embodiment of the fifth data signal receiving device according to the present invention. FIG. 8 is a block diagram showing an embodiment of the sixth data signal receiving device according to the present invention, FIG. 9 is a block diagram showing an embodiment of the seventh data signal receiving device according to the present invention, and FIG. FIG. 6 is a diagram illustrating the error normal time forward side for explaining the effect of soft decision decoding to be used. 101.201, 301, 401, 501, 601.7
01,801...Input terminal, 102,205.305
, 405, 505, 605, 705° 805... Branch metric calculation circuit, 103° 206. 306, 4
06,506,606.706.806...ACS circuit, 104,208,308.408,508,608
, 708, 808... path memory, 105... additional information processing circuit, 106... soft decision error correction circuit, 10
7,212,312412.512,612,712,
812...output terminal, 202, 302, 402, 50
2,602°702.802...Memory, 203,3
03 403.503,603,703,803...
switch, 204.304,404,504,604
704.804...Communication channel characteristic estimation circuit, 207,3
07.407,507,607.707 807...
Path metric comparison circuit, 209, 309, 409.5
09,609,709,809...equalization result determination circuit, 210,310,410,510,610.710,
810...Soft decision error correction code decoding circuit, 211,3
11,411,511,611゜711.811...
Control circuit, 901...Error peacetime curve when maximum likelihood sequence estimation equalization, 902...Error peacetimeness curve when maximum likelihood sequence estimation equalization and hard decision decoding are combined, 903...Maximum likelihood sequence estimation Error peacetime curve when equalization and soft decision decoding are used together.

Claims (8)

[Claims] (1) In a data signal receiving system that performs error correction of an input data signal using maximum likelihood sequence estimation equalization means and soft-decision error correction code decoding means using the Viterbi algorithm, the soft-decision error correction code decoding means comprises: The data is calculated by the equalization result obtained from the maximum likelihood sequence estimation equalization means and the information on the equalization process in the maximum likelihood sequence estimation equalization means obtained by observing the internal state of the maximum likelihood sequence estimation equalization means. A data signal reception method characterized by signal error correction. (2) It has a maximum likelihood sequence estimation equalization circuit that uses the Viterbi algorithm and a soft-decision error correction code decoding circuit that performs error correction of an input data signal based on the information output from the maximum likelihood sequence estimation equalization circuit. In the data signal receiving device, the maximum likelihood sequence estimation equalization circuit is a branch metric calculation circuit that receives a data signal and outputs a branch metric calculated as a likelihood between the data signal and the equalization result for each state transition. and an ACS circuit that updates the path metric by inputting the branch metric and the path metric for each state, and outputs the path metric and path memory update control signal for each state at the time the path metric is updated; a path metric storage circuit that stores a path metric for each state at the time of update; and a path metric storage circuit that inputs the path metric for each state, selects a maximum likelihood path metric from among the path metrics, and selects a state that gives the maximum likelihood path metric. A path metric comparison circuit to output, stores a state sequence group or a transition sequence group based on the surviving paths of each state, inputs the path memory update control signal, and performs a process based on the path memory update control signal. Update the state sequence group or transition sequence group based on the survival path of each state, and equalize the oldest state sequence group or transition sequence group among the state sequence group or transition sequence group based on the survival path of each state. A path memory that outputs a result group; and inputs the state output from the path trick comparison circuit and the equalization result group, and corresponds to the state output from the path metric comparison circuit from among the equalization result group. Selects and outputs the equalization results to be calculated, and also selects and outputs the equalization results for all of the surviving paths from the equalization results group, or for a plurality of paths selected from the equalization results group according to a predetermined rule. , count the number of equalization results that give the same result as the equalization result, convert the number of equalization results into a numerical value according to a predetermined rule, and simultaneously output the equalization result as an equalization process information signal. A data signal receiving device comprising: an equalization result determination circuit that outputs an output; (3) It has a maximum likelihood sequence estimation equalization circuit that uses the Viterbi algorithm and a soft-decision error correction code decoding circuit that performs error correction of an input data signal based on the information output from the maximum likelihood sequence estimation equalization circuit. In the data signal receiving device, the maximum likelihood sequence estimation equalization circuit is a branch metric calculation circuit that receives a data signal and outputs a branch metric calculated as a likelihood between the data signal and the equalization result for each state transition. , an ACS circuit that updates the path metric by inputting the branch metric and a path metric for each state, and outputs a path metric and a path memory update control signal for each state at the time the path metric is updated; a path metric storage circuit that stores a path metric for each state at a time; and a path metric storage circuit that inputs the path metric for each state, selects a maximum likelihood path metric from among the path metrics, and stores a state that provides the maximum likelihood path metric. path metric comparison that outputs information on whether the maximum likelihood path at the output point has transitioned from the maximum likelihood state one point before the output point (continuity information of the maximum likelihood path). A circuit, storing a state sequence group or a transition sequence group based on the surviving paths of each state, inputting the path memory update control signal, and determining the surviving path of each state based on the path memory update control signal. A path memory that updates a state sequence group or a transition sequence group based on the survival path of each state and outputs the oldest state sequence or transition sequence group as an equalization result group among the state sequence group or transition sequence group based on the survival path of each state. and storing continuity information of the maximum likelihood path output from the path metric comparison circuit, and storing continuity information of the maximum likelihood path output from the path metric comparison circuit, and a state that provides the maximum likelihood path metric output from the path metric comparison circuit, and the equalization information output from the path memory. result group and selects and outputs the equalization result corresponding to the maximum likelihood path metric from the equalization result group, and also outputs continuity information of the oldest maximum likelihood path as equalization process information at that point. A data signal receiving device comprising: an equalization result determination circuit that simultaneously outputs the equalization result as a signal. (4) It has a maximum likelihood sequence estimation equalization circuit that uses the Viterbi algorithm and a soft-decision error correction code decoding circuit that performs error correction of an input data signal based on the information output from the maximum likelihood sequence estimation equalization circuit. In the data signal receiving device, the maximum likelihood sequence estimation equalization circuit is a branch metric calculation circuit that receives a data signal and outputs a branch metric calculated as a likelihood between the data signal and the equalization result for each state transition. and an ACS circuit that updates the path metric by inputting the branch metric and the path metric for each state, and outputs the path metric and path memory update control signal for each state at the time the path metric is updated; a path metric storage circuit that stores path metrics for each state at the time of update; and a path that inputs the path metrics for each state, selects a maximum likelihood path metric from among the path metrics, and outputs the maximum likelihood path metric. A metric comparison circuit stores a state sequence group or a transition sequence group based on the surviving paths of each state, inputs the path memory update control signal, and calculates the state sequence group of each state based on the path memory update control signal. Update the state sequence group or transition sequence group based on the surviving path, and output the oldest state sequence group or transition sequence group among the state sequence group or transition sequence group based on the surviving path of each state as the equalization result group. a path memory that provides a maximum likelihood path metric outputted from the path metric comparison circuit, and the equalization result group outputted from the path memory, and selects the most likely path metric from among the equalization result group. Selects and outputs the equalization result corresponding to the oldest point in time of the likelihood path metric, stores the state series at the oldest point corresponding to the equalization result, and stores the state series selected one point before the output point. Simultaneously with the equalization result, information indicating whether or not the state sequence at the oldest point in time and the state sequence at the oldest point in time selected at the output point in time are continuous, as an equalization process information signal at that point in time. A data signal receiving device comprising: an equalization result determination circuit that outputs an equalization result. (5) It has a maximum likelihood sequence estimation equalization circuit that uses the Viterbi algorithm and a soft-decision error correction code decoding circuit that performs error correction of an input data signal based on the information output from the maximum likelihood sequence estimation equalization circuit. In the data signal receiving device, the maximum likelihood sequence estimation equalization circuit is a branch metric calculation circuit that receives a data signal and outputs a branch metric calculated as a likelihood between the data signal and the equalization result for each state transition. and an ACS circuit that updates the path metric by inputting the branch metric and the path metric for each state, and outputs the path metric and path memory update control signal for each state at the time the path metric is updated; a path metric storage circuit that stores path metrics for each state at the time of update; and a path that inputs the path metrics for each state, selects a maximum likelihood path metric from among the path metrics, and outputs the maximum likelihood path metric. A metric comparison circuit stores a state sequence group or a transition sequence group based on the surviving paths of each state, inputs the path memory update control signal, and calculates the state sequence group of each state based on the path memory update control signal. Update the state sequence group or transition sequence group based on the surviving path, and output the oldest state sequence group or transition sequence group among the state sequence group or transition sequence group based on the surviving path of each state as the equalization result group. a path memory that provides a maximum likelihood path metric outputted from the path metric comparison circuit, and the equalization result group outputted from the path memory, and selects the most likely path metric from among the equalization result group. Select and output the equalization result corresponding to the likelihood path metric, and count the number of surviving paths that are continuous from the maximum likelihood path one point before the output time for the surviving paths at the output time, and calculate the maximum likelihood path from the output time. The number of continuous remaining paths from the likely path is converted into a numerical value according to a predetermined rule, and the numerical value is stored as the equalization process information signal at the output time, and the oldest equalization process information signal is A data signal receiving device comprising: an equalization result determination circuit that outputs equalization results simultaneously; (6) It has a maximum likelihood sequence estimation equalization circuit that uses the Viterbi algorithm and a soft-decision error correction code decoding circuit that performs error correction of an input data signal based on the information output from the maximum likelihood sequence estimation equalization circuit. In the data signal receiving device, the maximum likelihood sequence estimation equalization circuit is a branch metric calculation circuit that receives a data signal and outputs a branch metric calculated as a likelihood between the data signal and the equalization result for each state transition. and an ACS circuit that updates the path metric by inputting the branch metric and the path metric for each state, and outputs the path metric and path memory update control signal for each state at the time the path metric is updated; a path metric storage circuit that stores a path metric for each state at the time of update; and a path metric storage circuit that inputs the path metric for each state, selects a maximum likelihood path metric from among the path metrics, and selects a state that gives the maximum likelihood path metric. In addition to storing and outputting, the value of the difference between the maximum likelihood path metric at the time of output and the path metric of the path selected according to predetermined rules, or the difference between the average value of all path metrics, is calculated. a path metric comparison circuit that numerically converts the difference value according to a predetermined rule and outputs the numerical value as an equalization process information signal at the output time; and a state series or transition series based on the surviving paths of each state. group, and input the path memory update control signal to update the state sequence group or transition sequence group based on the surviving path of each state based on the path memory update control signal, and a path memory that outputs the oldest state sequence group or transition sequence group as an equalization result group among the state sequence group or transition sequence group based on the surviving paths; and the equalization process information signal output from the path metric comparison circuit. , inputs the state giving the maximum likelihood path metric output from the path metric comparison circuit and the equalization result group output from the path memory, and selects the maximum likelihood path from the equalization result group. A data signal receiving device comprising: an equalization result determination circuit that selects an equalization result corresponding to a metric and outputs the equalization result simultaneously with an equalization process information signal at the oldest point in time. (7) It has a maximum likelihood sequence estimation equalization circuit using the Viterbi algorithm and a soft-decision error correction code decoding circuit that performs error correction of an input data signal based on the information output from the maximum likelihood sequence estimation equalization circuit. A data signal receiving device includes a branch metric calculation circuit that inputs a data signal and outputs a branch metric calculated as a likelihood between the data signal and an equalization result for each state transition, and a path for the branch metric and each state. an ACS circuit that updates the path metric by inputting a metric and outputs a path metric and a path memory update control signal for each state at the time of updating the path metric; and an ACS circuit that stores the path metric for each state at the time of updating. a path metric storage circuit that inputs the path metric for each of the states, selects the maximum likelihood path metric from among the path metrics, stores and outputs the state that gives the maximum likelihood path metric, and stores and outputs the state that gives the maximum likelihood path metric; a path metric comparison circuit that calculates a variance value of a branch metric or a path metric, converts the calculated variance value into a numerical value according to a predetermined rule, and outputs the numerical value as an equalization process information signal at the output time; A state sequence group or a transition sequence group based on the surviving path of each state is stored, and the path memory update control signal is input to create a state based on the surviving path of each state based on the path memory update control signal. a path memory that updates a sequence group or a transition sequence group and outputs the oldest state sequence group or transition sequence group as an equalization result group among the state sequence group or transition sequence group based on the surviving path of each state; storing the equalization process information signal output from the path metric comparison circuit, and inputting a state giving a maximum likelihood path metric output from the path metric comparison circuit and the equalization result group output from the path memory; an equalization result determination circuit that selects an equalization result corresponding to the maximum likelihood path metric from the equalization result group and outputs the equalization result simultaneously with the oldest equalization process information signal; A data signal receiving device comprising: (8) It has a maximum likelihood sequence estimation equalization circuit that uses the Viterbi algorithm and a soft-decision error correction code decoding circuit that performs error correction of an input data signal based on the information output from the maximum likelihood sequence estimation equalization circuit. In the data signal receiving device, the maximum likelihood sequence estimation equalization circuit is a branch metric calculation circuit that receives a data signal and outputs a branch metric calculated as a likelihood between the data signal and the equalization result for each state transition. and an ACS circuit that updates the path metric by inputting the branch metric and the path metric for each state, and outputs the path metric and path memory update control signal for each state at the time the path metric is updated; a path metric storage circuit that stores a path metric for each state at the time of update; and a path metric storage circuit that inputs the path metric for each state, selects a maximum likelihood path metric from among the path metrics, and selects a state that gives the maximum likelihood path metric. outputting the maximum likelihood path metric, storing the maximum likelihood path metric, calculating the difference between the maximum likelihood path metric at the output point and the maximum likelihood path metric one point before the output point, and calculating the difference between the calculated maximum likelihood path metrics; a path metric comparison circuit that converts the numerical value into a numerical value according to a predetermined rule and outputs the numerical value as an equalization process information signal at the output time simultaneously with the state giving the maximum likelihood path metric, based on the surviving path of each of the states. A state sequence group or a transition sequence group is stored, and an update control signal is input to the path memory, and a state sequence group or a transition sequence group based on the surviving path of each state is generated based on the path memory update control signal. and outputs the oldest state sequence group or transition sequence group as an equalization result group among the state sequence group or transition sequence group based on the surviving paths of each state; and the output from the path metric comparison circuit. input the state giving the maximum likelihood path metric output from the path metric comparison circuit and the equalization result group output from the path memory; an equalization result determination circuit that selects an equalization result corresponding to the maximum likelihood path metric from among the group and outputs the equalization result simultaneously with the equalization process information signal at the oldest point in time; data signal receiving device.