JPH03282667A - Computer device - Google Patents

Abstract

PURPOSE:To evade the extension of an integrated circuit and to prevent the large power consumption by transferring the data between a data memory and a peripheral device in a period when a CPU has no access to the data memory during one instruction of the CPU and via an exclusive data bus not via a data bus. CONSTITUTION:A CPU 1 receives an instruction from an instruction memory 7 via a bus 6 and has an access to a data memory 2 or a peripheral device 3 via a data bus 4 in response to the instruction. Then the data are transferred between the device 3 and the memory 2 via an exclusive data bus 5 in a period when the CPU 1 has no access to the memory 2 during one instruction of the CPU 1. Thus it is possible to transfer a large quantity of data to the device 3 from the memory 2 without deteriorating the executing speed of the CPU 1 nor the processing speed of the device 3. Then the CPU 1 is never expanded and the large power consumption can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a computer device having a central processing unit (hereinafter referred to as CPU), memory, and other peripheral devices. own CPU
The present invention relates to a computer device capable of accessing data memory of a computer.

[Conventional technology]

In a conventional computer device that integrates a CPU, memory, and peripheral devices, one data bus is connected to the CPU as shown in Figure 2.
21, data memory 221 is shared by the peripheral device 23; Data bus 24 is connected from CPU 21 to data memory 2.
2, when the CPU 21 accesses the peripheral device 23, and when the peripheral device 23 accesses the data memory 22. CPU21 is data
The cases in which the memory 22 is accessed and the cases in which the CPU 21 accesses the peripheral device 23 correspond to instructions from the CPU 21. However, when the peripheral device 23 accesses the data memory 22, there are cases where the peripheral device 23 responds to instructions from the CPU 21, and cases where the peripheral device 23 independently requires data from the data memory 22, regardless of the instructions from the CPU 21 for its operation. There are cases. The latter is called a direct memory access operation (hereinafter referred to as a DMA operation).

The DMA operation is used when it is necessary to transfer a larger amount of data from the data memory 22 to the peripheral device 23 in a short time than the amount transferred from the data memory 22 to the peripheral device 23 with one command from the CPU 21. Ru.

Normally, if the CPU 21 is an 8-bit CPU, it is 1
The amount of data that can be transferred from data memory 22 to peripheral device 23 with a command is about 8 bits.

For example, the peripheral device 23
If 2 bits are required, it is better for the peripheral device 23 to directly access the data memory 22 without going through the data memory access operation of the CPU 21, since the peripheral device 23 accesses it four times during one instruction of the CPU 21 at its own timing. Because it's good.

When performing a DMA operation, data controlled by the CPU 21 and data controlled by the peripheral device 23 are transferred to the data bus 24.
The operation of the CPU 21 is stopped so as not to interfere with each other, and the data bus 24 is opened to the peripheral devices 23. The peripheral device 23 sends a DMA operation request 25 to the CPU 21, and
U21 puts the DMA operation into a state where it can be executed, releases the data bus 24, sends a DMA enable signal 26 to the peripheral device 23, and stops the operation until a DMA operation cancel signal 27 is issued from the peripheral device 23.

[Problem to be solved by the invention]

Since the DMA operation uses the data bus 24 in FIG. 2 to transfer data to the peripheral device 23, the CPU operation must be stopped during the DMA operation, which reduces the apparent CPU processing speed. Figure 3 shows the situation.

A in FIG. 3 shows the operation timing of the CPU when there is no DMA operation. B in FIG. 3 is a case where a DMA operation is executed every other CPU instruction. For example, if the CPU instruction execution time is 2μ seconds and the time required for DMA operation is also 2μ seconds, then in Figure 3A, the CPU instruction execution time is 2μ seconds.
However, in B of FIG. 3, the instruction execution time of the CPU appears to be 4 microseconds.

Further, in the above example, the DMA operation time is the same as the execution time of one instruction by the CPU, but it may take even longer depending on the processing content of the peripheral device. In other words, the CPU
Because the data bus used for data processing and the data bus used by peripheral devices are the same,
This is because the DMA operation period increases if data several times the bit width of the bus is transferred to the peripheral device.

Furthermore, if the processing content of the peripheral device is asynchronous with the CPU operation, even if a DMA operation request is issued from the peripheral device, the CPU
Depending on the operating status of U, the DMA operation permission signal may not be sent from the CPU immediately and the operation of the peripheral devices may stop during that time.

- When using DMA operations, there may be cases where both the processing speed of the CPU and the processing speed of peripheral devices become slow.

The faster the execution processing speed that a device external to the computer requires of the computer, the more disadvantageous it becomes. Furthermore, in order to increase the execution processing speed with such a configuration, it is necessary to increase the processing speed of the CPU itself. If the CPLI is an integrated circuit, the size of the internal transistors must be increased, leading to an enlargement of the integrated circuit, which also results in increased power consumption.

[Means to solve the problem]

The computer device of the present invention includes a central processing unit, an instruction memory, a data memory, and a peripheral circuit, and an instruction bus connected to the instruction memory and a first data bus connected to the central processing unit.
a bus is connected to the data memory, a first data bus and a second data bus are connected, the second data bus is connected to the peripheral circuit, and the data memory has a first data bus connected to the peripheral circuit; The data transfer is performed via the second data bus during the period when the central processing unit is not accessing the data memory during the instruction cycle of the central processing unit.

The period during the instruction cycle of the central processing unit when the data memory is not accessed by the central processing unit is a dedicated period during the instruction cycle.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The CPU receives instructions from the instruction memory 7 via the instruction bus 8 and accesses the data memory 2 or the peripheral device 3 via the data bus 4 in accordance with the instructions. Data transfer between peripheral device 3 and data memory 2 takes place via a dedicated data bus 5. The data memory 2 has input/output devices for a data bus 4 and an input/output device for a dedicated data bus 5. In addition, the data on the dedicated data bus 5 and data bus 4
The bit widths are different, and the data bit width of the dedicated data bus 5 is larger.

FIG. 5 shows the operating status of the CPU 1 during one instruction.

Each CPUI instruction is divided into four timings, and the data memory 2 can only be accessed once at each timing. During timing 51, the CPUI is not connected to data.
Memory 2 is not accessed, timing 52, 53.54
Then, CPU 1 accesses data memory 2.

For example, if data bus 4 is 8 bits, the dedicated data
The bus 5 is assumed to be 32 bits, and the cycle of one instruction of the CPU 1 is assumed to be 2 μsec. Currently, CPU 1 is operating, peripheral device 3
is operating asynchronously with CPU1. It is assumed that the peripheral device 3 requires 32 bits of data every 2 microseconds due to its operation. Peripheral device 3 accesses data memory 2 via dedicated data bus 5 during timing 52 during the CPU 1 instruction cycle. Unlike the data bus 4, the dedicated data bus 5 has a bit width of 32 bits, so 32 bits of data can be transferred from the data memory 2 at a time, and at timing 51, peripheral devices are always transferred while the CPU is operating. 3 and data memory 2, the data memory 2 only needs to be accessed once.

Furthermore, there is no need for the peripheral device 3 to obtain permission from the CPU 1 when transferring data from the data memory 2.

FIG. 4 shows another embodiment of the invention. The difference from the previous embodiment is that the data memory 42 has only two data input/output devices, and it is determined whether either the dedicated data bus 45 or the data bus 44 is connected to the input/output device of the data memory 42. There is a bus switching device 48 for switching. The bit width of the data in the pig memory 420 input/output device is the same as the bit width of the dedicated data bus. The bus switching device 48 is controlled by a switching control signal 49, and when the switching control signal 49 goes high, the data input/output device of the data memory 42 receives dedicated data.
It is connected to the bus 45, and when it goes low, it is connected to the data bus 44.

FIG. 5C shows the timing of the switching control signal 48.

9. The switching control signal 49 goes to no level at timing 51 and goes to low level at timings 52, 53, and 54, so other operations are the same as in the previous embodiment.

〔Effect of the invention〕

In this way, data transfer between data memory and peripheral devices is
By using the dedicated data bus instead of the data bus during the period when the CPU does not access data memory during one instruction of the PU, the execution speed of the CPU does not decrease, and the processing speed of peripheral devices also increases. Large amounts of data can be transferred from data memory to peripheral devices without deteriorating the CP.
Expansion of U and large power consumption can be prevented.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of the prior art, FIG. 3 is a timing explanation of the prior art, FIG. 4 is a block diagram of another embodiment of the present invention, and FIG. FIG. 5 is a timing explanation of the embodiment of FIG. 1 and the embodiment of FIG. 4. 0 28...Instruction bus,...Instruction memory, 46...Instruction bus, 7...Instruction memory.

Claims (1)

[Claims] 1. In a computer device having a central processing unit, an instruction memory, a data memory, and a peripheral circuit, the central processing unit has an instruction bus connected to the instruction memory, and a first data bus connected to the instruction memory. a first data bus and a second data bus are connected to the data memory, the second data bus is connected to the peripheral circuit, and the data memory is connected to the peripheral circuit; A computer device characterized in that data transfer between the central processing unit and the data memory is performed via a second data bus during a period when the central processing unit is not accessing the data memory during an instruction cycle of the central processing unit. 2. The period in which the central processing unit is not accessing the data memory during the instruction cycle of the central processing unit as set forth in item 1 above is a period provided exclusively during the instruction cycle. computer equipment.