JPH0327631A - Selective call receiver - Google Patents

Abstract

PURPOSE:To always attain reception at a frequency with the highest electric field and to shorten the detection time by detecting the electric field strength while using the number of regular bit change points as a parameter and switching plural frequencies. CONSTITUTION:When a frequency received precedingly is f1, a f1 data is set to a PLL oscillation section 44 by a control section 40 to attain the reception of the signal f1. At first the result of a secondary comparator 17 is decided and when OK, it is decided that the electric field at the frequency f1 is strong and the signal with the frequency f1 is received. When the result of the comparator 17 is NG, the result of a primary comparator 16 is decided and when OK, a flag is set and when NG, a f2 data is set as it is to the oscillation section 44. With frequency f2 is received, the result of a comparator circuit 17 is decided, and when OK, the signal with the frequency f2 is used for the reception. When NG, the flag is checked, and when the flag is not set, the f1 data is sent to the oscillator 44 and the signal with the frequency f1 is received. When the flag is not set, the signal with the frequency f2 is used, the result of the comparator 16 is decided and when OK, the signal with the frequency f2 is received.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a selective call receiving device that switches and uses a plurality of receiving frequencies. (Prior Art) Conventionally, this type of selective call receiving apparatus supports, for example, a signaling system as shown in FIG. The signaling system shown in Figure 2 divides one frame into 15 groups, each group consisting of one synchronization word and eight selective call words, and the synchronization word is a frame synchronization signal common to each group and a group identification signal. The selective call word consists of 31 bits including the group signal for the
It is a CH (31, 16) code, and consists of a code that excludes all O's and all 1's. FIG. 3 shows an example of the configuration of a conventional selective call receiving device. In the same figure, a signal received by an antenna 31 and a receiving section 32 is converted into an NRZ signal by a waveform shaping section 33, and a bit synchronization section 34 performs pit synchronization between the internal clock of a clock generation section 35 and the input signal to perform frame synchronization. The detecting section 36 receives the frame synchronization signal, the group signal detecting section 37 receives the group signal, and then the paging signal detecting section 38 compares and detects the self paging signal based on data from the ROM 39 and the control section 40. If so, the speaker 42 is driven through the buffer section 41 to notify the user of the call. On the other hand, depending on the reception status of the frame synchronization signal and the group synchronization signal, the control section 40 and the battery saving control section 43
Power is controlled to be intermittently supplied to the receiving unit 32, etc., and the control unit 4
From 0. Data corresponding to the local oscillation frequency is sent to the PLL oscillator 44 to control the reception frequency of the receiver 32.
45 is a battery. Next, the switching operation of multiple channels will be explained according to FIG. Two rounds of f1 and f3 from the base station? For example, when the selective calling receiver receives the frequency f1 for the signal (a) that is transmitted at a frequency of Send f■ data and try to receive a frame synchronization signal at f. If the frame synchronization signal can be received, then turn off the battery saving and try to receive the own gnorep signal, and if the signal can be received, turn on the battery saving at the end of the own group. On the other hand, the case where the electric field of f1 is very weak and f2 is strong is (mouth). Similar to (a), an attempt is made to receive the frame synchronization signal at f1, but if the electric field is too weak to receive it, for example, f2 data for receiving the f2 frequency is sent to the PLL oscillator 44 in a period of about 2 groups. At f2 (a)
Starts a reception operation similar to . In this way, f1,
I was switching f2. (Problems to be Solved by the Invention) In the conventional selective call receiving device described above, the reception frequency was switched by detecting a frame synchronization signal.
If frequency switching takes at least l groups of time, and in the above example, the electric field at f1 is at the limit where the frame synchronization signal can be received, for example, if you are at point a in Figure 9, reception at f is possible. However, there was a drawback that it did not switch to f2. It is an object of the present invention to provide a selective call reception device which eliminates the drawbacks of the conventional method, can receive the strongest electric field frequency in a short time, and does not require a special signal for electric field detection. (Means for Solving the Problems) A selective call receiving device of the present invention includes a receiving unit that transmits a selective call signal from a base station and outputs it as a digital signal;
A counter that detects a change point in the regular timing of a digital signal, a plurality of comparators that compare the output of this counter with multiple set values to correspond to an electric field value, and the output of this comparator is used to control the reception section, etc. A battery saving control section that controls the power supply, a control section that controls data for switching between multiple reception frequencies based on the output of the comparator, a PLL oscillation section that oscillates a variable frequency based on this data, and a , a frame period, and a detection unit that detects a paging signal. Also, during reception operation, it judges multiple comparator outputs at multiple frequencies, and detects the frequency with the most normal change points. It has a control unit that controls the reception operation, and further has a control unit that controls the reception operation to be performed at the frequency at which the reception operation was previously performed when it is determined that the comparator outputs are the same at multiple frequencies. It is something. (Function) According to the present invention, the electric field strength is detected using the number of regular bit change points as a parameter, and multiple frequencies can be switched, so reception operation can always be performed at the frequency with the strongest electric field. In addition, since there is no need to use a special signal code to detect electric field strength, air time can be reduced and the system simplified. (Example) An example of the present invention will be explained based on FIG. 1, FIG. 4, and FIG. 8. FIG. 1 is a block diagram of the bit synchronization section and electric field detection section of the selective call receiving device of the present invention. In the figure, 1 is the NRZ input, 2 and 3.5 are the control inputs from the control section, 4 is the primary comparator output, 6 is the secondary comparator output, 7 is the change point detection section, 8 is the phase comparison section, 9 is an integration section, 10 is a clock generation section, 11 is a pulse increase/decrease section, 12 is a frequency division section, 13 is a latch, 14 is a counter, 15 is a windowing signal generation section, 16 is a primary comparator, and 17 is a 2 This is the next comparator.

FIG. 1 mainly shows a configuration corresponding to the conventional bit synchronizer 34 shown in FIG.
Similar to the receiving device of No. 0334, it operates as follows. A change point detection means is constructed from a digital PLLiA by adding a clock generation section 10 to a change point detection section 7, a phase comparison section 8, an integration section 9, a pulse increase/decrease section 11, and a division section 12. 13 is a latch, 14 is a counter that performs hexadecimal up/down counting, 15 is a window opening signal generator, 16 is a primary comparator, l7 is a secondary comparator, 2, 3, and 5 are standards from the control unit 40, respectively. Value input terminal, 4.6 is control unit 4
This is the output terminal to 0. In addition, with the above configuration, the window opening signal generating section 15, when a desired reception signal is input,
This is to determine the position where the change point should exist and the position where it should not exist, and uses the internal timing pulse obtained from the clock generator 10 as input, and is configured by counters, gates, etc., and performs the counter reset shown in Figure 6. It is reset by signal (d).

Next, while referring to the timing charts of Figs. 5 and 6, we will explain the operation of the NRZ signal (No.
n-Rturn to Zero signal)
SAG signal form (1 word=62.5ms,
1 batch = 1.0625 g). Figure 5 shows the changes in the NRZ change point (b), window opening signal (C), latch output signal (d), and latch reset signal (a) with respect to the change in the NRZ signal input (.) shown in Figure 1. The situation is shown below. Here, the unit bit length of the NRZ signal (a) is 1.95m+, and if the change point unit bit is to be detected at 1716, the change point will be at a position of 122 us. Waveform shaping section 33 in FIG.
When an NRZ signal is input from input terminal 1 as an output, a bit-synchronized reproduced clock is generated by digital PLL section A. As shown in FIG. 5(e), the output of the window opening signal generator 15 has a ratio of "H" to "L" selected to be, for example, 6:10, and the output is NRZ at approximately the center of the 'H' portion. It is designed to detect the changing point of the signal.NR
The detection output of the change point of the Z signal is sent to the counter l4 and also to the latch 13, and the latch 13
When a plurality of NRZ change points exist in each section of ``N, 47 L'', the second and subsequent points are ignored, and the latch reset signal (
e) to reset the latch 13. Next, the counter 14 changes the output of the latch 13 so that the window opening signal (c) is
When the output is ``, it counts up, and when it is ``L'' it counts down.The counter 14 maintains 0 when the output is 0 and counts down, and maintains F when the output is F (= 16) and counts up. The outputs of the counter 14 are input to a primary comparator 16 and a secondary comparator 17, respectively, and after comparison with reference values set by input terminals 3 and 5,
When the counter output exceeds the reference value, it is output to the control section 40, and the power supply from the battery 45 to the receiving section 32, etc. is controlled via the battery saving control section 43 in different modes. As the reference value, for example, the secondary comparator 16. For 17, set them to 3 and 7, respectively. Figure 6 shows how the battery is saved with respect to the output of the counter 14. In the same figure, the primary judgment clock (a
) The comparison of the primary comparator 16 is performed at the timing (62.5 m). Since noise occurs randomly when there is no signal,
The up counter values cancel each other out and never exceed 3, so the primary comparison 1i! l6 output 4
maintains mode 1 shown in FIG. 6 (.) in which the signal is received intermittently at "L". On the other hand, when receiving the 5 ringing signal, the primary comparator l
The output of 6 becomes ``H'', and at this time, the mode 2 shifts to mode 2 shown in FIG. 6(b), in which the power to the receiver 32, etc. continues to be turned on for a further 62.5+ms than in mode 1.
Next, according to the timing of the secondary determination input 5 in FIG. 6(f), the secondary comparator 17 determines whether the value of the counter l4 is 7 or more, and when the output is "LH", the mode is set to mode l. Also"
When the signal is "H", it is assumed that reception has been completed completely, and the system shifts to mode 3 shown in Figure 6(c), turns on the power to the receiver, etc. for about 2 seconds, and moves on to the next step of frame synchronization signal verification. According to the above structure, as shown in FIG.
Even if battery saving is activated when there is no signal in mode 1 as shown in (b), preamble detection is performed by pattern matching as in the conventional example, but as shown in (b), the position of the change point of the received calling signal, that is, Establishing bit synchronization also serves as preamble detection, making it possible to detect a calling signal. Furthermore, whereas conventionally the bit synchronization was performed and then the transition was made to the preamble pattern matching, according to the above structure, the bit synchronization can also serve as the preamble matching, and therefore the time until the synchronization is established is It has the advantage of saving power supply. The rest of the structure is the same as in Figure 3, but the movement in Figure I? Since the operation of the control unit 40 changes depending on the situation, the description will focus on that part. The operation shown in FIG. 1 can be applied to any signal speed by changing only the basic clock, so a description thereof will be omitted.

For example, if the value of the primary comparator 16 is selected to be 3 and the value of the secondary comparator 17 to be 7, the operation as shown in FIG. becomes possible. In other words, if the previously received frequency f■ data is sent to and received by the PLL oscillator 44, and both the primary comparator 16 and the secondary comparator l7 are NG, then the f2 frequency data is sent to the PLL oscillator 44.
The signal is sent to and received by the oscillation unit 44, and if the primary comparator 16 or the secondary comparator 17 is OK, the signal goes directly to frame synchronization signal detection. In this case, to judge the result of the comparator,
Since BCH code is used as the signal system, 1 to 2
Words are sufficient. The receiving frequencies are f1 and f,
Figure 5 shows the general operation in the case of two frequencies. As shown in the flowchart of FIG. 8, when the previously received frequency is f1, f1 data is determined by the control unit 40 to the PLL oscillation unit 44 in FIGS. 3 and 1, and reception at f1 is performed. ．． First, determine the result of the secondary comparator 17, and
If so, it is determined that the electric field at f1 is strong, and reception operation at f1 is performed. When the result of the secondary comparator 17 is NG, the result of the primary comparator 16 is determined, and when it is OK, a flag is set, and when it is NG, the f3 data is directly set in the PLL oscillation section 44. f3 is received, and similarly the secondary comparator 17
Determine the result. If it's OK, just f! Enters reception operation. Also, if it is NG, check the above flag,
If it is determined, the f1 data is sent to the PLL oscillator 44, and reception operation begins at f. If the flag is not set, leave f8 to judge the result of the primary comparator 16 and OK.
If so, enter reception operation at f2. If the result of the primary comparator 16 is also NG, it is reset to f, which entered the reception operation last time, and the reception operation starts at f1. By performing the above operations, it is possible to always enter reception operation at the frequency with the strongest electric field. According to this embodiment, an example has been shown in which two comparators are used and two reception frequencies are switched, but it is also possible to use a plurality of comparators and switch between a plurality of frequencies using a similar method. (Effects of the Invention) According to the present invention, the electric field strength can be detected using the number of normal bit change points as a parameter and multiple frequencies can be switched, so that the reception operation is always performed at the frequency with the strongest electric field. Furthermore, since there is no need to use a special signal code for electric field strength detection, it is possible to reduce air time and simplify the system.Furthermore, the detection time is also shortened compared to conventional methods. The practical effect is extremely large.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a bit synchronization section and electric field detection section of a selective call receiving device according to an embodiment of the present invention, FIG. 2 is a diagram of a conventional signal system, and FIG. 3 is a block diagram of a conventional selective call receiving device. , Fig. 4 shows the same signal as Fig. 1. FIG. 5 is a timing chart for explaining the operation of the device in FIG. 1 during one bit of the NRZ signal, and FIGS. 6 and 7 are battery saving diagrams of the device. FIG. 8 is a reception flowchart of the present invention, and FIG. 9 is a schematic diagram of the service area of a selective call receiving device that calls simultaneously on a plurality of frequencies. 1...NRZ input, 2,3.5...Control input from the control section, 4...Primary comparator output, 6...
・Secondary comparator output, 7... Change point detection section, 8...
・Phase comparison section, 9... Integration section, 10... Clock generation section, l1... Pulse increase/decrease section, 12... Frequency division section,
13... Latch, 14... Counter, 15... Window opening signal generator, 16... Primary comparator, 17...
Secondary comparator.

Claims (3)

[Claims] (1) A receiving unit that receives a selective call signal from a base station and outputs it as a digital signal, a counter that detects a change point in the regular timing of the digital signal, and compares the output of the counter with a plurality of set values. a plurality of comparators that correspond to electric field values; and a battery saving control unit that controls the power supply of the receiving unit etc. based on the output of the comparators.
a control unit that controls data for switching a plurality of reception frequencies based on the output of the comparator;
A selective call receiving device comprising: a PLL oscillation section that oscillates a variable frequency; and a detection section that detects a frame period and a paging signal when receiving the paging signal. (2) The control unit according to claim (1), further comprising a control unit that determines a plurality of comparator outputs at a plurality of frequencies when performing a reception operation, and controls the reception operation to be performed at a frequency with the most normal change points. Selective call receiving device. (3) The selective call receiving apparatus according to claim (2), further comprising a control section that controls the receiving operation to be performed at the frequency at which the previous receiving operation was performed when it is determined that the comparator output is the same at a plurality of frequencies.