JPH03274933A - Interleave synchronizing circuit - Google Patents

Abstract

PURPOSE:To synchronize an interleave frame and to remove phase indefinition by extracting only an information bit on the reception side, deciding one absolute phase from plural pulled-in phases and synchronizing the interleave frame. CONSTITUTION:A received signal with the phase indefinition is fetched into a demapping means and the information bit corresponding to a pulse for interleave frame synchronization is extracted and equivalently converted to the plural pulled-in phases by an interleave frame synchronization establishing means. Then, an interleave frame synchronizing phase is searched in each phase. In such a case, since the interleave synchronizing frame is discovered in only one absolute phase is the respective pulled-in phases, the interleave frame synchronization is established and the phase indefinition can be removed by detecting the absolute phase.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention provides a method for digital communication that uses both a coded modulation method that has a high error correction ability for random errors and an interleaving method that can improve the error correction ability for burst errors. The present invention relates to an interleave synchronization circuit that detects an interleave frame synchronization phase on the receiving side. [Prior Art] A coded modulation method has been considered as a powerful error correction method (G., Ungerboeck, “C
channel coding with 5ultile
vel/phase signals”, IEEE
ran, IT, vol, IT-28, pI)55-
67.1982). On the other hand, in multilevel modulation, differential logic conversion is used to solve the problem of phase uncertainty when absolute phase transmission is impossible, but when differential logic conversion is used in coded modulation, requires the code to be transparent. Note that a search for a transparent code is currently underway (L, Wei, “ROtationally 1nva
riant Convolutional channel
elcoding with expanded si
gnal 5pace part2", IEEEJ-S
ACvol, 5Ac-2, No5. pp672-686
．． Sep, 1984), but a code with a large constraint length that provides a sufficient coding gain has not been found. Therefore, currently there are solutions that take advantage of the redundancy of the coded modulation scheme to remove the phase uncertainty (elevated, Aikawa,
Nakamura, “Reference carrier phase uncertainty removal circuit suitable for coded modulation,” IEICE Letters 82 Volume 12, 1989.
month) is valid. [Problems to be Solved by the Invention] Incidentally, in digital microwave communication, application of a coded modulation method with a large coding gain is being considered (A,
Chouly and H, 5ari, 'Appl.
cation of Trellis coding
to digital microwave radio
. IEEE ICC88, 15-1, June 1988
), but the coded modulation method belongs to random error correction code,
No significant improvement effect can be expected for burst errors. However, in digital microwave communications, countermeasures against not only errors caused by thermal noise, fading, etc., but also burst errors caused by radar interference, etc., have become important issues.
As one solution to this problem, an interleave method has been proposed that improves error correction capability by randomizing burst errors. Note that when interleaving is applied, a process is performed in which each interleave frame of a fixed interleave size is stored in a memory, and the reading order is changed and transmitted. Therefore, on the receiving side, it is necessary to perform deinterleaving to restore the order of the signals. For this purpose,
It is essential to establish synchronization of interleaved frames on the receiving side, and a common method for this is to insert a synchronization pulse on the transmitting side and detect this on the receiving side to establish synchronization. By the way, in order to extract the synchronization pulse when the interleave method is used in combination with the coded modulation method,
Phase uncertainties must be removed. However, the method of using differential logic conversion for this purpose is not a good idea in terms of coding gain, as described above. Furthermore, when using the redundancy of the coded modulation method, it is necessary to already perform deinterleaving at the input stage of the phase uncertainty removal circuit, which has not been achieved using conventional methods. The present invention provides an interleave synchronization circuit that enables phase uncertainty removal and interleave synchronization even when a code that provides a sufficiently large coding gain is used when a coded modulation method and an interleave method are used together. The purpose is to provide. [Means for Solving the Problems] FIG. 1 is a block diagram showing the basic configuration of the circuit of the present invention. The present invention according to claim 1 is characterized in that encoded bits and non-coded bits of a transmission data stream are mapped and interleaved on a predetermined signal space and transmitted, and the received signal is deinterleaved and then a corresponding decoding process is performed. In an interleave synchronization circuit for a digital communication system that uses both coded modulation and interleaving, an interleave frame synchronization pulse is inserted into the transmitted data string, and the received signal arranged in a predetermined signal space is demapped. , a demapping means for extracting the information bit corresponding to the pulse for interleave frame synchronization, and a means for equivalently rotating the phase of the information bit output, searching for the interleave frame synchronization phase from the obtained plurality of pull-in phases, and determining its absolute phase. Establish interleaved frame synchronization,
and interleave frame synchronization establishing means for removing phase uncertainty and subjecting the received signal to deinterleaving processing. The invention according to claim 2 provides a method for mapping and interleaving coded bits and non-coded bits of a transmission data string onto a predetermined signal space, and transmitting the resultant data, and deinterleaving the received signal and then performing corresponding decoding processing. In a digital communication system that uses both coded modulation and interleaving, the non-coded bits of the transmitted data stream are arranged rotationally symmetrically, and a pulse for interleaved frame synchronization is inserted into the non-coded bit stream. demapping means for demapping uncoded bits from the signal;
The apparatus includes interleave frame synchronization establishing means for establishing interleave frame synchronization in accordance with the output of the demapping means and for providing deinterleaving processing of the received signal. (Function) The present invention as set forth in claim 1 captures a received signal with phase uncertainty into the demapping means, extracts the information bit corresponding to the interleave frame synchronization pulse, and further includes the interleave frame synchronization establishing means, Equivalently transform into multiple entrainment phases and search for the interleaved frame synchronization phase in each phase. Here, one of each entrainment phase is an absolute phase, and the interleaved frame synchronization phase is found only in that absolute phase. Accordingly, interleave frame synchronization can be established and phase uncertainty can be removed by detecting its absolute phase. Since the non-encoded bits are inserted into bits, there is no phase uncertainty even if the unencoded bits are demapped on the receiving side, and interleaved frame synchronization can be established. An embodiment will be described in detail. Figure 2 is a block diagram showing an example of the configuration of an encoder and a mapping circuit. In this embodiment, the encoding rate is 1/1 with 16QAM encoding.
An example using No. 2 encoder is shown below. In FIG. 2, one pinto to be encoded is input to the encoder 21, and two encoded bits are output. These 2 pint encoded bits and 2 unencoded non-encoded bits are input to the mapping circuit 23,
placed at the corresponding signal point. The encoder 21 receives the input of the 1-bit data string χ as follows.
Output encoded bits consisting of the unchanged output y and the test sequence Z. Generally, in a code, the information data part of the encoder output is the same as the input data (y = x)
Although they are classified into systematic codes and non-systematic codes (y-s-x), here is an example of forming a systematic code. In other words, in the case of a systematic code with a coding rate of 1/2, ■
The pinto outputs the encoder input as it is, and the other pinto outputs the shift register 25 and exclusive OR circuit 27 to -g.
It is output from a circuit consisting of. FIG. 3 is a diagram showing an example of mapping arrangement in the mapping circuit 23. In the figure, the 2-bit encoded bit is C01C1, the 2-bit uncoded bit is UO1U1, and the output data string of the mapping circuit corresponding to each signal point is (Co
CI UOUl). In this embodiment, as shown in FIG.
ion) method, the non-encoded bits are rotationally symmetric. That is, the uncoded bits are

Based on the four signal points at the center that are [00], the unencoded bits are [11
] is located at the 4th corner, and [10] and [01] are located next to each other, making them rotationally symmetrical. FIG. 4 is a diagram showing the structure of an interleaved frame. In the figure, the 4 bits arranged vertically correspond to the output data string of the mapping circuit 23, and in FIG.
IUOUl). Also, the width is segment l
-k, and F1 to F4 are inserted interleave frame synchronization pulses (hereinafter referred to as "synchronization pulses")
shows. FIG. 4(a) is an example in which synchronization pulses (Fl to F4) are inserted into both encoded bits (CO, CI) and unencoded bits (UO, Ul). FIG. 4(b) shows a synchronization pulse (Fl~
F2) is inserted. FIG. 4(C) is an example in which synchronization pulses (F1 to F2) are inserted into non-encoded bits. Note that when a synchronization pulse is inserted into a coded bit, that bit is also coded by the encoder, so even if 1 bit is inserted, it is coded into 2 bits. FIG. 5 is a diagram showing the interleave format used in the circuit of the present invention. In the figure, the horizontal direction is segment (k), and the vertical direction is interleave depth d. That is, the interleave size n is kXd. Further, each rectangle is a memory arranged in an array, and the interleaver on the transmitting side has a configuration in which each data string is independently written in the horizontal direction and read in the vertical direction. In this embodiment, since the configuration is to process four data sequences, four array memories are stacked one on top of the other. Note that this means that interleaving is performed while maintaining the relationship between the 4 bits of each time slot. Therefore, for this purpose, after establishing segment synchronization, it is necessary to establish interleave frame synchronization based on the periodicity of the synchronization pulse. FIG. 6 is a block diagram showing a configuration example of a coded modulation modem to which the present invention is applied. Note that FIG. 6(a) shows the configuration of the modulation section, and FIG. 6(b) shows the configuration of the demodulation section. In FIG. 6(a), an input data string is inputted via a synchronization pulse insertion circuit 51 to an encoding modulation section 52 composed of an encoder 21 and a mapping circuit 23, and its output is a synchronization pulse insertion circuit 51. The signal is inputted to a 16QAM modulator 54 via an interleaver 53 synchronized with a circuit 51, modulated, and transmitted. In FIG. 6(b), 16QA to which the received signal is input
The MI modulator 61 demaps the demodulated signal using a simple decoder 6.
2 and the deinterleaver 63. The output of the demapping simple decoder 62 is directly transmitted to the 90° phase shifter 6.
41, 180° phase shifter 642, and 270° phase shifter 643, respectively, are input to synchronous circuits 65 and 653,
Furthermore, each output is input to a phase uncertainty removal circuit 66 to achieve interleave frame synchronization. The output of phase uncertainty removal circuit 66 is sent to deinterleaver 63 and main signal phase shifter 67. Deinterleaver 6
The output of No. 3 is input to a decoder 68 via a main signal phase shifter 67, and decoded data is output. The operation of the coded modulation modem will be described below with reference to FIG. 7, which shows input and output data of each part. In the synchronizing pulse insertion circuit 51 to which the three data sequences shown in FIG. 7(a) are input, synchronizing pulses as shown in FIG. 4 are inserted (FIG. 7(b)). The third series of output bits of the synchronization pulse insertion circuit 51 is encoded by the encoder 21, converted into four series of data strings, and sent to the mapping circuit 2.
3 (FIG. 7(C)). That is, the fourth series of synchronization pulses corresponding to the test series is generated from the third series of synchronization pulses. Further, as explained in FIG. 4, the synchronization pulse may be inserted into both the coded bits and the non-coded bits, or may be inserted only into the coded bits or the non-coded bits. The mapping circuit 23 performs a predetermined mapping process, and the output data string is interleaved by the interleaver 53, where the four data strings are interleaved while maintaining the 4-bit relationship (FIG. 7(d)). On the receiving side, the demodulated signal obtained from the 16QAM demodulator 61 is a signal with phase uncertainty, as shown in FIG. 7(e). In the demapping simple decoder 62, after demapping and simple decoding the demodulated signal (see Fig. 7))
, each phase shifter 64. ~64°, 90°, 180°, 27
A phase shift of 0° is applied (Fig. 7 (2)). The synchronization circuits 65° to 653 search for the interleave frame synchronization phase for each signal, including signals that are not subjected to phase shift processing. The interleave frame synchronization phase is 4 6 synchronous circuits
5. 653, and the phase uncertainty removal circuit 66 removes the phase uncertainty by detecting whether interleave frame synchronization has been established at that one pull-in phase (Fig. 7). (Company)). The obtained results are sent to a deinterleaver 63 and a main signal phase shifter 67, respectively. The main signal is deinterleaved after synchronization is established and phase uncertainty is removed, the main signal is shifted to an absolute phase by a main signal phase shifter 67, and decoded by a decoder 68. Note that the phase shifter passively realizes the function of shifting the phase of the carrier for synchronous detection, and the phase shifter passively realizes the function of shifting the phase of the carrier for synchronous detection, and it
This is a configuration in which corresponding bits of a series of data strings are inverted. FIG. 8 is a diagram showing an example of the configuration of a phase shifter. In the figure, the 90° phase shifter 641 is composed of an inverting circuit 81 that inverts the I channel, and the 180° phase shifter 64□ is composed of inverting circuits 82 and 83 that invert both the ■ channel and the Q channel. The phase shifter 643 is composed of an inversion circuit 84 that inverts the Q channel, and an equivalent phase shift is performed by digital signal processing. FIG. 9 is a block diagram showing an example of the configuration of a demapping simple decoder. Note that FIG. 9(a) shows an example of the configuration of a demapping circuit for encoded bits, and FIG. 9(b) shows an example of the configuration of a simple decoder. In the case of the symbols shown in FIG. 3, the demapping circuit is as follows:
Since C0=Q1 and CI=11, the configuration is such that the bits of Ql and 11 are directly extracted to C01C1. When the simple decoder uses the systematic code encoded by the encoder 21 shown in FIG. It has a configuration that brings out the focus as is. In this way, in this embodiment, a received signal with phase uncertainty is equivalently converted into each pull-in phase, and one of each pull-in phase is
One is the absolute phase, and by finding the interleave frame synchronization phase only at that absolute phase, interleave frame synchronization is established, and phase uncertainty is removed by detecting the absolute phase, but the synchronization pulse is By inserting only the coded bits, it is possible to simplify the demapping simple decoder 62 on the receiving side. In other words, the demapping circuit of the demapping simple decoder 62 is a circuit that performs the reverse operation of the mapping circuit on the transmitting side, and converts the received signal placed in the signal space into a mapping arrangement for coding modulation (the coding bits are set). It is configured to convert according to the partition method (non-encoded bits are rotationally symmetric). Therefore, in the case of encoded 2LQAM, a memory or logic circuit with L bit input and L bit output is required, but when inserting a synchronization pulse only in the encoded focus (Fig. 4 (b)), Demapping circuitry is required only for the encoded bits. On the other hand, the demapping circuit for encoding focus can be realized with a simple configuration due to the periodicity of the set partition method, and the demapping simple decoder 62 can be simplified. By the way, the mapping method in the coded modulation method is as follows.
Coded bits are determined by the set partition method, but there is no particular method for non-coded bits. Therefore, if the synchronization pulse is inserted into the non-coded bit sequence of coded modulation (Fig. 4 (C)) and the non-coded bits are arranged rotationally symmetrically, after demapping on the receiving side,
It is possible to detect synchronization pulses on uncoded bits and establish interleaved frame synchronization. In other words, since the non-encoded bits are rotationally symmetric, there is no phase uncertainty, and interleave frame synchronization can be established before the phase uncertainty removal circuit, followed by deinterleaving, followed by separate phase uncertainty removal. I do. FIG. 10 is a block diagram showing another configuration example of a coded modulation modem compatible with such a method. Note that FIG. 10(a) shows the configuration of the modulation section, and FIG. 10(a) shows the configuration of the demodulation section. In FIG. 10(a), synchronization pulses are inserted into non-coded bits by a synchronization pulse insertion circuit 51'. The other configuration of the modulation section is the same as that shown in FIG. 6(a). In FIG. 10(b), a non-encoded pit demapping circuit 91 demaps non-encoded bits and sends them to a synchronization circuit 93. The synchronization circuit 93 searches for an interleave frame synchronization phase, but since the non-encoded bits are rotationally symmetrical, interleave frame synchronization can be established without removing phase uncertainty. Deinterleaver 63
', the main signal is deinterleaved according to the output of the synchronization circuit 93, and a phase uncertainty removal circuit 95 provided separately is used.
The phase uncertainty is removed by the decoder 68, and the decoding process is performed by the decoder 68. [Effects of the Invention] As described above, the present invention extracts only the information bits corresponding to the interleave frame synchronization pulse on the receiving side, determines one absolute phase from a plurality of pull-in phases, and performs interleave frame synchronization. This enables interleaving in the coded modulation method. That is, in the coded modulation method, phase uncertainty can be removed without using differential logic conversion using transparent codes. Therefore, in a coded modulation system that is resistant to random errors, it is possible to perform interleaved frame synchronization and phase uncertainty removal using a code that provides a sufficiently large coding gain, which is not possible with differential logic conversion. Furthermore, it becomes possible to apply interleaving that can exhibit a strong error correction ability for burst errors.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the principle configuration of the present invention. FIG. 2 is a block diagram showing a configuration example of an encoder and a mapping circuit. FIG. 3 is a diagram showing an example of mapping arrangement in a mapping circuit. FIG. 4 is a diagram showing the structure of an interleaved frame. FIG. 5 is a diagram showing an interleave format used in the circuit of the present invention. FIG. 6 is a block diagram showing a configuration example of a coded modulation modem to which the present invention is applied. FIG. 7 is a diagram showing input/output data of each part of the embodiment. FIG. 8 is a diagram showing an example of the configuration of a phase shifter. FIG. 9 is a diagram showing an example of the configuration of a demapping simple decoder. FIG. 10 is a block diagram showing another example of the configuration of a coded modulation modem. 21... Encoder, 23... Mapping circuit, 51.
... synchronization pulse insertion circuit, 52 ... coding modulation section,
53... Interleaver, 54... 16QAM modulator, 61... 16QAM demodulator, 62... Demapping simple decoder, 63... Deinterleaver, 64...
... Phase shifter, 65 ... Synchronization circuit, 66 ... Phase uncertainty removal circuit, 67 ... Main signal phase shifter, 68 ... Decoder, 81-8 ... Inversion circuit, ■...Non-coded focus demapping circuit, 93...Synchronization circuit, 95...Phase uncertainty removal circuit. 12345678910 123456789101+ 1234567891011 1471025811369 1471025811369 1471025811369 deterministic (some signal) (demapped signal) (a) (b) Fig. 0

Claims (2)

[Claims] (1) Coded modulation and interleaving in which coded bits and non-coded bits of a transmission data stream are mapped onto a predetermined signal space, interleaved and transmitted, and the received signal is deinterleaved and then the corresponding decoding process is performed. In a digital communication system that uses the interleave frame synchronization pulse in combination with the above, the configuration is such that an interleave frame synchronization pulse is inserted into the transmission data string, and the received signal arranged on the predetermined signal space is de-mapping, and the interleave frame synchronization pulse is inserted into the interleave frame synchronization pulse. a demapping means for extracting a corresponding information bit, and equivalently rotating the phase of the information bit output, searching for an interleave frame synchronization phase from the obtained plurality of pull-in phases, and determining the absolute phase to establish interleave frame synchronization. and interleave frame synchronization establishing means for removing phase uncertainty and providing for deinterleaving processing of a received signal. (2) Coded modulation and interleaving in which coded bits and non-coded bits of a transmission data stream are mapped onto a predetermined signal space, interleaved, and transmitted, and the received signal is deinterleaved and then the corresponding decoding process is performed. In a digital communication system that uses the non-encoded bits of the transmitted data stream in a rotationally symmetrical manner, an interleaved frame synchronization pulse is inserted into the non-encoded bit series, and the non-encoded bits of the transmitted data stream are An interleaving device characterized by comprising: a demapping means for demapping coded bits; and an interleave frame synchronization establishment means for establishing interleave frame synchronization according to the output of the demapping means and providing for deinterleaving processing of a received signal. synchronous circuit.