JPH03274735A - Manufacture of semiconductor device with schottky electrode - Google Patents

Abstract

PURPOSE:To prevent the lowering of adhesive properties with a resist by forming a Schottky junction by forming a first layer composed of the silicide of a high melting point metal onto a semiconductor substrate, shaping a second layer consisting of the high melting-point metal onto the first layer, forming a third layer made up of the silicide, etc., of the high melting-point metal and forming a Schottky electrode. CONSTITUTION:Si<+> ions are implanted into a semi-insulating GaAs substrate 1 as donor impurities, and a conductive layer 2 is formed through annealing. A WSix film 3, a W film 4 and a WSix film 5 are superposed and applied successively onto the conductive layer 2. Since WSix has adhesive properties with a photo-resist better than W, the resist is hardly peeled when the photo-resist 6 is applied onto the WSix film 5 as an uppermost layer, thus improving yield. The photo-resist 6 is patterned, and the WSix film 5, the W film 4 and the WSix film 3 are machined through reactive ion etching, thus shaping a gate electrode. The photo resist 6 is removed, the ohmic electrodes of a source and a drain are formed and the electrodes and the conductive layer 2 are coated with an inter-layer insulating film 10, and a semiconductor device is completed through wiring 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device having a Schottky electrode.

[Conventional technology]

GaAs MESFET (MetalSemiconductor
onductor Field Effect Tra
nsistor), a high melting point metal silicide such as tungsten silicide, which has excellent thermal stability and good adhesion to the semiconductor substrate, is used as the first layer, and a high melting point metal layer such as financial tungsten is layered on top of it. A technique for reducing gate resistance is known from Japanese Patent Laid-Open No. 61-214481.

[Problem to be solved by the invention]

When a stacked film gate (lower layer is a WSi x film and upper layer is a metal tungsten film) is used as a gate electrode of a GaAs MESFET, there is a problem in that the resist is likely to peel off, resulting in a decrease in the yield of gate formation.

An object of the present invention is to prevent a decrease in adhesion to a resist that occurs when a high melting point metal is used as a Schottky gate electrode material.

[Means to solve the problem]

The above object is a step of directly forming a first layer made of silicide of a high melting point metal on a semiconductor substrate to form a Schottky junction, and a step of forming a second layer made of a high melting point metal directly on the first layer. or a step of forming through a layer containing a high melting point metal,
Directly forming a third layer made of at least one material selected from the group consisting of high melting point metal silicide, high melting point metal nitride, and silicon on the second layer, on the third layer. a step of directly forming a resist film, a step of buttering the resist film, and a step of etching the first layer and the layer formed thereon using the patterned resist film as a mask to form a Schottky electrode. By forming a distant relative.

[Effect]

In the present invention, since high melting point metal silicide is used as the bottom layer (first layer) of the gate electrode, it is possible to form a good Schottky junction at the semiconductor interface. Furthermore, since a high melting point metal is used as the second layer, it is possible to reduce the resistance of the gate.

Furthermore, since the third layer having good adhesion to the resist is formed as the uppermost layer, peeling of the resist can be prevented.

When connecting a wiring layer to the gate electrode, contact resistance can be reduced by removing the third layer and directly connecting the wiring layer to the second layer.

〔Example〕

The present invention will be explained below using examples.

In the example, the case where it is used as a gate electrode of GaAs MESFET will be explained, but InP, InGaA
It can be used for other compound semiconductors such as s, I n A Q A s, and single element semiconductors such as silicon, and can be used for Schottky diodes, I G F E T (
It is also possible to use it as a gate electrode of an insulated gate FET) or the like.

Example, 1 Embodiment 1 of the present invention will be described with reference to FIGS. 1 and 2.

Si+ is added to the semi-insulating GaAs substrate 1 as a donor impurity.
A conductive layer 2 is formed by implanting ions and performing annealing. On top of that, a W Si x film 3 of 1100n, a W film 4
The WSix film 5 is overlaid with a thickness of 200 nm and a thickness of 10 nm. The deposition of WSi,3,5 was performed by sputtering a sintered W5Si3 target with Ar'' ions, and the pressure of Ar gas during sputtering was 9 mtorr, and the power was 0.35 kW DC. x film set Iffcx is 0.22, and the internal stress is 3 in the tensile direction.
X 10"dyne/d.

The deposition of Wl114 is performed by sputtering using a W target, with an Ar gas pressure of 5 mtorr and a direct current power of 0.36 kW. At this time, the internal stress of the W film is GaA
For the s substrate, 7×10 'dyne/
al, but since it is actually deposited on the W S i x film, the stress will be dissipated at any interface of the W S
The total stress of the i x film 3 and the W film 4 becomes almost zero with respect to the GaAs substrate. Since the stress in the uppermost W Si x film 5 is thin, it can be almost ignored. W Si x has better adhesion to photoresist than W, so if photoresist 6 is applied on top layer W S i x film S, resist peeling will hardly occur, so conventional W/
The yield is improved compared to the case of a gate with a two-layer structure of W Si x.

After patterning the photoresist 6, the WSi x film 5, W film 4, WSix
The film 3 is processed to form a gate electrode.

The sheet resistance of the gate electrode used in this example is approximately 0.
9Ω/port, and a single layer W Si x gate (approximately 7Ω
/ mouth) is about 178. FIG. 1 shows the cross-sectional shape of the gate metal after processing.

Next, after removing the photoresist 6, the source and drain ohmic electrodes (not shown for clarity) are removed, and the interlayer insulating film 1 is removed.
The present embodiment is completed by covering 0 and wiring 11.

The contact resistance between the wiring metal (Au) 11 and the uppermost layer WSiX film 5 is 3 to 5 Ω when the contact hole is a square of 1×1 μm 2 . However, when the uppermost layer WSix film 5 is removed at the contact hole portion and the wiring metal is brought into contact with the intermediate layer W film 4, the contact resistance can be reduced to 0.6 to 0.8Ω, so the parasitic resistance of the gate It becomes possible to reduce the resistance by 2 to 4 Ω. The cross-sectional structure in this case is shown in FIG.

Example, 2 In Example 1, W S i ! of the third layer, the uppermost layer! Although the film thickness of the film 5 was set to 5 to 10 nm, FIG. 3 shows the cross-sectional shape of the gate electrode in the case where it was made thicker. The thickness of the uppermost WSiX film 5 is 50 nm.

In the dry etching process using CHF3, CF4, NF, gas, etc., the etching rate of W S i x is 2 to 4 times higher than that of W. Side etching occurs in the IX layer 5 from the side surface, and the W layer 4 is exposed from the side etched portion. As a result, the cross-sectional shape of the intermediate layer W film 4 becomes trapezoidal.

During processing of the bottom layer WSix film 3, polymer generated from the etching gas adheres to the side surfaces, so
Etching is slower than that of the i x film 5, and side etching is slight.

Although the gate electrode of this example has the disadvantage that the gate resistance is slightly larger than that of Example 1, it has the advantage that the flatness is improved when the glabella insulating film is applied to the gate electrode.

Example 3 An example of the present invention is shown in FIG. In the dry etching process, the etching rate of W Si Therefore, in this embodiment, W Si
The X layer 3 and the W layer 4 each have a thickness of 1100 nm, and this is repeated twice to obtain a 4-layer structure, and then a W Si x layer 5 with a thickness of several nm is deposited on the top layer.

In this case, since the wsix layer 3 is made thinner, the amount of side etching of this layer is reduced, and the cross-sectional shape of the gate electrode approaches a rectangle.

Example 4 In Examples 1 to 3, the top layer 5 has the same W S x as the bottom layer 3.
* was used. The reason for this is that the sputtering target was changed from WsSlx to W, and then again to W3Si,
This is because there is an advantage that the lowermost layer 3, intermediate layer 4, and uppermost layer 5 can be formed continuously by switching to the above.

However, the top layer 5 is W Si X N y or W
N.

It is also possible to use a target of W, Si3, or W to be formed by sputtering in a nitriding atmosphere. In this case, W S l xNy, WH, is Af
It acts as a barrier metal against W in wiring and gate electrodes, suppresses electromigration in contact holes, and improves the reliability of integrated circuits and extends product life.

Other materials for the top layer 5 include TaSix, MoSix,
Other silicides such as TiSix, Irsix, or WN
,, nitrides such as T a Nx, borides such as WB, TaB, carbides such as WC, SiC, TiC, or Si
It is also possible to use .

Example 5 In a load FET of an integrated circuit, the cell area can be reduced by directly connecting the gate electrode and the ohmic electrode on the source side. In this case, in a gate electrode having a rectangular cross-sectional shape, a defect occurs in which the ohmic electrode is disconnected at the corner portion of the side end. A method to solve this problem is to form a Si film as the top layer of the gate electrode material in the region that will become the source side end of the gate electrode, and to side-etch the Si film by dry etching when forming the gate electrode. A method of improving step coverage by processing the source side end of the gate electrode into a tapered shape using
It is known from the publication No. 187876.

Further, since Si can also achieve the object of the present invention, it is possible to combine the present invention and the above-mentioned prior art.

As a fifth embodiment, an example will be shown in which this combination is applied to an integrated circuit having an inverter circuit. FIG. 5 is a sectional view thereof, and FIGS. 6(a) to 6(e) are manufacturing process diagrams of the load FET portion.

A semi-insulating substrate 1, an active layer 2 of a drive FET and a load FET.
was formed, and WSi was formed by DC (direct current) sputtering.
The x layer 3 and the W layer 4 are deposited to a thickness of 100 nm and 200 nm, and further RF
A 50 nm Si layer 7 is deposited by (high frequency) sputtering. At this time, a W Si x layer 5 is formed at the interface between the W, Ii 4 and the Si layer 7 by sputter mixing and diffusion (FIG. 6(a)).

The thickness of this W S i x layer 5 can be made 1 to 2 nm by increasing the RF power when depositing S i f@ 7, but it is also possible to make it even thicker by heating with an infrared lamp. Next, the Si layer 7 is left only on the source side of the region where the gate electrode of the load FET is to be formed, and the Si layer 7 is removed from other regions. After that, photoresist 6 is applied to a thickness of 1 μm, and the gate electrode is patterned (
Figure 6(b)).

Tri-etching is performed using the photoresist 6 as a mask to process the gate electrode. At this time, since the etching rate of Si is one order of magnitude higher than that of W, the etching rate of Si is etched while etching the W layer 4.
In i Nl 7, side etching progresses from the side.

As a result, the W layer 4 is processed into a tapered shape in the portion where the S i M 7 remains. The cross-sectional structure of the load FET at this time is shown in FIG. 6(c).

In this step, in the gate electrode of the load FET, the lower surface of the photoresist 6 is made of Si or WSIX as described above.
Furthermore, since the lower surface of the photoresist 6 is in contact with W S x x in the gate electrode of the open FET, the photoresist 6 will not peel off during this process.

Next, after removing the photoresist 6, a high-concentration conductive layer (n''Fg) 9 was formed by ion implantation, and a Si○2 film 12 of about 300 nm was deposited using a D chemical vapor deposition method. Afterwards, the n+ layer 9 is activated by activation annealing at 800°C for 15 minutes.Subsequently, the organic resist film 13 is formed to a thickness of about 1 μm.
After coating, use this as a mask to form S in the ohmic electrode formation area and the wiring area between the gate and source of the load FET.
in.

Film 12 and Si layer 7 are removed. Next, ohmic metal (AuGe) 8 is deposited to a thickness of 0.2 μm (Fig. 6 (
d)).

Next, the organic resist film 13 and the Si*2 film 12 are removed (soft-off method) to form an ohmic electrode. The cross-sectional structure of the load FET at this time is shown in FIG. 6(e). The ohmic electrode 8 on the source side is directly connected to the gate electrode, and can occupy a smaller area than the ohmic electrode 8 on the drain side.

A cross-sectional view of the inverter circuit at this time is as shown in FIG. Thereafter, an interlayer insulating film is deposited and a wiring process is performed to complete the integrated circuit (not shown).

〔Effect of the invention〕

The present invention eliminates the peeling of photoresist that occurs when forming a low-resistance gate electrode using tungsten, and has the effect of improving the yield of integrated circuits.

Furthermore, by using a high melting point metal nitride or a mixture of high melting point metal silicide and nitride in the top layer, outward diffusion of tungsten in the wiring metal and gate electrode is suppressed, and the electromigration life (EM) is suppressed. It has the effect of extending lifespan.

Furthermore, by selecting a material with a high etching rate, such as Si, for the uppermost layer, it is possible to provide a taper at the side edge of the gate electrode, thereby improving step coverage. This effect is effective in improving the yield of integrated circuits in which the cell area is reduced by direct gate-source connection in the load FET.

[Brief explanation of drawings]

Figure 1 shows the MES of Example 1 using the stacked gate of the present invention.
A cross-sectional view of the FET. Figure 2 is a cross-sectional structural diagram of Example 1 after wiring. Figure 3 is a cross-sectional structural diagram of Example 2 with a thicker top layer W S i x film. Figure 4 is a four-layer structure. FIG. 3 is a cross-sectional structural diagram of Embodiment 3 in which the present invention is applied to a stacked gate. FIG. 5 is a cross-sectional structural diagram of Example 5 showing a method of processing the source side of the gate electrode into a tapered shape in order to directly connect the ohmic electrode on the source side of the load FET and the gate electrode, and FIG. 6(a) to 6(e) are process flow diagrams of the load FET portion of Example 5. Explanation of symbols 1... Semi-insulating substrate, 2... Conductive layer, 3, 5...
High melting point metal silicide or nitride, 4... High melting point metal,
6... Photoresist, 7... Silicon, 8... Ohmic metal, 9... N+ layer, 10... Interlayer insulating film,
11...Wiring metal.

Claims (1)

[Claims] 1. A first layer made of high melting point metal silicide on a semiconductor substrate.
a step of forming a second layer made of a high melting point metal directly or via a layer containing a high melting point metal on the first layer; a step of forming a second layer made of a high melting point metal on the second layer; a step of directly forming a third layer made of at least one selected from the group consisting of silicide, high melting point metal nitride, and silicon; a step of directly forming a resist film on the third layer; A semiconductor device having a Schottky electrode, comprising a step of patterning, and etching the first layer and the layer laminated thereon using the patterned resist film as a mask to form a Schottky electrode. manufacturing method. 2. The Schottky electrode according to claim 1, wherein the layer containing the high melting point metal has at least one set of layers in which a high melting point metal layer and a high melting point metal silicide layer are laminated in this order. A method for manufacturing a semiconductor device having the following. 3. Claim 1, which includes a step of removing part or all of the third layer after forming the Schottky electrode.
A method for manufacturing a semiconductor device having a Schottky electrode according to item 1 or 2. 4. A first layer made of high melting point metal silicide on a semiconductor substrate
a step of forming a second layer made of a high melting point metal directly or via a layer containing a high melting point metal on the first layer; a step of forming a second layer made of silicon on the second layer Third
a step of directly forming a first resist film on the third layer, a step of patterning the first resist film, and a step of using the patterned first resist film as a mask. a step of etching the third layer and exposing a silicide layer of the constituent material of the second layer formed at the interface between the second layer and the third layer when forming the third layer; The third layer remaining after the etching and the silicide layer of the constituent material of the second layer in a continuous portion thereof are covered with a third resist film so that at least one end is terminated with the third layer. The process of
and a step of dry etching the first layer and the layer formed thereon using the second resist film as a mask to form a Schottky electrode shape, and in the dry etching step, the third resist film is dry etched. A method for manufacturing a semiconductor device having a Schottky electrode, characterized in that a side surface of the Schottky electrode at a portion terminated with a layer has a tapered portion processed so that the angle of the cross section toward the semiconductor substrate side is an acute angle. 5. The Schottky electrode is a gate electrode of a field effect transistor, and after the dry etching step, the third layer is removed and the field effect transistor is exposed between the gate electrode and the source electrode. 5. A method of manufacturing a semiconductor device having a Schottky electrode according to claim 4, further comprising the step of depositing a conductive film between both electrodes and electrically connecting the two electrodes.