JPH03268515A - Integration comparing circuit - Google Patents

Abstract

PURPOSE:To practically change the reference of decision by counting up compared results outputted from a holding circuit during a 2nd period longer than a 1st period in accordance with a program stored in an inside, comparing the counted result with a 2nd variable reference value, and deciding a state based upon the result of comparison. CONSTITUTION:A counter 22 counts up synchronizing information '1' by using a transmission STA as a clock and reset at the time of inputting a decision clock with a 10msec period from an interval timer 23. A comparator 24 compares the value of the counter 22 with the 1st fixed reference value (n). A flip flop 25 holds the output of the comparator 24 in each input of a decision clock and outputs the result to a central processing circuit(CPU) 26. Since the CPU 26 may execute integration not by a SAT period but each 10msec, processing can be executed with a scope. When a reference value (m) is changed by rewriting the contents of an EEPROM or the like for storing a program, the reference value practically be changed.

Description

[Detailed Description of the Invention] [Summary] Regarding an integral comparison circuit that integrates a signal indicating a certain state for a predetermined period of time and compares it with a reference value to determine whether the state is in that state or not, even when the reference value itself cannot be changed. input signal 1
The purpose is to make it possible to substantially change the criteria for judgment by processing in a program storage type processing device whose cycle is longer than the cycle. an interval timer that outputs a judgment clock with a cycle of 1 and returns the value of the counter to its initial value; a comparator that compares the value of the counter with a first reference value; a holding circuit that holds each judgment clock, and a judgment result of the output of the holding circuit for each judgment clock, counts the judgment results over a second period that is longer than the first period, and uses the counting result as a second reference value. and a program storage type processing device that compares and determines the status.

[Industrial application field]

The present invention relates to an integral comparison circuit that integrates a signal indicating a certain state for a predetermined period of time and compares it with a reference value to determine whether the signal is in that state.

In car phones and mobile phones, a tone signal of a certain frequency (SAT: Supervisory Audio Tone) is used in addition to the voice signal to monitor call quality.
is superimposed on the audio signal and transmitted to and received from the base station. Then, after converting the received SAT to a dinotal signal,
A digital PLL (phase locked loop) is used in an LSI (Large Scale Integrated Circuit) to generate a stable signal and transmit it. Furthermore, it is determined whether the phases of the received SAT and the transmitted SAT have a predetermined phase relationship, and the integrated value of the result is compared with a reference value to determine the line quality, and the communication channel is switched or the line is disconnected. It's in control.

[Conventional technology]

A conventional SAT phase comparison and integral comparison circuit is shown in FIG.

The phase comparator consists of a D-type flip-flop, and receives the received SAT at its D terminal and inputs the transmitted SAT at its clock terminal. Under normal conditions, the phase relationship between the receiving SAT and the transmitting SAT is such that the receiving SAT is higher than the transmitting SAT, as shown in Figure 5.
The relationship is 1/4 cycle ahead. therefore,
The output of the D-type flip-flop is always 1. but,
When the PLL becomes asynchronous, the above phase relationship is no longer maintained. Therefore, the output of the flip-flop for a predetermined time period is counted, and when 1 is equal to or greater than a predetermined number of times, it is determined that the PLL is synchronized.

The counter 32 counts the output 1 of the D-type flip-flop using the transmission SAT as a clock. The interval timer 33 outputs a determination clock with a period of 250 m5ec, and the counter 32 is reset every time this determination clock is generated. The comparator 34 compares the counter value with a reference value, and outputs 1 when the value is greater than or equal to the reference value. The D-type flip-flop 35 holds the output of the comparator for each judgment clock, and the SAT
output as phase synchronization information.

[Problem that the invention seeks to solve]

The received SAT is also affected by the performance of the radio section, and the actual P
The signal manually input to the LL contains noise and noise, so it is necessary to make the synchronization judgment changeable.

However, as mobile phones and the like have become increasingly integrated into LSIs, the counters, comparators, flip-flops, etc. shown in Figure 4 are configured as hardware within the LSI, and once the reference value is determined, it cannot be changed. There is. Furthermore, if this part is attempted to be performed by so-called software using a program storage type processing device, the load will be large because comparison is performed every SAT cycle.

The present invention provides SA even if the reference value itself cannot be changed.
It is an object of the present invention to enable the determination criteria to be substantially changed by processing in a program storage type processing device having a cycle longer than one cycle of T.

[Means to solve the problem]

FIG. 1 shows a block diagram of the principle of the present invention.

The counter 11 counts state information based on a clock,
It is initialized by the first period determination clock from the interval timer 12. Comparator 13 compares the output value of counter 11 and a fixed first reference value. The holding circuit 14 holds this comparison result using the judgment clock. The program storage type processing device 15 counts the comparison results from the holding circuit 14 over a second period longer than the first period according to an internally stored program, and compares the counting results with a variable second reference value. , determine the status based on the comparison result.

[Effect]

The cycle of input to the program storage type processing device I5 is longer than the cycle of input of status information, so the processing load is reduced compared to when status information is input directly. The second reference value can be easily changed by changing the program or the like.

〔Example〕

FIG. 2 shows an embodiment of the invention.

The D-type flip-flop 21 operates similarly to the flip-flop 31 shown in FIG. 4, and outputs synchronization information as state information. The counter 22 counts 1 of the synchronization information using the transmission SAT as a clock, and counts 1 of the synchronization information from the interval timer 23.
It is reset by a determination clock having a cycle of m5ec.

A comparator 24 compares the value of the counter 22 with a fixed first reference value n.
Compare with. The flip-flop 25 holds the output of the comparator 24 for each judgment clock, and is connected to the central processing circuit (CPU).
Output to 26. The CPU 26 stores a program therein and operates according to this program.

FIG. 3 shows a flowchart of one synchronization determination process by the CPU 26.

When starting ■, first set the variable N representing the number of repetitions to 0.
and set the variable representing the count value to 0■.

Next, when the judgment clock of 10m5ec is input, ■, if the flip-flop indicates synchronization, ■, the variable L! , :
Add 1■. Then, add 1 to the variable N and determine whether N and 25 are equal. If not, return to ■. If they are equal, compare the variable with the second reference value m. If it is greater than or equal to m, synchronize. If it is less than m, it is determined that it is asynchronous [phase], and it ends at 0°. Therefore, the determination result is output every 250 m5ec, which is the same as the conventional circuit shown in FIG.

The integration by the CPU 26 is based on l0m5, not the period of SAT.
Since it only needs to be done for each eC, processing can be done with plenty of time. Furthermore, if the reference value m is changed by rewriting the EEPROM or the like that stores the program, it becomes possible to substantially change the reference value.

In mobile phones, the CPU is often operated intermittently in order to save power, but even in that case, it is effective because it only needs to be operated every 10 m5ec.

〔effect〕

As described above, according to the present invention, the reference value can be changed by the program storage type processing device, and the processing interval of the program storage type processing device can be made relatively long.

[Brief explanation of drawings]

Figure 1 is a diagram of the principle of the present invention, Figure 2 is a block diagram of an embodiment of the present invention, Figure 3 is a flowchart of synchronization determination processing, Figure 4 is a block diagram of a conventional circuit, and Figure 5 is a receiving SAT.
and a time chart of transmission SAT are shown, respectively. 11, 22.32...Counter. +2.23.33...Interval timer. 13, 24. 34... Comparator. 14...Holding circuit. 15...Program storage type processing circuit. 21, 25.31.35...Flip-flop. 26...CPU Principle configuration diagram of the present invention No. 11 I

Claims (1)

[Claims] A counter (11) that counts input state information based on a clock, and an interval that outputs a determination clock with a first period longer than the clock and returns the value of the counter (11) to its initial value. A timer (12), a comparator (13) that compares the value of the counter (11) with a first reference value, and a holding circuit (13) that holds the comparison result of the comparator (13) for each judgment clock. 14), the judgment result of the output of the holding circuit (13) is taken in for each judgment clock, the judgment result is counted over a second period longer than the first period, and the counting result is compared with a second reference value. and a program storage type processing device for determining a state.