JPH03263127A - Instruction execution control system - Google Patents

Abstract

PURPOSE:To curtail the number of steps of a program and to reduce the capacity of a memory by providing a control mechanism to generate forcibly an instruction executed in a second cycle and thereafter by hardware, in the case plural cycle instructions are fetched. CONSTITUTION:The system is provided with an instruction register 1, a decoder 2, a control register 3, a flag 4, and an instruction updating control circuit 5. In such a state, by a fact that a fetch of plural cycle instructions is detected, the fetch of a new instruction is discontinued, and also, by a fact that a flag for showing a fact that plural cycle instructions are fetched is set, a specific operation control signal is generated, and the execution of a second cycle and thereafter of plural cycle instructions is controlled. In such a way, the number of steps of a program decreases, and the capacity of a memory for storing it becomes small.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an instruction execution control system, and particularly to an instruction execution control system for a processor equipped with a control mechanism for enabling execution of multi-cycle instructions.

[Conventional technology]

Conventionally, this type of control system has been designed to execute one instruction in only one cycle.

An example of the operation of the prior art will be explained with reference to the time chart of FIG. For example, when generating an address, first,
Fetch the offset calculation instruction (f□), decode it (dt), and at the same time fetch the base addition instruction (f2). Simultaneously with the decoding (d2), offset calculation is performed (ex), followed by base addition (e 2 ).

[Problem to be solved by the invention]

In the conventional instruction execution control method described above, one instruction is executed in only one cycle, which increases the number of program steps and the memory capacity to store them. Since this is done frequently, there are disadvantages such as high bus occupancy.

[Means to solve the problem]

The configuration of the instruction execution control system of the present invention includes a decoder that detects fetching of a multi-cycle instruction which is an instruction that requires a plurality of machine cycles for execution in the instruction execution control mechanism of the bromo-ysu; an instruction update control means for interrupting the fetch of a new instruction upon detecting the fetch of the instruction; a flag indicating that the multi-cycle instruction has been completed; and the flag being set; The decoder is characterized in that it generates a specific operation control signal and controls execution of the second cycle and subsequent cycles of the multi-cycle instruction.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which 1 is an instruction register, 2 is a decoder that generates processor operation control signals and detects multi-cycle instruction fetch, and 3 stores processor operation control signals. register, 4 is a flag indicating that a multi-cycle instruction has been fetched, 5 is a flag indicating that a multi-cycle instruction has been fetched.
is a control circuit for interrupting instruction updating upon detection of a multi-cycle instruction fetch.

An example of the operation shown in FIG. 2 will be explained with reference to the timing chart of FIG.

Considering an address generation instruction as an example of a multi-cycle instruction, this instruction is an instruction that executes for 2 cycles, and 1
Assume that offset calculation is executed in the 1st cycle, and base addition is executed in the 2nd cycle.

First, in the fetch cycle fl, an address generation instruction is fetched (loaded into instruction register 1), and then in the decode cycle dll, the decoder 2 detects that the fetched instruction is an address generation instruction, and the multi-cycle instruction detection signal is This notifies the instruction update control circuit 5 accordingly.

Upon completion of the decode cycle dll, the flag 4 is set to logic “1”.
" is set, and the address generation command detection signal output from the decoder 2 is masked by the flag signal F1.

Also, at this time, the control register 3 is loaded with a control signal for performing offset calculation, but the instruction register 1
The data does not change under the control of the instruction update control circuit 5,
The address generation instruction remains stored.

In the decode cycle d12, since the flag 4 is set to logic "1", the decoder 2 forcibly generates a control signal for base addition.

At the completion of the decode cycle d12, those control signals are loaded into the control register 3, and at the same time the flag 4 is reset.

In this way, offset calculation is performed in execution cycle ett and base addition is performed in execution cycle e12, making it possible to execute two cycles with one instruction, the address generation instruction.

Furthermore, if an instruction other than the address generation instruction is fetched (f2), decoding (d2) is completed and flag 4 remains reset, so only one cycle is executed (e2).

〔Effect of the invention〕

As explained above, the present invention reduces the number of program steps by providing a control mechanism in which when a multi-cycle instruction is fetched, the hardware forcibly creates an instruction to be executed from the second cycle onwards. Therefore, it is possible to reduce the capacity of the memory that stores them, and at the same time, the number of instruction fetches is reduced, which has the effect of lowering the bus occupancy rate.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a timing chart showing an example of the operation of the conventional technology. 1... Instruction register, 2... Decoder, 3... Control register, 4... Flag, 5... Instruction update control circuit.

Claims (1)

[Claims] A decoder detects fetching of a multi-cycle instruction, which is an instruction requiring multiple machine cycles for execution in an instruction execution control mechanism of a processor; an instruction update control means for suspending the instruction; a flag indicating that the multi-cycle instruction has been fetched;
An instruction execution control method characterized in that when the flag is set, the decoder generates a specific operation control signal to control execution of a multi-cycle instruction from the second cycle onwards.