JPH03243193A - Motor controller - Google Patents

Abstract

PURPOSE:To facilitate the control of a motor and prevent the generation of restriction in the transmission of data by a method wherein a register is provided with an output signal of a timing circuit as a timing signal to give and take data with a proper timing. CONSTITUTION:An access signal 26, obtained by decoding the light signal 15, an address signal 14 and a tip select signal 13 of a higher rank microprocessor through a decoder 16, is inputted into a timing circuit 18 to convert it into a proper timing. Then, data are taken into the input register 31 of a second stage, which is connected to the input data path 29 of a second stage, by the output 30 of the timing circuit 18 while the data are given to the data path 32 under processing the data. According to this method, a timing between the data on the data path 2 and a data access signal 20 is collapsed to prevent the data on the data path 2 from being not taken into the register 31.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a motor control device that performs digital speed control of an electric motor.

(Prior Art) With the spread of microcomputers, microcomputers have been widely applied in the field of control because they are capable of performing complex and sophisticated control, and have become indispensable. A conventional technique for digital speed control of an electric motor using such a microcomputer will be explained using an elevator electric motor control device as an example.

FIG. 5 shows a block diagram of the speed control system in the elevator. In FIG. 5, 41 is a three-phase AC power supply, 42 is a converter, 43 is a DC smoothing capacitor, and 44 is an inverter. It is converted into alternating current with variable frequency and supplied to the induction motor 47.

Reference numeral 48 denotes a rotation angle detector installed on the motor shaft, which is horizontally connected to a pulse generator or resolver. 49 is a sheave, and a counterweight 50 suspended from a rope wound around this sheave 49 and an elevator car 51 are rotated by driving the sheave 49 by an electric motor 47.
It will be run.

Load detector 51a installed in elevator car 51
outputs a load detection signal.

Elevator speed control is performed by applying an appropriate Heas drive signal to the inverter 44, and this control will be described below.

The deviation between the speed command value output by the speed command value generation block 60 and the speed detection value obtained by manually inputting the rotation angle information output from the rotation angle detector 48 to the rotation angle/speed conversion block 58 is defined as the speed. It is input to five control blocks, its output and the load detection signal are manually input to the addition block 57, and the torque command signal is input to the hector control calculation block 56.
to use human power.

The rotation angle information output from the rotation angle detector 48 is also input manually to this vector control calculation block 56 . As a result, the induction motor 47 is output from the hector control calculation block 56.
The current command value for
The deviation from the current detection signal output from the current control block 55 is input to the current control block 55, and the output voltage command signal and the carrier triangular wave output from the carrier triangular wave generation block 54 are manually inputted to the comparator 53. The output of the base signal is manually input to the base drive circuit 52 to obtain a base drive signal, which is then supplied to the inverter 44 to control the speed of the elevator.

In the elevator motor control device configured as described above, conventionally, the part A surrounded by the dotted line in FIG. Both were processed digitally. Then, the digital current command value signal output from digital circuit A is converted to D/A.
The signal is converted into an analog signal by a converter, and the subsequent current control block 55, carrier triangular wave generation block 54, and comparator 53 process the analog signal.

(Problem to be Solved by the Invention) However, in conventional motor control devices that perform current control using analog signals, the offset and circuit constants of the operational amplifier may change depending on the temperature and other environments, and the analog signal There was a problem in that it was easily affected by external noise. Furthermore, if the loop cane is increased in an attempt to improve the followability of current control, the voltage waveform is disturbed, so there is a problem that there is a limit to the followability of current control.

On the other hand, in recent years, digital signal processing sensors (hereinafter referred to as DSP) and custom ICs (hereinafter referred to as AS
With the advent of ICs, high-speed digital signal processing has become possible, and current control has become possible with digital circuits. This has made it possible to avoid the effects of the environment and noise that could have occurred earlier, and to improve the followability of current control. However, if all elevator speed control, including the current control section, is performed using digital signals, the processing speed of current control, speed control, etc. is required to be faster than that of a microprocessor. For this reason, this part is driven by a high-speed clock that is asynchronous to the microprocessor, but the interface between the microprocessor and this part requires that both timing signals be output to each other and performed in synchronization. This has led to problems such as restrictions on data transfer and an increase in the load on the microprocessor.

This invention was made in view of these conventional problems, and its purpose is to provide a system that is easy to control, does not impose restrictions on data transfer, and does not increase the load on the microprocessor. An object of the present invention is to provide a digital control type electric motor control device.

[Structure of the Invention] (Means for Solving the Problems) The present invention includes a host microprocessor that performs main motor calculations, and a clock that operates at a higher speed than the operating clock of the host microprocessor to perform high-speed processing calculations. In a motor control device comprising a digital processing system that generates motor control values, a register for data interface between the upper microprocessor and the digital processing system, and a register for the data interface between the upper microprocessor and the digital processing system, and a register for the data interface between the upper microprocessor and the digital processing system, The device includes a timing circuit that changes the timing to an appropriate timing based on an operation clock, and sends and receives data at an appropriate timing by applying an output signal of the timing circuit to the I-no register as a timing signal.

(Function) In the motor control device of the present invention, the host microprocessor performs main control, obtains control information from the host microprocessor, and the digital processing system operates asynchronously with the host microprocessor to control the motor. Since the operating clock of the digital processing system is asynchronous with that of the host microprocessor and is also faster, there is a speed difference between the digital processing system and the host microprocessor.

Therefore, a register is provided for a data interface between the two, and the timing of the data access signal from the host microprocessor is changed using a timing clock of a digital processing system obtained by dividing the high-speed clock. Data is exchanged by.

In other words, a data register is provided in an elevator control system that has a high-speed digital processing system that controls the system sequence using a host microprocessor and also detects the speed of the system's drive source and controls the current control system. Since this register is used to exchange data between the processor and the digital processing system, this allows the speed detection section and current control section to be used as one of the peripherals assigned to the address space of the host microprocessor. It becomes possible to handle
Data transfer during this time will be simplified and made more general. Therefore, if the host microprocessor, speed detection section, and current control section access this data buffer when exchanging data, there will be no problem between the host microprocessor, speed detection section, and current control section, which have different operating speeds. Data can be exchanged easily.

(Example) Hereinafter, embodiments of the present invention will be explained in detail based on the drawings.

FIG. 1 is a block diagram of an all-digital motor control system for an elevator, which is an embodiment of the present invention.

1 in FIG. 1 is a microprocessor (CPU), and 2 is a data bus. 3 is a data bus control signal, which is composed of a read signal, a write signal, a chip select signal, and an address bus.

4 is a two-phase pulse signal which is a pulse generator output, and this two-phase pulse signal 4 is a custom IC for speed detection (ASIC) that detects rotation angle and performs hector control calculation.
-APPLICATION 5PECIFICINTE
GR^-TED CIRCUIT) 5 will be manually operated.

6 is an ASIC that performs processing after current control together with a digital signal processor (DSP) 7, and outputs a base drive signal 8.

9 is an analog current detection signal, and A/D converter 10
is converted into a digital signal by the AS I C6.
given to.

11 is a high speed clock generator (OS C),
Processing in the IC 5, AS IC 6, DSP 7, and A/D converter 10 is performed in synchronization with this clock.

In this motor control device, the microprocessor 1 performs both operation sequence processing and protection sequence processing.
Generation of the speed command value (60) in the same way as shown in FIG.
Rotation angle/speed conversion (58), speed control (59), and addition (57) to the load detection signal are performed, and torque commands and the like are transferred to the ASICs 5 and 6 via the data bus 2.

In AS I C5, 2 which is the pulse generator output
A phase pulse signal 4 is obtained, converted into rotation angle information, and transferred to the microprocessor. Further, a part of the vector control calculation (56) in FIG. 5 is performed using this rotation angle information and the slip frequency transferred from the microprocessor 1, and a current command value phase reference signal is transferred to the ASIC 6.

The DSP 7 uses the current detection signal, current command value phase reference signal, and torque command obtained through the ASIC 6 to
Hector control l calculation (56) and current control (5
5), and the voltage command signal obtained as a result is sent to the ASIC.
Transfer to 6.

The ASIC6 is the pig interface to the DSP7 mentioned earlier, and the generation of the carrier:angular wave (5) in Figure 5.
Comparison of 4) with voltage command signal and carrier triangular wave (53)
and generates a base signal to be output to the base drive circuit (52).

The data interface between the microprocessor 1 and the ASIC 6 in the all-digital elevator motor control system configured as described above will be explained with reference to FIG.

FIG. 2 is a block diagram of the data bus output section within the AsIc6. In this FIG. 2, 12 to 15 are data bus control signals 3 in FIG. 1, 12 is a read signal (RD), and 13 is a chip select signal (C3).
14 is an address bus (ADDRESS BUS),
15 is a write signal (WR), which is given from the microprocessor 1 to the ASIC 6.

A decoder 16 decodes the data bus control signals 12 to 15, and outputs data such as rotation angle and slip frequency to the data bus 2.

17 is a timing clock obtained by frequency-dividing the high-speed clock output from the high-speed clock generator 11 in FIG. 1 by a counter. 18 is a timing circuit that adjusts the access signal obtained from the host microprocessor 1, which is the output of the decoder, to appropriate timing.

] 9 is a data bus input/output cover sofa composed of a tri-state buffer with a large output capacity and an input buffer, in order to input and output data from the human data bus 20 and output data bus 21 inside the ASIC 6 to the data bus 2. circuit, and this data bus input/output cover sofa circuit 19
The output dry state buffer opens a gate by ANDing the read signal]-2 and the chip select signal 13 by the AND circuit 22, and outputs the data on the internal output data bus 21 to the data bus 2.

Data to be transferred to the host microprocessor 1 as a signal within the ASIC 6, such as rotation angle, is indicated at 23 in Figure 2.
It is indicated by. These data 23 are sent to the timing circuit 18
The read signal 12, address signal 14, and chip select signal 13 from the host microprocessor 1, which is the manual input of the timing circuit 18, are decoded by the decoder 16. The access signal 26 opens the gate of a tri-state buffer 27 connected to the output side of this register 25 and outputs it to the output data bus 21. The signal then passes through one data bus input/output cover circuit and is output to the data bus 2 from the host microprocessor 1.

Data to be transferred from the host microprocessor 1 to the ASIC 6 passes through the data bus input/output cover sofa circuit 19 from the data bus 2, is manually inputted to the manual data bus 20 inside the ASfC6, and is further transferred to the data bus 20 by the write signal 15 from the host microprocessor 1. Through the register 28 of the stage,
It is held in the two input data paths of the second stage.

A decoder 16 receives the write signal 15, address signal 14, and chip select signal 13 from the host microprocessor 1.
The access signal 26 obtained by decoding is input to the timing circuit 18 and converted to an appropriate timing.

The output 30 of the timing circuit 18 is used to input data into a second-stage human-powered data register 31 connected to a second-stage human-powered data bus 29, and provide the data to the data bus 32 during data processing.

In this way, the input data path 20.2 inside the ASIC6
9 is configured in two stages, and the reason why the data is taken into the first stage register 28 only by the write signal 15 is that the data on the data bus 2 and the output of the timing circuit 18 are synchronized due to the delay of the decoder 16 and the timing circuit 18. The timing with the data access signal 20 that was received is disrupted, and the data bus 2
This is to prevent the above data from not being taken into the register 31.

FIG. 3 shows the detailed circuit configuration of the timing circuit 18, and FIG. 4 shows the timing circuit 18 and internal processing data 2.
3.32 timing chart is shown. In FIG. 3, 17a is a timing clock synchronized with the update cycle of internal processing data, or a high speed clock obtained by doubling the frequency of that clock, and 1-7b are the same clocks as 17a or even faster locks. Further, 33a is a D-Q flip-flop with precent, 33b is a D-Q flip-flop, and 33C is an AND element.

By configuring the circuit in this way, the output 26a of the preset I)-Q flip-flop 33a is output to the next timing clock 1 after the access signal 26 from the host microprocessor 1 rises or falls.
The signal 24.3 is synchronized with the rising edge of signal 26a, and this signal 26a is further inputted into a differentiating circuit to generate a timing signal 24.3 synchronized with the rising edge and falling edge of signal 26a.
0 is output from this circuit 18.

The relationship between these timings is shown in FIG. In FIG. 4, the timing of the data bus during data processing indicated by 23 or 32 means that in the case of 23, this data is updated by the processing inside the digital processing system, and in the case of 32, it indicates the timing at which this data is updated by the processing inside the digital processing system. indicates the timing at which data must be stable for processing within the digital processing system. In other words, if data access from the host microprocessor 1 is performed at the same time as this timing, normal data exchange will not occur.

Note that FIG. 4 shows a case where the data access signal 26 from the host microprocessor 1 reaches the timing described above.

It can be seen from this timing chart that the timing signals 24 and 30, which are the outputs of the timing circuit 18, are enabled at a timing different from the timing of the data 23 or 32 during data processing. Further, in this timing circuit 18, by inserting a shift register using a timing clock between the output of the preset DQ flip-flop 33a and the differentiating circuit, the time Δt shown in FIG. 4 can be changed. Therefore, by inserting an appropriate shift register in consideration of timing variations of data 23 or 32 during data processing, the timing clock manually inputted to the timing circuit 18 can be changed to the output of the timing circuit 18. It is possible to change the timing of a certain timing signal 24.30.

As described above, if the data bus input part inside the ASIC 6 is configured, the upper microprocessor 1 can
Data can be exchanged with the ICs 5 and 6 as one of the peripherals assigned to a certain area of the address space without performing special software processing or providing a complicated interface circuit.

Therefore, in this embodiment, a data access signal from a microprocessor to a circuit section that requires high-speed processing, such as current control, is converted to an appropriate timing by a high-speed clock of the high-speed processing section. By importing data from the host microprocessor into the registers of the high-speed processing part in synchronization with
It becomes possible to perform all-dinotal speed control of elevators with versatility.

In the above embodiment, the synchronization circuit that synchronizes the access signal from the -4th microprocessor with the timing clock of the digital processing system is replaced with the timing circuit in the above configuration, and the output of this synchronization circuit is used as the data. A similar effect can be obtained by a configuration provided to an interface register. However, in this case, especially if the data to be accessed from the host microprocessor is being processed at high speed in the digital processing system, synchronization must be performed by taking into account variations in the delay times of the D-Q flip-flops in the synchronization circuit. Select the timing clock to use. For this reason, it may be difficult to design a frequency division counter that generates a timing clock.

However, if a timing circuit is used instead of a synchronization circuit as in the present invention, the timing clock given to the timing circuit will be used to synchronize the processing timing within the digital processing system with respect to the data accessed by the host microprocessor. The clock is faster than the clock, and the timing of the timing signal output from the timing circuit, that is, the timing at which data is taken into the data interface register, can be easily changed by adding a shift register circuit to the timing circuit. Therefore, there is no need to change the timing clock, and the design of the frequency division counter becomes easier.

[Effects of the Invention] As described above, according to the present invention, data transfer between a low-speed processing digital processing system and a high-speed processing digital processing system can be easily and effortlessly carried out, and there are no restrictions on data transfer. Therefore, it is possible to provide a motor control device using a digital control method that does not require any additional control.

[Brief explanation of drawings]

FIG. 1 shows the constituent countries of an embodiment of the present invention, FIG. 2 is a block diagram showing the structure of the data bus output part of the ASIC of the above embodiment, and FIG. 3 shows the structure of the timing circuit in the ASIC of the above embodiment. FIG. 4 is a timing chart showing data access timing of the timing circuit in the above embodiment, and FIG. 5 is a block diagram of a conventional example. 1... Microprocessor 2... Data bus 5.
6... Custom IC (ASIC) 7... Digital signal processor (DSP) 10... A/D converter 11... High speed clock generator 16... Decoder 18... Timing circuit 25.28 .31...Register

Claims (1)

[Claims] In a motor control device consisting of a host microprocessor that performs main motor calculations, and a digital processing system that operates at a clock faster than the operating clock of this host microprocessor, performs high-speed processing calculations, and generates motor control values. , a register for data interface between the upper microprocessor and the digital processing system, and a timing circuit that changes an access signal from the upper microprocessor to an appropriate timing using an operating clock of the digital processing system, A motor control device configured to send and receive data at appropriate timing by giving an output signal to the register as a timing signal.