JPH03240821A - Information recording device - Google Patents

Abstract

PURPOSE:To effectively transfer and record data and to shorten the data recording time by controlling the transfer of data to a storage means which stores temporarily the recorded data as well as the data recording/inspecting operations to a recording medium in parallel with each other. CONSTITUTION:An information recording device (optical disk drive device) 1 is connected to a host computer 2 and records data to a recording medium (optical disk) or reproduces data out of the optical disk with the instruction of the computer 2. Then the means 4 and 7 control the transfer of data to a storage means (buffer) 8 which stores temporarily the data to be recorded to the optical disk as well as the data recording/inspecting operations to the optical disk in parallel to each other. In other words, an optical disk controller ODC 7 controls the read/write data and this control operation is controlled by a CPU 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information recording device that records information using a recording medium such as an optical disk or a magneto-optical disk.

[Prior Art] Conventionally, magnetic disks, optical disks, and the like have been known as disk-type information recording media. In such a disk recording medium, for example, a spiral track is divided into a plurality of sectors, and information is recorded in sector units.

By the way, it is known that optical discs have a high error rate when recording information, so an error correction code (ECC) is added to the data.
C: Error Correction Code)
By adding , processing is performed to increase the reliability of the data. Also, immediately after recording data, playback the data in that sector and verify whether it was recorded correctly (
verification) processing is being performed. If there is an error, the defective sector can be repaired by recording data in the same sector again or recording data in another alternative sector. Adding, deleting, or verifying such correction codes is
This is performed by an ECC circuit which will be described later.

An information recording/reproducing device using such an optical disk records or reproduces information according to instructions from a host device, which is a higher-level control device. Generally, the speed at which data is transferred from a host device to an information recording/reproducing device is often different from the speed at which data is actually recorded on an optical disc. Therefore, the information recording and reproducing apparatus uses a buffer memory to temporarily store data from the host device and temporarily store reproduced data from the optical disc. Also,
This buffer is also used to hold data until the verification process is completed, in order to re-record the data in the error sector when an error occurs when performing the verification process as described above.

FIG. 9 shows the timing of data transfer from a conventional host device, data recording onto an optical disk, and verification.

The optical discs used here are either the Write 0nece method, in which data cannot be erased and only allows for additional writing, or the 0ver Write method, which allows overwriting without erasing sectors that have already been written. It is something.

In FIG. 9, data is first transferred from the host device to the information recording/reproducing device. At this time, if the amount of recording data is larger than the buffer size, the data in the capacity of the buffer is transferred multiple times. When one data transfer is completed, the information recording/reproducing apparatus writes data onto the optical disc, and then jumps to the beginning of the recorded sector for verification. Then, the recorded data is played back and checked to see if it was recorded correctly. When the first transfer data recording and verification are completed in this way, the next second data transfer is performed, and writing to the optical disk and verification are performed in the same manner. Then, until all data from the host device has been recorded,
The process described above is repeated.

[Problem to be Solved by the Invention J] However, in conventional devices, data transferred from a host device is stored in a buffer, and then the data is recorded on an optical disk. Therefore, data transfer to the buffer, data recording to the optical disk, and verification are performed alternately, and while data is being transferred to the buffer,
Recording data to the optical disc must wait.

For this reason, conventional data transfer and data recording are inefficient (and data recording processing requires a long time).

The present invention has been made to solve these problems, and its purpose is to efficiently transfer data to a buffer and record data to a recording medium, and to shorten data recording processing time. The object of the present invention is to provide an information recording device that provides the following information.

[Means for Solving the Problem] In order to achieve the above object, a storage means for temporarily storing data sent to be recorded on a recording medium is provided, and after recording the data in the storage means on the recording medium, the recording is performed. An information recording device for verifying whether or not a device is normal, characterized in that the information recording device has means for controlling data transfer to the storage means, data recording to the recording medium, and verification processing thereof in parallel. provided.

[Operation] According to the present invention, data transfer and recording can be efficiently performed by controlling data transfer to a storage means for temporarily storing recorded data, data recording to a recording medium, and verification processing thereof in parallel. This is done to significantly shorten the recording processing time.

[Examples] Examples of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the information recording apparatus of the present invention.

In FIG. 1, an optical disk drive device is connected to a host computer 2, and according to instructions from the host computer 2 records data on an optical disk (not shown) or reproduces data from the optical disk. The interface between the optical disk drive device l and the host computer 2 is an SC5I (Smoll Computer System).
tem Interface), and the 5csr controller 3 performs handshaking of commands, data, etc. The 5C3I controller 3 also has a function of measuring the transfer speed of data transferred from the host computer 2. The transfer speed measured here is
It is used to control data recording processing as described later.

The CPU 4 receives commands sent from the host computer 2 via the 5C5I controller 3, and controls data write/write processing to be described later.

The ROM 5 is a fixed memory in which a control program for the CPU 4 is stored, and the RAM 6 is a work memory for the CPU 4.

In addition, 0DC (Optical Disk Control
7 controls read/write data, and its operation is controlled by the CPU 4.

Note that the specific configuration of 0DC7 will be described in detail later.

Buffer RAM 8 is a buffer memory for read/write data, and ECC circuit 9 is used to store user data.
CC (Error Correction Code)
This circuit executes modulation processing that adds error correction and demodulation processing that performs error correction using ECC. The ECC circuit 9 also has a verify function that uses ECC to determine whether there are more than a certain amount of defects in the reproduced data. A modulation/demodulation circuit 10 modulates a recording signal to an optical disk and demodulates a reproduced signal from the optical disk, and an R/W section 11 is a device for recording data on the optical disk or reading data from the optical disk.

Next, the flow of data when performing data recording processing in this embodiment will be explained. First, when a write command is sent from the host computer 2 to the 5csr controller 3, the CPU 4 sends the ODC 7 the number of the first sector in which to record data, the number of sectors, and the buffer RAM.
8 specifies the start address of the data to be temporarily stored.

Further, the CPU 4 instructs the R/W unit 11 to seek to the target sector. The ODC 7 stores data from the host computer 2 in the buffer RAM 8 via the 5CSI controller 3 according to the CPU 4 (7) instruction. At the same time, the ODC 7 checks the sector number of the optical disk demodulated by the modulation/demodulation circuit 10, and when the target sector is detected, sends the data loaded in the buffer RAM 8 to the ECC circuit 9. The ECC circuit 9 adds ECC to the sent data and sends it to the modulation/demodulation circuit IO, and further sends it to the R
The /W unit 11 performs a process of writing one sector worth of data into a designated sector of the optical disc. When the recorded data is in multiple sectors, the above-described process is repeated.

After recording this data, verify processing is performed to check whether the data has been recorded normally.
When PU 4 finishes recording the predetermined number of sectors, R/
0DC7 indicates that the data demodulated by the modulation/demodulation circuit 10 is of the target sector, and sends the data to the ECC circuit. 9 and check the number of defects. If this defect exceeds a certain amount, it is determined that a verify error has occurred, and data in the buffer RAM 8 is rewritten to the defective sector. Therefore, the recorded data is held in the buffer RAM 8 until the verification is successful.

FIG. 2 is a block diagram showing a specific configuration of the ODC 7. As shown in FIG.

The 0DC7 is composed of a control section 20 and various registers used for recording processing on an optical disc.

The command register 21 is set by the CPU 4 at the time of a write command.The sector number 21a is the number of the first sector to be recorded, the size 21b is the number of sectors to be recorded, and the buffer load address 21c is the first address of the buffer RAM 8 into which the recording data is loaded. be. The load processing register 22 is used when transferring data from the host computer 2, the size 22a is the number of sectors to be transferred, the buffer pointer 22b is the address to be stored in the buffer RAM 8, and the counter 22c is the data loaded in the buffer RAMB. is the effective number of sectors.

The data write processing register 23 is used when recording data on an optical disc, and includes a sector number 23a for recording data, a sector number 23b, a buffer pointer 23c indicating the address of the buffer RAM 8, and a counter indicating the number of sectors to be continuously recorded. It consists of 23d. The verify processing register 24 is used during verification, and includes a sector number 24a to be verified and a counter 24b indicating the number of sectors to be verified consecutively.

Furthermore, the status setting register 25 is used to set various conditions necessary to start recording data on the optical disc, and the number of lightweight sectors 25a is set in advance by a buffer RAM.
8 is the number of sectors of data loaded. Also,
The number of write block sectors 25b is the maximum number of sectors to be continuously recorded and verified at one time, the buffer top address 25c is the starting address of the buffer RAM 8, the buffer end address 25d is the final address, and the buffer space 25e is the buffer RAM 8. is the number of free sectors.

Note that the number of write block sectors 25b may be the maximum number of sectors that can be stored in the buffer RAM 8, or may be the maximum number of sectors that can be stored in the buffer RAM 8, or the number that minimizes the rotational waiting time of the optical disc when jumping to the first sector for verification after recording. The number of sectors may be as follows. The number of lightweight sectors 25a is calculated by the control unit 20 based on the data transfer rate from the host computer 2, the data recording rate on the optical disk, and the amount of data to be recorded, and is the optimum number to minimize the recording processing time. It is a value.

A method for determining the number of lightweight sectors will be explained with reference to FIG.

First, the data transfer rate from the host combiator 2 to the buffer RAM 8 is TH (time/sector), and the buffer RA
The recording speed of data from M8 to the optical disk is T. (
time/sector). At this time, the time taken to load n sectors of data into the buffer RAM 8 and record it on the optical disc is assumed to be T1, and similarly, the data recording time of n-1 sectors is assumed to be T2.

Further, it is assumed that data recording is started when a sector's worth of data is loaded into the buffer RAM 8, and the time for loading a sector's worth of data therein is assumed to be T3.

Note that by starting recording on the optical disc before loading all data into the buffer RAM 8 and performing data loading and recording in parallel, it is possible to shorten the recording processing time. However, in this case, if all data has not been loaded at the start of recording of the final sector, data cannot be written and it is necessary to wait for one revolution of the optical disc. Therefore, in such a case, the recording processing time becomes longer due to waiting for rotation of the optical disc.

Therefore, the condition that does not require waiting for the rotation of the optical disk can be obtained from the following equation (13).

TL≦l +TI...(1) Furthermore, T
1 in the shortest time, it is sufficient to find the minimum value that satisfies the condition for minimizing T, that is, the number of sectors loaded at once into the buffer RAM 8 mentioned above (11). Therefore, the following (2 ) ~ (4) are substituted into the above equation (1) and rearranged, TL = THx n''' (2) T3
=TMXk...(3)T2=T
oX (n-1) (4) Equation (5), which is a condition for finding the minimum value of k, is obtained.

k≧n (n 1 ) XTD/TH-(5
) T is uniquely determined by the R/W section 11, and T is 5C.
It is determined by measuring with the 3I controller 3. Therefore, the recording processing time (T1) can be minimized by finding the minimum k (integer value) that satisfies the above equation (5) based on the number n of sectors to be recorded.

Note that when a plurality of host computers 2 are connected to the optical disk drive device 1, the data transfer rate T is measured for each host computer 2 by the 5CSI controller 3. That is, since the data transfer rate TH differs depending on the type of host computer, it is sufficient to measure T for each host computer and find the optimum value of k according to the results. Furthermore, in an MCAV system device that divides an optical disc into a plurality of zones and records at a different recording frequency for each zone, the recording speed differs for each zone.

In this case, for example, the value of To corresponding to each zone is R
It is sufficient to set it as a table in OM 5 and find the value of k using Tゎ for each zone.

Furthermore, methods for measuring the data transfer rate of the host computer 2 in the 5C3I controller 3 include, for example, counting the reference clock within the data transfer period of one sector, or measuring the transfer period of one byte of data. In addition, this data transfer rate measurement is based on 5CS
Not limited to I controller 3, CPU 4 and 0D
Of course, it is also possible to measure with C7.

Next, data recording processing by the ODC 7 of the above embodiment will be explained in detail. FIG. 4 is a flowchart showing data load processing, FIG. 5 is a flowchart showing data recording processing, and FIG. 6 is a flowchart showing verification processing. Note that the data load process and the data recording or verify process can proceed simultaneously.

First, when the host computer 2 instructs recording,
The CPU 4 issues a write command to the ODC 7 and sets the command register 21 shown in FIG. That is, a sector number 21a which is the number of the first sector to be recorded, a size 21b which is the number of sectors to be recorded, and a buffer load address 21c which is the first address of the buffer RAM 8 into which data is to be loaded are set. - When this set is completed, the ODC 7 starts the data loading process shown in FIG. However, before issuing the write command described above, the CPLI 4 is assumed to set the status setting register 25 shown in FIG. 2. That is, the number of lightweight sectors 25a is set to a value of k that minimizes the recording processing time described above, and the number of write block sectors 25b is set to the maximum number of sectors that can be stored in the buffer RAM 8. . Also, the buffer top address 25
c, buffer end address 25d has buffer RA
The start address and end address of M8 are set respectively.

Therefore, the data loading process shown in FIG. 4 will be described in detail.

First, in Sl, load processing register 2 shown in FIG.
Size 22a is the number of sectors to be loaded in 2, and size 23 is the number of sectors to be recorded in the write processing register 23.
The value of the size 21b, which was previously set in the command register 21, is set in b. The number of sectors to be recorded is set in the size 21b. In addition, a buffer pointer 22b indicating the load address of the buffer RAM 8 of the load processing register 22, and a buffer pointer 23c indicating the address of the buffer RAM 8 of the write processing register 23 are set in the state setting register 25. Set the value of top address 25c. Furthermore, the sector number 23a of the write processing register 23
Then, the sector number 24a of the verify processing register 24 is set to the first sector number to be recorded, which is the same as the sector number 21a of the command processing register 21.

Then, the buffer space 25 of the status setting register 25
The number of sectors that can be stored from the buffer top address 25c to the buffer end address 25d is set in e.

In S2, if the value of the buffer space 25e is 0, verification of the data in the buffer RAM 8 is completed and the process waits until the buffer RAM 8 becomes free. That is,
Wait until buffer space>0. In S3, the buffer RAM 8 indicated by the buffer pointer 22b
The data from the host computer 2 is loaded from the address 1 byte by byte while the buffer pointer 22b is incremented by 1, and 22 worth of data on 1 is loaded. Then,
In S4, the value of the counter 22c of the load processing register 22 is set to +1L, and in S5, the values of the buffer space 25e of the state setting register 25 and the size 22a of the load processing register 22 are set to -1. The value of this size 22a is the number of sectors to be loaded. After this, in S6, load processing register 2
The value of the buffer pointer 22b of No. 2 is updated to the address to be loaded next. That is, if the value of the buffer pointer 22b exceeds the buffer end address 25d,
A ring buffer is realized by setting the value of the buffer top address 25c. Then, in S7, the number of sectors of data to be loaded is set in the load processing register 22 (
- determining whether size 22a) is 0;
It is determined whether loading of all data into the buffer RAM 8 has been completed. If the value of the size 22a is not 0, the same process is repeated from S2 again to finish loading all data.

Next, data write processing will be explained with reference to FIG.

First, when receiving a write command from CPU4, Sl
Then, the size 23 is set in the counter 23d of the write processing register 23 and the counter 24b of the verify processing register 24.
If the value of b is larger than the value of the number of write block sectors 25b, the value of the number of write block sectors 25b is set. Conversely, if the value of the size 23b is smaller than the value of the number of write block sectors 25b, the value of the size 23b is set. In S2, the process waits for the R/W unit 11 to access the target sector indicated by the sector number 23a of the write processing register 23. When the target sector is detected, it is determined in S3 whether the value of the load counter 22c is greater than the value of the number of lightweight sectors 25a.

As a result, if NO in S3, 1 of the optical disk will be deleted in S4.
After waiting for rotation, the same process is performed again from S2. The CPU 4 is notified that the optical disk is waiting for one revolution, and the CPU
4 controls the R/W unit 11 to be located on the same track when the rotation wait mode is entered. In other words,
The sector worth of data explained in Figure 3 is stored in the buffer RAM.
It waits on the same track until it is loaded into 8. On the other hand, when S3 becomes YES, data is written to the sector designated by the sector number 23a of the write processing register 23 in S5. Next, in S6, the buffer pointer 23c
, updates the sector number 23a, and updates the counter 23d in S7.
, size 23b are each set to -1.

Thereafter, in S8, it is determined whether the value of the counter 23d is O or not, and if it becomes 0, the process proceeds to verification processing. Also, if it is not 0, the data of the next sector to be written in S9 will be buffered.
To check if it is loaded into RAM 8,
The buffer pointer 22b of the load processing register 22 and the buffer pointer 23c of the write processing register 23 are compared. Here, if the two do not match, the next data is stored in the buffer RAM 8, so data is written again from S5 to the next sector. On the other hand, if they match, the SIO enters the mode of waiting for one revolution of the optical disc and performs the process of S9 again. This S9 and SIO processing is necessary because data transfer by the host computer may be interrupted even if the number of lightweight sectors 25a is set to an appropriate value. In this way, data is written into the target sector one sector at a time, and when all data has been written, the value of the counter 23d becomes O in S8, and the process proceeds to verify processing.

Figure 6 shows the verification process.
This notifies the CPU 4 that the recorded first sector is in a state to be accessed. Then, it waits until the sector number 24a of the verify processing register 24, which is the target sector, is detected. When the target sector is detected, the reproduced data of the target sector is sent to the ECC circuit 9 in S2 to perform verification processing. In S3, if a verify error is detected, error handling is performed, and if verification is OK, the 'verify sector (sector number 24a) is updated in S4. Next, in S5, the buffer space 25e is increased by +11. , a verify counter 24b, and a load counter 22c.
are each set to -1. In this case, when the buffer space 25e is in the waiting state at 82 in FIG. Can be restarted.

Thereafter, in S6, it is determined whether the verify counter 24b is 0 or not, and if it is not 0, the same process is performed from S2, and the verify process is repeated for every l sector. and,
When the value of the counter 24b becomes 0, it is determined in S7 whether the size 22a of the load processing register 22 is 0 or not. Here, if it is not 0, repeat the write process in Figure 5,
When it becomes O, a series of data write and verify processes are all completed.

FIGS. 7 and 8 show the timing of data transfer from the host computer, recording, and verification processing when the above-described processing is performed. In this example, it is assumed that an amount of data exceeding the size of the buffer RAM 8 is to be written, and the write and verify processes are repeated twice.

Further, FIG. 7 shows the timing when the data transfer rate T of the host computer 2 is faster than the recording speed T0 on the optical disk, and FIG. 8 shows the timing when the opposite is true.

First, FIG. 7 will be explained. In this case, TM>T
o, so to minimize the wait time in the figure,
According to the above-mentioned equation (5), it is sufficient to set it to =1. The data transferred from the host computer 2 is stored in the buffer RAM.
8, and when the wait time has elapsed, write processing (write l) is started in parallel with the data transfer. When all the data in the buffer RAM 8 has been written, the track jumps to the first sector written, and the verify process (verify 1) begins. This verification 1
During the process, as is clear from the figure, when the verification of the first sector is completed, data for the next write 2 period is loaded into the buffer RAM 8 for one sector. Furthermore, when the verification of the next sector is completed, the data of the next sector to be written in the write 2 period is loaded. In this way, one sector of data is sequentially loaded into the buffer RAM 8 each time verification is completed in units of sectors.

This eliminates the waiting time for data loading from the next write 2 period, and the write 2 process can be executed immediately after verify 1 ends.

Next, FIG. 8 will be explained. The timing shown in this figure is when TM <To, as described above. In this case as well, the wait time can be minimized by finding k that satisfies the above-mentioned equation (5). Also,
The timing shown in FIG.
Transfer to.

Therefore, there is no waiting time for data loading from write 2 (therefore, data can be written immediately after verification is completed. Note that if THX2>TD, there is no waiting time for the rotation of the optical disk during write 2. Therefore, data transfer, data writing, and verification can be performed as shown in FIG.

[Effects of the Invention] As explained above, according to the present invention, data transfer to a storage means for temporarily storing recorded data, data recording to a recording medium, and verification processing thereof are performed in parallel, so that data transfer is easy. , recording and verification can be performed in parallel, and data recording processing can be performed efficiently. Therefore, compared to the conventional method in which data transfer, recording, and verification are performed alternately, there is an effect that data recording processing time can be significantly shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the information recording device of the present invention, FIG. 2 is a block diagram showing a specific example of ODC, and FIG.
FIG. 4 is an explanatory diagram showing the timing of data transfer by the host computer and data recording on the optical disk; FIG. 4 is a flowchart showing the flow of data loading processing in the embodiment;
FIG. 5 is a flowchart showing the flow of data write processing, FIG. 6 is a flowchart showing the flow of data verification processing, and FIG. 7 is data transfer from the host computer to the optical disk when TH>To in the above embodiment. An explanatory diagram showing the timing of data recording and data verification. Fig. 8 is an explanatory diagram showing the timing of data transfer from the host computer, data recording to an optical disk, and data verification when T, <T. FIG. 2 is an explanatory diagram showing the timing of data transfer, data recording, and data verification in a conventional device.

Claims (2)

[Claims] (1) An information recording apparatus comprising a storage means for temporarily storing data sent to be recorded on a recording medium, and after recording the data in the storage means on the recording medium, verifying whether the recording is normal or not. An information recording apparatus comprising means for controlling data transfer to a storage means, data recording on the recording medium, and verification processing thereof in parallel. (2) The information recording apparatus according to claim 1, wherein the control means starts transferring data to be recorded in the next recording to the storage means during verification processing of data recorded on the recording medium.