JPH03228390A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH03228390A JPH03228390A JP2023681A JP2368190A JPH03228390A JP H03228390 A JPH03228390 A JP H03228390A JP 2023681 A JP2023681 A JP 2023681A JP 2368190 A JP2368190 A JP 2368190A JP H03228390 A JPH03228390 A JP H03228390A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- stitch
- chip
- wiring board
- trademark
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000004069 differentiation Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成集積回路装置に関し、特に、半導体ＩＣ等
のチップ部品が搭載される場合において、チップ部品の
搭載ミスを激減し、効率的な部品搭載処理を行なうため
の混成集積回路装置に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a hybrid integrated circuit device, and in particular, when chip components such as semiconductor ICs are mounted, it is possible to drastically reduce mounting errors of chip components and improve efficiency. The present invention relates to a hybrid integrated circuit device for performing component mounting processing.
従来、混成集積回路装置用配線基板上のチップ部品搭載
用導体マウントランドパターンとしては、四角形あるい
は星形形状が用いられ、特にチップ部品搭載時の搭載方
向確認方法としては、例えば配線基板上のステッチラン
ド側に形成されたチップ部品の１番ビンに対応するステ
ッチランドパターンを目印として用い、これとチップ部
品の１番ビンが一致するように搭載される。Conventionally, a rectangular or star-shaped conductor mount land pattern for mounting chip components on a wiring board for a hybrid integrated circuit device has been used.In particular, as a method for confirming the mounting direction when chip components are mounted, for example, stitching on the wiring board has been used. The stitch land pattern corresponding to the No. 1 bin of the chip component formed on the land side is used as a mark, and the chip component is mounted so that the stitch land pattern corresponds to the No. 1 bin of the chip component.
第３図（ａ）、（ｂ）に従来例を示した。本例では、１
番ビンに対応するステッチランドパターン４近傍にマー
クパターン６を配置することにより区別し、識別可能と
している。A conventional example is shown in FIGS. 3(a) and 3(b). In this example, 1
A mark pattern 6 is placed near the stitch land pattern 4 corresponding to the number bin to enable differentiation and identification.
上述した従来の半導体ＩＣチップ部品は、１番ビン位置
が多様であり、多数の異なるチップ部品を同時に搭載す
る混成集積回路装置においては、作業者が組立仕様図面
との整合を確認するのが難しく、部品搭載作業時に搭載
方向ミスによる誤搭載が発生しやすいという欠点がある
。In the conventional semiconductor IC chip components mentioned above, the position of the first bin varies, and in a hybrid integrated circuit device in which many different chip components are mounted at the same time, it is difficult for an operator to confirm consistency with the assembly specification drawing. However, there is a drawback that incorrect mounting is likely to occur due to incorrect mounting direction during component mounting work.
特に、最近のゲートアレーＩＣに代表されるＡＳＩＣ部
品等の場合には、予かしめ接続パッド位置が標準的に決
められており、かつ位置関係についても左右上下対称の
位置に配置されているものがほとんどとなっている。こ
のため、より搭載方向確認が困難となっているばかりで
なく、搭載方向ミスが発生してもミス自体か発見されず
に後工程の処理か行なわれ、最終の検査工程で大量の不
良製品が発見されるという問題も発生している。In particular, in the case of ASIC components, such as recent gate array ICs, the positions of the caulking connection pads are standardly determined, and the positions of the connection pads are symmetrically arranged horizontally and vertically. Most are. For this reason, not only is it more difficult to confirm the mounting direction, but even if a mounting direction error occurs, the mistake itself is not detected and is processed in the subsequent process, resulting in a large number of defective products being produced in the final inspection process. There is also the problem of being discovered.
本発明の目的は、チップ部品の誤搭載による不良製品の
発生のない混成集積回路装置を提供することにある。An object of the present invention is to provide a hybrid integrated circuit device that does not generate defective products due to incorrect mounting of chip components.
本発明は、配線基板と、該配線基板上に搭載された表面
に商標と品名を含む特徴あるパターンが表示された半導
体ＩＣを含むチップ部品と、前記配線基板上に形成され
前記チップ部品に配線接続するステッチランドとを有す
る混成集積回路装置において、それぞれの前記チップ部
品の前記商標と品名を含む特徴あるパターンの存在する
辺と対向する前記配線基板上の位置に配列された前記ス
テッチランドの形状を他辺と対向する位置に配列された
前記ステッチランドの形状に対して変形させ識別できる
ようになっている。The present invention relates to a wiring board, a chip component including a semiconductor IC having a characteristic pattern including a trademark and a product name displayed on the surface mounted on the wiring board, and a wiring board formed on the wiring board and connected to the chip component. In a hybrid integrated circuit device having connecting stitch lands, the shape of the stitch lands arranged at a position on the wiring board opposite to a side on which a characteristic pattern including the trademark and product name of each chip component is present. can be identified by changing the shape of the stitch land arranged at a position facing the other side.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）、（ｂ）は本発明の第１の実施例の平面図
及びＡ部の部分拡大平面図である。FIGS. 1(a) and 1(b) are a plan view of a first embodiment of the present invention and a partially enlarged plan view of part A.
第１の実施例は、第１図（ａ＞、（ｂ）に示すように、
搭載する半導体チップ１表面上の商標パターン８の存在
する辺に配列された接続パッド５と対応する配線基板２
上のそれぞれのチップ部品接続用のステッチランド４の
マウントランド３側の先端には、高さが２００〜４００
μｍ、底辺幅がステッチランド４の幅に等しい２００〜
５００μｍ程度の三角形状の変形パターン部７が形成さ
れている。In the first embodiment, as shown in FIG. 1 (a>, (b)),
Wiring board 2 corresponding to connection pads 5 arranged on the side where trademark pattern 8 is present on the surface of semiconductor chip 1 to be mounted
At the tip of the mount land 3 side of the stitch land 4 for connecting each chip component above, there is a height of 200 to 400 mm.
μm, the base width is equal to the width of stitch land 4 200 ~
A triangular deformed pattern portion 7 of about 500 μm is formed.
このような変形パターン部７を付加したステッチランド
４を有する配線基板２上に半導体ＩＣチップ１を搭載す
る場合には、変形パターン部７と半導体ＩＣチップ１表
面上の商標パターン８か表示されている辺の接続パッド
５とが一致するよう確認しながら搭載作業を実施する。When the semiconductor IC chip 1 is mounted on the wiring board 2 having the stitch land 4 to which the deformed pattern part 7 is added, the deformed pattern part 7 and the trademark pattern 8 on the surface of the semiconductor IC chip 1 are displayed. Carry out the mounting work while making sure that the connection pads 5 on the same side match.
第２図（ａ＞、（ｂ）は本発明の第２の実施例の平面図
及び８部の部分拡大平面図である。FIGS. 2(a) and 2(b) are a plan view of a second embodiment of the present invention and a partially enlarged plan view of part 8.
第２の実施例は、第２図（ａ）、（ｂ）に示すように、
搭載する半導体チップ１表面上の商標パターン８の存在
する辺に配列された接続パッド５と対応する配線基板２
上のそれぞれのチップ部品接続用のステッチランド４の
マウントランド３側の先端には、例えば、深さがステッ
チランド４の幅に等しく２００〜５００μｍ程度の三角
形状の交互に向きを変えた切欠きが付加された変形パタ
ーン部１１が形成されている。The second embodiment, as shown in FIGS. 2(a) and (b),
Wiring board 2 corresponding to connection pads 5 arranged on the side where trademark pattern 8 is present on the surface of semiconductor chip 1 to be mounted
At the tip of the mount land 3 side of each of the stitch lands 4 for connecting chip components above, there are, for example, triangular notches whose depth is equal to the width of the stitch land 4 and is about 200 to 500 μm, and whose directions are changed alternately. A deformed pattern portion 11 is formed to which a deformed pattern portion 11 is added.
このような変形パターン部１１を付加したステッチラン
ド４を有する配線基板２上に半導体ＩＣチップ１を搭載
する場合には、変形パターン部１１と半導体ＩＣチップ
１表面上の商標パターン８が表示されている辺の接続パ
ッド５とが一致するように確認しながら搭載を実施する
ことにより、第１の実施例と同じ効果が得られる。When the semiconductor IC chip 1 is mounted on the wiring board 2 having the stitch land 4 to which the deformed pattern part 11 is added, the deformed pattern part 11 and the trademark pattern 8 on the surface of the semiconductor IC chip 1 are displayed. The same effect as in the first embodiment can be obtained by carrying out the mounting while checking that the connection pads 5 on the same side match.
以上説明したように本発明は、配線基板上のそれぞれの
チップ部品表面上に形成された商標あるいは製品名表示
パターン等の特徴あるパターンの存在する辺と対向する
配線基板上の位置に配列されたステッチランドの形状を
他辺に配列されたステッチランドの形状に対して変形さ
せ識別できるようにしたことにより、搭載方向確認が容
易となり、従ってミスのないチップ部品搭載作業が実現
できるという効果がある。As explained above, the present invention provides for chip components arranged at positions on a wiring board opposite to the side where a characteristic pattern such as a trademark or product name display pattern formed on the surface of each chip component on the wiring board is present. By changing the shape of the stitch land so that it can be identified by changing the shape of the stitch lands arranged on the other side, it becomes easier to confirm the mounting direction, which has the effect of realizing error-free chip component mounting work. .
第１図（ａ）、（ｂ）は本発明の第１の実施例の平面図
及びＡ部の部分拡大平面図、第２図（ａ）、（ｂ）は本
発明の第２の実施例の平面図及びＢ部の部分拡大平面図
、第３図（ａ）（ｂ）は従来の混成集積回路装置の一例
の平面図及び０部の部分拡大平面図である。
１・・・半導体ＩＣチップ、２・・・配線基板、３・・
・マウントランド、４・・・ステッチランド、５・・・
接続パッド、６・・・１番ピンマーク、７，１１・・・
変形パターン部、８・・・商標パターン、９・・・ボン
ディングワイヤ、ＩＯ・・・導体層。FIGS. 1(a) and (b) are a plan view and a partially enlarged plan view of part A of the first embodiment of the present invention, and FIGS. 2(a) and (b) are the second embodiment of the present invention. FIGS. 3(a) and 3(b) are a plan view of an example of a conventional hybrid integrated circuit device and a partially enlarged plan view of part 0. FIGS. 1... Semiconductor IC chip, 2... Wiring board, 3...
・Mount Land, 4... Stitch Land, 5...
Connection pad, 6...1st pin mark, 7, 11...
Deformed pattern portion, 8... Trademark pattern, 9... Bonding wire, IO... Conductor layer.
Claims (1)
品名を含む特徴あるパターンが表示された半導体ＩＣを
含むチップ部品と、前記配線基板上に形成され前記チッ
プ部品に配線接続するステッチランドとを有する混成集
積回路装置において、それぞれの前記チップ部品の前記
商標と品名を含む特徴あるパターンの存在する辺と対向
する前記配線基板上の位置に配列された前記ステッチラ
ンドの形状を他辺と対向する位置に配列された前記ステ
ッチランドの形状に対して変形させ識別できるようにし
たことを特徴とする混成集積回路装置。a wiring board; a chip component mounted on the wiring board that includes a semiconductor IC on which a distinctive pattern including a trademark and a product name is displayed; and a stitch land formed on the wiring board and connected to the chip component by wiring. In the hybrid integrated circuit device, the shape of the stitch lands arranged at a position on the wiring board opposite to the side on which the characteristic pattern including the trademark and product name of each of the chip components is present is different from the other side. A hybrid integrated circuit device characterized in that the stitch lands arranged at opposing positions are deformed in shape so that they can be identified.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2023681A JPH03228390A (en) | 1990-02-02 | 1990-02-02 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2023681A JPH03228390A (en) | 1990-02-02 | 1990-02-02 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03228390A true JPH03228390A (en) | 1991-10-09 |
Family
ID=12117206
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023681A Pending JPH03228390A (en) | 1990-02-02 | 1990-02-02 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03228390A (en) |
-
1990
- 1990-02-02 JP JP2023681A patent/JPH03228390A/en active Pending
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