JPH03219712A - Balanced type mixer - Google Patents

Balanced type mixer

Info

Publication number
JPH03219712A
JPH03219712A JP1425790A JP1425790A JPH03219712A JP H03219712 A JPH03219712 A JP H03219712A JP 1425790 A JP1425790 A JP 1425790A JP 1425790 A JP1425790 A JP 1425790A JP H03219712 A JPH03219712 A JP H03219712A
Authority
JP
Japan
Prior art keywords
signal
terminal
signal terminal
diodes
bias
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1425790A
Other languages
Japanese (ja)
Inventor
Shigeyuki Tanaami
田名網 茂幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1425790A priority Critical patent/JPH03219712A/en
Publication of JPH03219712A publication Critical patent/JPH03219712A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To attain the use of a local oscillation signal oscillator with a small output by applying a bias to two diodes being components of a mixer so as to decrease the local oscillation signal inputted to a local oscillation signal. CONSTITUTION:An LO signal is inputted to a local oscillation LO signal terminal 2 and an RF signal is inputted to an RF signal terminal 1, then the IF signal subject to frequency conversion obtained by the mixture of the signals is obtained from an IF signal terminal 3. Then a bias voltage is applied from a bias terminal 4 to diodes X1, X2 and the voltage is set so that the conversion loss of the mixers is minimized. The bias voltage is not outputted to an IF terminal 3 by an IF DC branch line 9. Thus, the bias voltage is applied to the diodes X1, X2 to decrease the LO signal inputted to the LO terminal 2 thereby attaining the use of a small output of LO oscillator.

Description

【発明の詳細な説明】 〔産業上の利用分野] 本発明はマイクロ波帯で使用されるミキサに関し、特に
ラットレース形ハイブリッドを使用したバランス形ミキ
サに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a mixer used in a microwave band, and more particularly to a balanced mixer using a rat race type hybrid.

〔従来の技術〕[Conventional technology]

従来、マイクロ波帯で使用するラットレース形ハイブリ
ッドとダイオードで構成されたバランス形ミキサは、第
2図のように構成されている。図において、ラットレー
ス形ハイブリッド5の4個の端子の内、アイソレーショ
ンを持つ2個の端子に高周波(RF)信号端子1、及び
局発(LO)信号端子2を設け、残りの2個の端子とR
F−LO信号短絡用の先端開放線路6との間にそれぞれ
ダイオードXi、X2を逆極性に接続している。
Conventionally, a balanced mixer composed of a rat race type hybrid and a diode used in the microwave band is constructed as shown in FIG. In the figure, of the four terminals of the rat race type hybrid 5, two terminals with isolation are provided with a radio frequency (RF) signal terminal 1 and a local oscillator (LO) signal terminal 2, and the remaining two terminals are terminal and R
Diodes Xi and X2 are connected with opposite polarities to the open-end line 6 for shorting the F-LO signal.

そして、この先端開放線路6に中間周波(IF)信号端
子3を接続している。
An intermediate frequency (IF) signal terminal 3 is connected to this open-ended line 6.

なお、LO信号端子2にはIFリターン10を接続して
いる。
Note that an IF return 10 is connected to the LO signal terminal 2.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のバランス形ミキサは、ダイオードXi、
X2が先端開放線路6を介して逆極性に接続され、かつ
この先端開放線路6にIF信号端子3を接続しているた
め、これらダイオードXI。
The conventional balanced mixer described above has diodes Xi,
Since X2 is connected with opposite polarity via the open-ended line 6, and the IF signal terminal 3 is connected to this open-ended line 6, these diodes XI.

X2にバイアスをかけることができない。このため、L
O信号端子2から入力させるLO倍信号大きくする必要
があり、大きな出力の出るLO信号発振器を使用しなけ
ればならないという問題がある。
Cannot bias X2. For this reason, L
There is a problem in that it is necessary to increase the LO multiplied signal input from the O signal terminal 2, and an LO signal oscillator with a large output must be used.

本発明の目的は、小出力のLO信号発振器を使用するこ
とを可能にしたバランス形ミキサを提供することにある
An object of the present invention is to provide a balanced mixer that makes it possible to use a low output LO signal oscillator.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のバランス形ミキサは、ラットレース形ハイブリ
ッドのアイソレーションを有する2個の端子にそれぞれ
RF信号端子及びLO信号端子を接続し、他の2個の端
子と高周波短絡用の先端開放線路との間にそれぞれ逆極
性で2個のダイオードを接続したミキサに、ダイオード
の一方と先端開放線路との間にDCリターン及びDC阻
止コンデンサを介挿し、かつ先端開放線路に接続したI
F−DC分波器を介してIF信号端子及びバイアス端子
を接続した構成としている。
The balanced mixer of the present invention connects an RF signal terminal and an LO signal terminal to two terminals having rat race type hybrid isolation, respectively, and connects the other two terminals to an open-ended line for high frequency short circuit. A mixer with two diodes connected with opposite polarities between them, a DC return and a DC blocking capacitor inserted between one of the diodes and an open-ended line, and an I connected to the open-ended line.
The configuration is such that the IF signal terminal and bias terminal are connected via an F-DC branching filter.

〔作用〕[Effect]

本発明によれば、2個のダイオードにバイアスを印加す
ることが可能となり、LO信号端子に入力させるLO倍
信号小出力化することが可能となる。
According to the present invention, it is possible to apply a bias to two diodes, and it is possible to reduce the output of the LO multiplied signal input to the LO signal terminal.

〔実施例〕〔Example〕

次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の構成図である。図において
、ラットレース形ハイブリッド5は図示を省略した誘電
体基板上に形成しており、その4個の端子の内、アイソ
レーションを持つ2個の端子にそれぞれ直流阻止用コン
デンサC1,C2を介してRF信号端子1.LO信号端
子2を接続している。また、このLO信号端子2側の端
子にはコンデンサとインダクタンスで構成されるI F
 IJターン7を接続している。一方、残りの2個の端
子とRF−LO短絡用の先端開放線路6との間にダイオ
ードXi、X2を逆極性に接続している。
FIG. 1 is a block diagram of an embodiment of the present invention. In the figure, the rat race type hybrid 5 is formed on a dielectric substrate (not shown), and out of its four terminals, two terminals with isolation are connected to DC blocking capacitors C1 and C2, respectively. RF signal terminal 1. LO signal terminal 2 is connected. In addition, the terminal on this LO signal terminal 2 side has an I F which is composed of a capacitor and an inductance.
IJ turn 7 is connected. On the other hand, diodes Xi and X2 are connected with opposite polarities between the remaining two terminals and the open-end line 6 for RF-LO short circuit.

この場合、一方のダイオードX1と先端開放線路6との
間には、DCリターン8と直流阻止用コンデンサC3を
介挿している。DCリターン8はインダクタンスで構成
される。
In this case, a DC return 8 and a DC blocking capacitor C3 are inserted between one of the diodes X1 and the open-ended line 6. DC return 8 is composed of an inductance.

更に、前記先端開放線路6には一本の信号線6aを接続
し、この信号線6aにはIF−DC分波器9を介してI
F端子3とバイアス端子4をそれぞれ接続している。こ
のIF−DC分波器9はコンデンサとインダクタンスで
構成される。
Furthermore, one signal line 6a is connected to the open-end line 6, and an I
The F terminal 3 and bias terminal 4 are connected to each other. This IF-DC branching filter 9 is composed of a capacitor and an inductance.

この構成によれば、LO信号端子2にLO倍信号入力し
、RF信号端子1にRF信号を入力すれば、これら信号
の混合によって得られた周波数変換されたIF倍信号、
IF信号端子3から得ることができる。そして、このと
きダイオードX1゜X2にはバイアス端子4からバイア
ス電圧が印加され、この電圧はミキサの変換損失が最小
になるように設定される(この実施例の場合は十電圧)
According to this configuration, by inputting an LO multiplied signal to the LO signal terminal 2 and an RF signal to the RF signal terminal 1, the frequency-converted IF multiplied signal obtained by mixing these signals,
It can be obtained from the IF signal terminal 3. At this time, a bias voltage is applied to the diodes X1 and X2 from the bias terminal 4, and this voltage is set so that the conversion loss of the mixer is minimized (10 voltages in this example).
.

このバイアス電圧はIF−DC分波器9によってIP端
子3に出力されることはない。
This bias voltage is not outputted to the IP terminal 3 by the IF-DC branching filter 9.

したがって、このバイアス電圧をダイオードXI。Therefore, this bias voltage is applied to diode XI.

X2に印加することにより、LO端子2に入力させるL
O倍信号小さくすることが可能となり、小出力のLO発
振器を使用することが可能となる。
By applying to X2, L is input to LO terminal 2.
It becomes possible to make the signal O times smaller, and it becomes possible to use a small output LO oscillator.

また、IF信号端子3とバイアス端子4が共通の1本の
線6aにより先端開放線路、換言すればミキサから取り
出されるため、IF−DC分波器9をミキサ外部に取り
付けるように構成することにより、例えばミキサをビン
端子付きのパッケージに搭載する場合には、線6aに相
当する1本のピン端子をパッケージ外に突出させればよ
い。このため、この種のミキサにおいては、IF倍信号
バイアス電圧の入出力を一本のピン端子1本で行うこと
ができ、バイアスをかけないミキサの場合と同じパッケ
ージを使用することもできる。
In addition, since the IF signal terminal 3 and the bias terminal 4 are taken out from the open end line, in other words, the mixer, by a single common line 6a, the IF-DC branching filter 9 is configured to be attached outside the mixer. For example, when the mixer is mounted in a package with a pin terminal, one pin terminal corresponding to the wire 6a may be made to protrude outside the package. Therefore, in this type of mixer, input and output of the IF multiplied signal bias voltage can be performed with one pin terminal, and the same package as in the case of a mixer without bias can be used.

なお、このミキサを送信ミキサとして利用する場合には
、LO信号端子2にLO倍信号入力し、IF信号端子3
にIF倍信号入力することで、RF信号端子1からRF
信号を得ることができる。
When using this mixer as a transmission mixer, input the LO multiplied signal to the LO signal terminal 2, and input the LO multiplied signal to the IF signal terminal 3.
By inputting the IF multiplied signal to the RF signal terminal 1, the RF
I can get a signal.

また、RF信号端子1とLO信号端子2とは互いに交換
することができる。
Further, the RF signal terminal 1 and the LO signal terminal 2 can be exchanged with each other.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ミキサを構成する2個の
ダイオードにバイアスを印加することができるため、L
O信号端子に入力させるLO信号を小さくでき、小出力
のLO信号発振器の使用が可能となる。また、IF−D
C分波器を外付けすることで、パッケージしたミキサの
一本のピン端子を利用してIF倍信号入出力とバイアス
電圧の印加を行うこともできる。
As explained above, in the present invention, since bias can be applied to the two diodes constituting the mixer, L
The LO signal input to the O signal terminal can be made small, and a small output LO signal oscillator can be used. Also, IF-D
By attaching a C branching filter externally, it is also possible to input/output the IF multiplied signal and apply a bias voltage using one pin terminal of the packaged mixer.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の構成図、第2図は従来のバ
ランス形ミキサの構成図である。 1・・・RF信号端子、2・・・LO信号端子、3・・
・IF信号端子、4・・・バイアス端子、5・・・ラッ
トレース形ハイブリ・7ド、6・・・先端開放線路、7
・・・IFリターン、8・・・DCリターン、9・・・
IF−DC分波器、10・・・IFリターン、XI、X
2・・・ダイオード、CI、C2,C3・・・DC阻止
コンデンサ。 (Ir)
FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional balanced mixer. 1...RF signal terminal, 2...LO signal terminal, 3...
・IF signal terminal, 4... Bias terminal, 5... Rat race type hybrid, 7 lead, 6... Open end line, 7
...IF return, 8...DC return, 9...
IF-DC branching filter, 10...IF return, XI, X
2...Diode, CI, C2, C3...DC blocking capacitor. (Ir)

Claims (1)

【特許請求の範囲】[Claims] 1、誘電体基板上に形成したラットレース形ハイブリッ
ドと、このハイブリッドのアイソレーションを有する2
個の端子にそれぞれ接続した高周波信号端子及び局発信
号端子と、前記ハイブリッドの他の2個の端子と高周波
短絡用の先端開放線路との間にそれぞれ逆極性で接続し
た2個のダイオードと、これらダイオードの一方と前記
先端開放線路との間に介挿した直流リターン及び直流阻
止コンデンサと、前記先端開放線路に接続した中間周波
・直流分波器と、この分波器にそれぞれ接続した中間周
波信号端子及びバイアス端子とを備えることを特徴とす
るバランス形ミキサ。
1. A rat race hybrid formed on a dielectric substrate, and 2.
a high frequency signal terminal and a local signal terminal respectively connected to the terminals of the hybrid, and two diodes connected with opposite polarities between the other two terminals of the hybrid and the open-ended line for high frequency short circuit, respectively; A DC return and DC blocking capacitor inserted between one of these diodes and the open-ended line, an intermediate frequency/DC splitter connected to the open-ended line, and an intermediate frequency/DC splitter connected to the splitter, respectively. A balanced mixer characterized by having a signal terminal and a bias terminal.
JP1425790A 1990-01-24 1990-01-24 Balanced type mixer Pending JPH03219712A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1425790A JPH03219712A (en) 1990-01-24 1990-01-24 Balanced type mixer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1425790A JPH03219712A (en) 1990-01-24 1990-01-24 Balanced type mixer

Publications (1)

Publication Number Publication Date
JPH03219712A true JPH03219712A (en) 1991-09-27

Family

ID=11856040

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1425790A Pending JPH03219712A (en) 1990-01-24 1990-01-24 Balanced type mixer

Country Status (1)

Country Link
JP (1) JPH03219712A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008152852A1 (en) * 2007-06-14 2008-12-18 Kyocera Corporation Current blocking circuit, hybrid circuit device, transmitter, receiver, transmitter-receiver, and radar device
JP2012209878A (en) * 2011-03-30 2012-10-25 Furukawa Electric Co Ltd:The Balanced mixer, quadrature modulation/demodulation device and radar device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008152852A1 (en) * 2007-06-14 2008-12-18 Kyocera Corporation Current blocking circuit, hybrid circuit device, transmitter, receiver, transmitter-receiver, and radar device
US8179304B2 (en) 2007-06-14 2012-05-15 Kyocera Corporation Direct-current blocking circuit, hybrid circuit device, transmitter, receiver, transmitter-receiver, and radar device
JP5171819B2 (en) * 2007-06-14 2013-03-27 京セラ株式会社 DC blocking circuit, hybrid circuit device, transmitter, receiver, transceiver, and radar device
JP2012209878A (en) * 2011-03-30 2012-10-25 Furukawa Electric Co Ltd:The Balanced mixer, quadrature modulation/demodulation device and radar device

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