JPH0321948B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern recognition device that classifies sample patterns into a plurality of classes based on statistical features.

Conventionally, some statistical feature quantities are obtained for a certain pattern, these are used as feature vectors, and a certain distance between a position in this feature space and a position for a plurality of predetermined classes is compared, A pattern recognition method is used that determines that a pattern belongs to the class with the smallest distance. A conventional pattern recognition device will be described with reference to FIG. The feature amounts of the pattern are sent sequentially on the data bus 1. Arithmetic unit group 2 exists as many as the number of classes, calculates the distance between the feature quantity on data bus 1 and the feature quantity of each class stored in register 3, and sends the result (distance) to the data. - Output to bus group 4. The comparator 5 compares the distance data of the data bus group 4 and outputs the number of the smallest value class to the output line 6 as a recognition result.

However, the above-mentioned device had the following drawbacks. First, when recognizing each pattern at high speed, feature quantities are sent one after another to the data bus 1, but if there are many classes, the comparator 5
Since a large amount of distance data is simultaneously input from the data bus group 4, very high speed is required to calculate the minimum value. Second, the total number of classes varies depending on the target of pattern recognition, but
With the configuration shown in Figure 1, it is not easy to expand or expand the equipment.
It is difficult to reduce the size.

An object of the present invention is to provide a high-speed pattern recognition device for an object in which many sample patterns need to be recognized one after another without using a particularly high-speed circuit.

Another object of the present invention is to provide a pattern recognition device that can be easily adapted to objects having different total numbers of classes without changing the recognition speed.

The configuration of the present invention will be explained with reference to the embodiment shown in FIG. The invention consists of a chain of building blocks 7 arranged in series. There are as many structural units 7 as there are classes to be recognized, and each sample and hold the feature amount of each pattern sent over the data bus 1 from the previous structural unit 7 at a fixed time interval, and then select the next structure. unit 7
a first latch 8 that outputs an output to the first latch 8; a second latch 14 that samples and holds the distance transmitted on the data bus 11 from the previous structural unit 7 at regular intervals; a third latch 15 that samples and holds the class number sent as the class signal 13 from 7 at regular intervals;
A register 3 in which feature quantities of each class are stored, and an arithmetic unit that calculates the distance in the feature space between the feature quantities stored in the register 3 and the feature quantities held in the first latch 8. 2, the distance that is the output of the arithmetic unit 2 and the distance obtained from the previous structural unit 7 held in the second latch 14 are compared, and the minimum value is transferred to the next structural unit 7 via the data bus 11. and outputs the comparison result to the signal line 12, and the comparison result obtained from the signal line 12 determines whether the class number of the current structural unit 7 or the stage held in the third latch 15 is determined. It consists of a gate 10 which switches the similar signal obtained from the previous constituent unit 7 and outputs it to the next constituent unit 7 via a data bus 13.

Next, the operation of the embodiment of the present invention will be explained in detail with reference to FIG. The apparatus shown in FIG. 2 classifies patterns into N (integer) classes. In this example, the pattern consists of four features (x, y, z,
w) and are sent cyclically and sequentially on data bus 1. The feature quantity is held in the first latch 8 for one cycle. The arithmetic unit 2 of the i-th structural unit 7 holds (x, y, z, w) and the value of the i-th class feature quantity (x _i , y _i , z _i ,
w _i ). For example, if the Euclidean distance is used as the distance in the object of the problem, the calculation result d _i is calculated by equation (1).

d _i =√( _-i ) ² +(- _i ) ² +(-
_i ) ² +(- _i ) ² (1) The comparator 9 receives the data obtained from the comparator 9 of the preceding component 7 via the data bus 11 and held in the second latch 14 up to the previous stage. The minimum distance is compared with the distance obtained by the arithmetic unit 2 of the constituent unit 7, and the smaller value is output to the data bus 11 to the next stage. Furthermore, if the distance obtained at this stage is smaller, a gate signal is output to the signal line 12. The gate circuit 10 usually outputs the class number corresponding to the minimum distance to the previous stage obtained by the class signal 13 and held in the third latch 15 as it is as the class signal 13 to the next stage. line 12
When there is a gate signal in this stage, the class number i of this stage is
Output.

The above operations are executed simultaneously in each stage, and the feature amount of the pattern and its accompanying minimum distance and class number progress one stage at a time to the right in FIG. 2 at every synchronization. At this time, as a recognition result, the feature amount of the unknown pattern is given to the first stage, and after N cycles, the class number to which the pattern belongs is obtained as the output of the Nth stage one after another in the class signal 13. Further, on the data bus 11, the distance between the feature and the feature of the class to which it belongs is obtained. Since there is no previous stage for the first stage, a very large value may be given to the data bus 11, but as shown in FIG. can also give 0. In this case, dmax is the limit distance allowed for each class,
If the input pattern has a distance greater than this dmax from any class, 0 is obtained as the recognition result. This indicates that the input pattern was not classified into any class and was rejected.

According to the present invention, even when the total number of classes N is very large and classification into a large number of classes is required, the recognition process can be performed at high speed because feature amounts are accepted every cycle.

Further, in the present invention, since the device is in the form of a series connection of the structural units 7, it is easy to expand and contract. For example, when adding a new type to an existing device, all you need to do is simply connect the structural unit 7 to the (N+1)th stage, (N+2)th stage, etc. without making any changes to the previous parts. It can be expanded, and unnecessary classes can be deleted for each constituent unit 7.

As described above, according to the present invention, it is possible to configure a pattern recognition device that is high-speed and can be easily expanded and reduced.

In the above-described embodiment, the plurality of feature quantities are simultaneously sent on the data bus 1 through separate signal lines, but they may be transmitted serially by time division. In this case, the first latch 8 needs to have the function of switching and holding data that is sent sequentially. In addition, in the embodiment, the distance between the feature quantities calculated by the computing unit is the Euclidean distance, but when pattern recognition is performed using the maximum likelihood method, this distance becomes the Mahalanobis distance, and when there are four features, the equation
Calculate (2).

di=x−x _i y−y _i z−z _i w−w _i ^t・Σ ^-1 _i・x−x _i y−y _i z−z _i w−w _i +1 _o ｜Σ _i ｜ (2) In Equation (2), Σ _i represents the covariance matrix of the i-th class of features, Σ ⁻¹ _i represents its inverse matrix, and |Σ _i | represents the value of the determinant. In addition, various distances can be used depending on the purpose of the device. Furthermore,
The concept of probability can also be used instead of distance as a relation of belonging to a pattern class. In this case, the calculator 2 calculates the probability P _i that the pattern belongs to the i-th class, the comparator 9 compares this P _i with the maximum probability up to the previous stage, and sends the larger value to the next stage. communicate,
If P _i is large, a gate signal is generated at 12. 1
The data given to the data bus 11 to the comparator in the third stage is the minimum allowable distance Pmin instead of dmax.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional pattern recognition device, and FIG. 2 is a block diagram of a pattern recognition device of the present invention. In the figure, 1 is a data bus through which feature quantities are transmitted, 2 is an arithmetic unit, 3 is a register, and 8 is a first
9 is a comparator, 10 is a gate, 14 is a second latch, and 15 is a third latch.

Claims (1)

[Claims] 1 The first latch samples and holds the feature values of each pattern sent from the previous structural unit at regular intervals, and transmits them to the next structural unit, and also the distance sent from the previous structural unit. A second latch that samples and holds the class number sent from the previous structural unit at regular intervals, and a third latch that samples and holds the class number sent from the previous structural unit at regular intervals, and sets the feature values of each class. register and
The feature quantity stored in the register and the first
an arithmetic unit that calculates the distance in the feature space between the feature value held in the second latch, and a distance that is the output of the arithmetic unit and the distance obtained from the previous structural unit held in the second latch. A comparator that compares the distances and sends the minimum value to the next constituent unit and outputs the comparison result, and a comparator that compares the distance and sends the minimum value to the next constituent unit and outputs the comparison result. A pattern recognition device characterized in that a number of constituent units each consisting of a gate that switches a class number obtained from a constituent unit and sends it to the next constituent unit are connected in series as many as the number of classes.