JPH03218648A - Position detecting device - Google Patents

Abstract

PURPOSE:To make it possible to detect favorably the feed position of an object by a method wherein reference pattern position information within a region including an image region in an entire feed state is previously stored and this information is compared with reference pattern position information within the image region. CONSTITUTION:A picture signal 8 from an imaging device 6 is processed by a processing circuit, which is started by a starting signal from a control circuit 11, referring to reference patterns which are previously stored in a memory circuit. In the processing circuit, an image region is divided into a plurality of pieces of sections respectively in the X-axis and Y-axis directions and the existence of the reference patterns in the respective sections is detected. A combination of the positions of reference patterns, which have a relative positional relation identical with that of a plurality of partial patterns detected in an observation region, among the positions of a plurality of the stored reference patterns is selected Thereby, even the case where there is a possibility that the partial pattern of part determined previously among the partial patterns stops existing within the image region, the position of an object is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a position detection method for detecting the position of an object using a video pattern captured by a television camera or the like.

For example, there is a method of extracting a target pattern from images captured by an imaging device such as a television camera, distinguishing it from other patterns and background patterns, and determining the position of the target pattern within the two-dimensional image. 52-1411
It has been known from the past as shown in Publication No. 2 and Japanese Unexamined Patent Publication No. 52-91331.

In this method, the only partial pattern existing within the pattern of the imaging area is defined as a standard pattern, and position detection is performed by finding the position of the partial pattern that most closely matches this standard pattern. However, when the imaging magnification is increased, it becomes difficult to find the only partial pattern that exists in the imaging area. However, with this method, if there are multiple patterns that match the standard pattern within the imaging area,... ljjl+1! Even if the position of a partial pattern that matches the I pattern is detected, it is not known where the partial pattern is located on the object, so the position of the object cannot be determined based on the position of the partial pattern. Undetectable. Therefore, the following method has been proposed in the prior application (Japanese Unexamined Patent Publication No. 5-13-88-54). This method detects all partial patterns that match one standard pattern, compares their relative positional relationships, and detects combinations of some partial patterns that have predetermined relative positional relationships. By this, the position of some predetermined partial patterns is detected, and the position of the object can be detected based on the determined position.

However, the method according to this prior application is based on the premise that some of the plurality of partial patterns having the above-mentioned predetermined relative positional relationship are all present in the imaging region. However, if the magnification of the imaging device becomes high or if a deviation in the supply of the object occurs, the partial patterns will not necessarily all fall within the imaging area. In such a case, the method of the earlier application mentioned above cannot be applied.

An object of the present invention is to use partial patterns located at a plurality of locations on an object as a standard pattern, and to prevent a predetermined partial pattern from existing in an imaging area among the plurality of partial patterns that match the standard pattern. An object of the present invention is to provide a position detection device capable of detecting the position of an object even when there is a problem.

In order to achieve such an object, in the present invention, for an entire area larger than a partial area that is set on an object and imaged by an imaging device, that part is set at a plurality of positions within the pattern of the entire area. With the pattern. The positions of at least one type of standard pattern existing in the an area are stored in advance, and the positions of a plurality of partial patterns that match the standard pattern are detected from the pattern signal belonging to the an area, and the positions of the plurality of stored standards are detected. The feature is that the position of the object is detected by selecting a combination of standard pattern positions that have the same relative positional relationship as the relative positional relationship of a plurality of partial patterns detected in the observation area from among the pattern positions. There is.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the configuration of an automatic wire bonding apparatus for performing wire bonding onto a semiconductor pellet to which the position detection method according to the present invention is applied.

In the figure, when a semiconductor pellet 1 is supplied by a moving device 2, its image is projected onto an imaging plane 7 in an imaging device 6 via an objective lens 4 of a microscope [3] and a mirror 5. The video signal 8 obtained by this imaging device 6 enters the position detection device N9 according to the present invention as described later, where video processing is performed and a signal 10 representing the position coordinates of the target pattern on the object is obtained. It will be done. This position coordinate signal 1
0 is input to the control circuit 11, and a control signal 12 for marking operation is obtained at an appropriate time and sent to the XY servo mechanism 13 and the bonding mechanism 14 mounted thereon. As a result, the XY servo mechanism 13 is moved and the bonding mechanism 14 is moved to a predetermined position. An arm 15 having a capillary 16 at its tip is attached to this bonding mechanism 14, and by the above movement, the capillary 16 is moved to a position opposite to a desired position on the semiconductor pellet 1, and a control signal from the control circuit 11 is transmitted. 12, bonding is performed on the semiconductor pellet 1.

Note that the control circuit 11 is constituted by a processing device such as an electronic computer.

FIG. 2 shows the configuration of an embodiment of the position detection device 9 of FIG. 1 according to the present invention.

In the figure, a video signal 8 from an imaging device 6 is processed by a processing circuit 32 activated by an activation signal from a control circuit 11 with reference to a standard pattern stored in a storage circuit 31 in advance.

First, the processing by the processing circuit 32 will be explained.

FIG. 3 shows an example of a pattern of an object such as a semiconductor pellet 1, and the area 20 sufficiently covers the area even if the imaging area moves due to supply deviation. Further, a region 21 indicates an imaging region in a state where there is no supply shift.

FIG. 4 shows an example of the characteristic shape portions shown in FIG. 3, and these characteristic shape portions are stored in the storage circuit 31 as S+* patterns.

FIG. 6 shows an example of a video pattern within the imaging area 21 when an object is being supplied, and is input as a video signal 8 to the position detection device 119.

The processing circuit 32 divides the imaging area 21 in FIG. 6 into a plurality of sections in the horizontal and vertical directions, that is, in the X-axis and y-axis directions, as shown in FIG. Detect the presence of the standard pattern shown in the figure. The detection results are shown in FIG.

Numbers 1 to 4 in the figure are standard patterns (1) to 4 in Figure 4.
(4) is supported.

The results obtained in the processing circuit 32 in this way are stored in the storage circuit 33 in the form of the type of standard pattern, its XtV position coordinates, and the coordinates (i, j) of the section where the standard pattern exists. The area 20 of the pattern shown in FIG.
It is divided into a plurality of sections in the axial direction, and the position coordinates of the drifting patterns (1) to (4) in FIG. 4 in each section are detected in advance, and the results are shown in FIG.

In the present invention, the position information shown in FIG.
Locus 1 of the section where the position coordinates and its standard pattern exist
? It is stored in the memory circuit 34 in the form of l(I, J).

Note that regions 20' and 21' in FIG. 5 are the third regions, respectively.
This corresponds to areas 20 and 21 in the figure.

The processing circuit 35 in FIG. 2 detects where in FIG. 5 a portion that satisfies the positional relationship of the standard pattern shown in FIG. 7 is located, and thereby detects the supply position of the object. The result is stored in storage circuit 36. When the processing in the processing circuit 35 is completed, the processing circuit 32 takes in the contents of the storage circuit 36 and sends it to the control circuit 11.

Next, details of the processing in the processing circuit 32 will be explained.

FIG. 8 shows an example of a specific configuration of the processing circuit 32 shown in FIG.

In the figure, 6 indicates an imaging device such as a television camera shown in FIG. 2, and 41 indicates a clock generation circuit. A clock signal 41S output from the clock generation circuit 41 is input to the XY coordinate counter 42. The XY coordinate counter 42 includes an X coordinate force counter that counts the clock signal 41S to obtain the X coordinate of the imaging screen, and a Y coordinate counter that counts the carry signal 4.2c of this X coordinate counter to obtain the Y coordinate of the imaging screen.
It consists of a coordinate counter. 43 is a synchronization signal generation circuit. A synchronization signal 43S necessary for screen scanning of the imaging device 6 is generated based on the count value of the XY coordinate counter 42.

The imaging device 6 raster-scans the image plane in synchronization with the synchronization signal 435 and outputs the image signal 8. This video signal 8 is converted by the binarization circuit 44 into a binary signal 44S indicating whether the projected color of the picture element is "white" or "black", and is supplied to the video memory 45.

As the video memory 45 and the partial pattern cutout circuit indicated by reference numeral 46, for example, the type shown in Japanese Patent Publication No. 14112/1983 can be applied.

In other words, the video memory 45 stores 2 times the number of scanning lines (n-1).
It consists of n-1 shift registers connected in series to temporarily store digitized image information, and the output signals of these registers and the binary signal 44S are not aligned vertically on the imaging screen. It corresponds to n picture elements in a positional relationship. Therefore, the above-mentioned n picture element signals are taken out in parallel from the video memory 45 and are transferred to the partial pattern cutout circuit 46 which is made up of n shift registers each having a length of n bits.
If the information is derived as parallel information of nXn bits, partial patterns of nXn picture elements corresponding to the scanning position of the image will be extracted one after another.

Reference numeral 47 is a register for holding a standard pattern consisting of information of nXn picture elements to be compared with the partial pattern, and stores the standard pattern selectively outputted from the storage circuit 31 of FIG. The contents of this register 47 and the output of the partial pattern cutout circuit 46 are compared and verified for each corresponding bit by the comparison and addition circuit 48, and the total number of bits whose contents match is a signal indicating the degree of matching between the partial pattern and the standard pattern. It is output as 48S. Circuit 45, 46.48
operates in synchronization with the clock signal 41S, so the coincidence degree signal 485 is activated one after another in parallel with the scanning of the image plane.

Reference numeral 50 denotes an area dividing circuit which operates in synchronization with the clock signal 41S and receives an X counter carry signal 42C output from the XY coordinate counter 42 and an XY coordinate signal 49 (4
9X, 49Y), it is determined whether the current scanning point is within the effective imaging area, that is, the search area. If it falls within the search area, a match comparison instruction signal 51 is output. This circuit also divides the search area into a plurality of sections and generates an address signal 52 (52X, 52Y) indicating which section the scanning point belongs to. This address signal 52 is applied to a coincidence degree memory 56 and a coordinate memory 57 via an address switching circuit 55.

The coincidence degree memory 56 has a storage area corresponding to the address signal 52, and is capable of storing the maximum degree of coincidence between the partial pattern and the standard pattern up to the present moment for each section corresponding to the address in the search area. That is, the contents of the addressed storage area of memory 56 are reflected by signal 56S.
The matching signal 485 is read out from the matching signal 485 and input to the comparison circuit 59 together with the matching signal 485 successively outputted from the matching and adding circuit 48 .

The comparison circuit 59 outputs a pulse signal 598 when the newly determined degree of coincidence 48S is greater. This pulse signal 59S is input to an AND gate 54 whose opening/closing is controlled by the coincidence degree comparison instruction signal 51.
The pulse 54S is output from the AND gate 54 only during the output period of , and becomes a pulse 54S that enables data updating in the memories 56 and 57. Therefore, the 1M degree memory 56 can store the new degree of coincidence given by the signal 48S in the storage area corresponding to the address signal 52 in response to the pulse signal 54S.

On the other hand, the coordinate memory 57 has a coordinate storage area corresponding to the address signal 52, similar to the coincidence degree memory 56,
When the pulse signal 54S is applied, the coordinate data 495 output from the XY coordinate counter 42 is stored in the addressed storage area.

Since the screen scan is repeated in the X direction while shifting the position in the Y direction, the addresses of the sections within the search area also change one after another according to the above screen scan, and at the end of one screen scan, the standard pattern for all sections is The maximum degree of coincidence between the pattern and the partial pattern and the position meditation of the partial pattern are stored in the memories 56 and 57.

Reference numeral 60 denotes a control device, such as a computer, which is equipped with information input/output, sequence control, numerical control, and data judgment functions. When the control device 60 receives the activation signal 10A from the external control circuit 11, it starts a control operation according to a preprogrammed procedure. First, the required standard pattern storage circuit 31 is read out, and the pattern signal 62 is sent to the register 47, and the ? Parameters such as the modulus d2, d2, the number of divisions in the X and Y directions, and the starting points Xs and Ys of the search area are sent as a signal 63 to the area dividing circuit 50. Further, clear signals 64 and 65 are applied to the coincidence degree memory 56 and coordinate memory 57 to clear the contents of the memories, and then a switching signal 66 is applied so that the address switching circuit 55 can output the address from the area division circuit 50. Output.

When these preprocessing operations are completed, the control circuit 60 sends a pattern detection operation start instruction signal 67 to the area division circuit 50. When the area division circuit 50 receives the instruction signal 67, it starts an operation for pattern detection at the timing when the screen scanning of the imaging device WL6 returns to the initial position, and outputs the end signal 53 when one screen scan is completed. and notifies the control device of the end of the pattern detection operation.

When receiving the end signal 53, the control device 60 outputs a switching signal 66, and the address switching circuit 55 makes the memories 56 and 57 accessible by the address signal 68 output from the control device. 1!6
0 reads out the matching degree of each section stored in the matching degree memory 56 one after another to determine whether it is greater than or equal to a predetermined value, and if it is greater than or equal to the predetermined value, the coordinate value is read out from the coordinate memory 57 and is used as the standard pattern at that time. It is written into the storage circuit 33 on the control device side together with information indicating the type of the block and the coordinates of the section corresponding to the address signal 68.

When the processing for one standard pattern is completed in this way, the next standard pattern is read out from the storage circuit 31 and the same operation as described above is repeated.

Then, the same operation is performed for all standard patterns, and when all processing is completed, an activation signal, which will be described later, is sent to the processing circuit 35. When the processing in the processing circuit 35 is completed, the processing circuit 32 takes in the contents of the storage circuit 36 in response to an end signal, and sends it to the control circuit 11 as a signal 10B.

Next, the specific configuration of the area dividing circuit 50 will be explained with reference to FIG.

This circuit consists of an X address control section and a Y address control section, 70X and 70Y are registers for holding the coordinates Xs and Ys of the search starting point, respectively, and 71X and 7
1Y is the dimension d in the X and Y directions of one section to be divided
2, registers for holding d1, 72X and 72Y are registers for holding the number of sections net n in the X direction and Y direction, and the parameters held in each of these registers are controlled as a signal line 63. It is sent from the device 60. Also. 73X, 73Y, 74X, 74Y, 75X
, 75Y is a coincidence detection circuit, 76X, 76Y, 77X, 7
7Y is a counter, 78X, 78Y, 79 are flip-flops, 80X, 80Y, 81.84 are AND gates.
82X, 82Y, 83X, and 83Y indicate OR gates, respectively.

First, the operation will be explained from the X address control section.The coincidence detection circuit 73X
The coordinate 49X is compared with the coordinate XS of the search start point held in the register 70X, and when they match, a pulse signal 90X is output. This pulse signal 90X sets the flip-flop 78X and also sets the OR gates 82X and 83X.
The values of counters 79X and 77X are each reset to zero via. When flip-flop 78X becomes set, its output opens AND gate 80X,
The basic clock 418 is input to the counter 76X one after another, and a counting operation is started.

The coincidence detection circuit 74X outputs a pulse signal 91X when the value of the counter 76X matches the horizontal information d2 of one division section held in the register 71X. This pulse signal 91X is input to the counter 77X and the count value is
Along with fi, the counter 7 is input through the OR gate 82X.
6X reset terminal. Therefore, counter 4
6X repeats the counting operation for each counter value equal to the width of the divided section, and advances the value of the counter 77X each time the scanning point moves from one section in the X direction to the next section. Further, the contents of the counter 77X are values indicating which section in the horizontal direction the scanning is being carried out.
This value is output as a signal 52X indicating the X address of the section.

The coincidence detection circuit 75X compares the value of the counter 77X with the designated number n2 of sections in the X direction held in the register 72X, and outputs a pulse signal 92X when they match. The pulse signal 92X is input to the reset terminal of the counter 77X via the OR gate 83X, returns its value to zero, resets the flip-flop 78X, and resets the A N
D gate 80X is closed to block input of basic clock 415. Since these operations are repeated for each horizontal scanning line, the signal 52X indicating the X address of the divided section within the search area is repeatedly output.

Next, the Y address control section will be explained. The Y address control unit receives an instruction signal 6 from the control device 60 to start the detection operation.
When 7 is output, flip-flop 79 is set and AND gate 84 is opened. Coincidence detection circuit 73Y
is the Y coordinate 4 of the scanning point output from the coordinate counter 42
9Y and the coordinate Y of the search starting point held in register 70Y
s and when they match, a pulse signal 90Y is output. This pulse signal 90Y is applied to OR gates 82Y, 83
counters 76Y, 77Y are reset via Y, and if A N D gate 84 is open, flip-flop 78Y is set via it. by this,
AND gate 80Y is opened and coordinate counter 42 to 1
The carry signal 42C outputted for each horizontal scanning line is input into the counter 76Y one after another, and a counting operation is started.

The coincidence detection circuit 76Y outputs a pulse signal 91Y when the value of the counter 76Y matches the vertical width d of one divided section held in the register 71Y. This pulse signal is input to the counter 77Y to increment the count value by 1, and is also input to the reset terminal of the counter 76Y via the OR gate 82Y to reset the value. Therefore, the counter 76Y repeats the counting operation with the same count value in the vertical direction of the divided sections, and the counter 77Y repeats the counting operation every time the scanning point moves from one section in the Y direction to the next section.
This will cause the count to work.

The content of the counter 77Y is a value indicating which section in the vertical direction is being scanned, and this value is output as a signal 52Y indicating the Y address of the section. The signal 52Y is given to the coincidence degree memory 56 and the coordinate memory 57 together with the signal 52X indicating the X address.

The coincidence detection circuit 75Y compares the value of the counter 77Y with the designated number n of sections in the vertical direction held in the register 72Y, and outputs a pulse signal 82Y when they match. This pulse signal 92Y resets the counter 77Y via the OR gate 83Y, and at the same time resets the flip-flop 78.
Reset Y,79. Further, the pulse signal is sent to the control circuit 60 as a completion signal 53 of the designated pattern detection process.

Since the flip-flop 78Y is in the on state for exactly one scanning period of the search area, its output signal 9
3 and the output signal 94 of the AND gate 80X of the X address control section is taken out from the AND gate 81, thereby obtaining the coincidence degree comparison instruction signal 51.

Next, details of the operation of the processing circuit 35 shown in FIG. 2 will be explained.

FIG. 10 shows an example of a specific configuration of the processing circuit 35, where 100 is a bus line 101 for connecting between the processing circuits 32, 35 and the memory circuit 33 in FIG. 2, and 102 is a gate. circuit, 103 is a sequence, 104
105 represents a storage circuit that stores a microprogram, and 105 represents an arithmetic unit (ALU).

In such a configuration, when the processing in the processing circuit 32 described above is completed and the activation signal is sent to the activation circuit 101 through the bus line 100, this circuit 101 closes the gate circuit 102 and stores the memory circuits 33 and 34. and 36 from the bus line 100, while the sequencer 103
is activated, and the memory circuit 10 is activated by this sequencer 103.
The microprograms in 4 are sequentially read out, and the arithmetic circuit 1
Send to 05. The arithmetic circuit 105 uses the contents of the memory circuits 33 and 34 to perform the following operations according to the microprogram from the memory circuit 104, and stores the results in the memory circuit 36.

When the processing in the arithmetic circuit 105 is completed, the memory circuit 104
A termination signal is sent to the starting circuit 101, whereby the gate circuit 102 connects the bus line 100 and the memory circuits 33, 34, 36 again, while the pass line 1
00 to inform the processing circuit 32 of the end of processing in the processing circuit 35.

Thereby, the processing circuit 32 reads out the contents of the storage circuit 36 and sends it to the control circuit 11 in FIG.

Next, details of the processing in the arithmetic circuit 105 will be explained.

As mentioned above, the memory circuit 33 stores the patterns detected from the pattern within the imaging area imaged by the imaging device 6 of FIG.
The type of target pattern, its X, Y position coordinates, and the coordinates (ITJ) of the section where the standard pattern exists are stored in the memory circuit 34, and the i-image area moves due to the supply deviation. The type of standard pattern that exists in the image pattern of a certain area of the object including that area, its X, Y position, and the position WR of the section where the standard pattern exists.
(X, Y) is stored.

Therefore, the arithmetic circuit 105 reads out the contents of these memory circuits 33 and 34, and stores the position coordinates (i.j) of the section stored in the memory circuit 33, the type of standard pattern existing in that section, and the stored information. The position locus It(I, J) of the section stored in the circuit 34 is compared with the type of standard pattern existing within that section. FIGS. 11 and 12 show the types of standard patterns that exist within the sections of the predetermined area, and correspond to FIGS. 5 and 7, respectively. The numbers in the sections in these figures represent the types of standard patterns existing in that section, and correspond to (1) to (4) in FIG. 4.

When comparing the contents of the memory circuits 33 and 34, the first
Position coordinates (i, j) of the section in Figure 2 = (1 to 9, 1 to 7
) and the position coordinates (I.J) of the section in Figure 11 = (1 to 9
, 1 to 7), and count the number of identical standard patterns in the corresponding sections, that is, the number of matching numbers in the corresponding sections.

Next, the position coordinates (I, J) that are shifted to the right by one block from the above-mentioned position coordinates in Figure 12 and Figure 11 = (2 to 10, 1
-7) and count the number of matching numbers in the corresponding sections. In this way, the imaging area in FIG.
The area in the figure is moved sequentially in parallel and the above-mentioned number is counted.

In this way, finally, the plot coordinates (xy
j) = (1-9, 1-7) and the block coordinates (I
, J)=(10-18, 8-14), a matching section is found at the position of the imaging area where the matching count value is the maximum value.

In the examples shown in FIGS. 11 and 12, A in FIG. 11 and ai in FIG. (1+j)? (Eng., J) is (1.1), (4.7
) is the maximum number of matching partitions in the partitioned area.

The matching section A++ at (i=1
Xl3' drift and X of the coincident drift pattern in ~11)
, Y coordinates are taken out from the storage circuits 33 and 34, respectively. Here, the position coordinates of the standard pattern in sections A1 and at are (Xt, yt) and (Xt, Y+
) (i=1 to l1).

In addition to the above-mentioned information, the storage circuit 34 also stores the coordinates (xa,
ya) is stored, and this coordinate (X a , Y
a) is read from the memory circuit 34.

The amount of supply deviation (U a , V a ) in the X and Y directions at this specific position coordinate (xa, ya) is determined by two sets of position information ( xm+3'b) (X k, Y k
) and (X J ty J)
By using (X J ?YJ), (k≠j
), can be obtained by performing the following calculations.

Ua=Xa Xa Va=ya Ya However, xa=K1 (xb-xJ)-K2 (yh-yr)+
XJ'/a=Kz ()l XJ) -Kt (yh
yj)″″y· The supply deviation amount (Ua, Va) thus determined is stored in the memory circuit 36.

FIG. 13 shows an example of a specific configuration of the startup circuit 101 shown in FIG. 10, which is composed of a flip-flop 106. This flip-flop 106 is set by an activation signal 107 from the bus line 100, and its set output signal 108 closes the gate circuit 102 and activates the sequencer 103. On the other hand, when the calculation in the calculation circuit 105 ends, the flip-flop 106 is reset by the completion signal 109 sent from the storage circuit 104, and its reset output signal 110 is sent to the bus line 100, and the output signal 108 causes the flip-flop 106 to be reset by the completion signal 109 sent from the storage circuit 104. will be held.

In the above example, the case where there are four types of standard patterns has been described, but the present invention is not limited to this, and the number of standard patterns may be one type.

In the above example, as shown in FIGS. 5 and 7, the area set in advance on the object and the pattern of the imaging area of the object are divided into a plurality of sections, and each section is entered. The type and position coordinates of the standard pattern on the pattern are detected, but instead of dividing it into sections, the type and position coordinates of the standard pattern on the pattern are detected, and the type and position coordinates of the standard pattern on the pattern are detected. The positional coordinates of the above standard patterns may be compared to determine the position of the imaging area on the preset area, and the supply deviation amount of the object may be determined.

In this case, the standard pattern existence area is set by giving a certain spread to the position coordinates of the standard pattern on the setting area, and the existence area and the position coordinates of the standard pattern on the imaging area are compared to It may also be possible to deal with deviations in the supply angle. Further, the position coordinates of the standard pattern on the imaging area may have a certain spread, or the position coordinates of the standard pattern in both the setting area and the imaging area may have a certain spread.

As described above, according to the present invention, an area is set that includes the imaging area in all possible supply states of the object, and position information of a standard pattern within that area is stored in advance. By comparing the information with the position information of a standard pattern within the imaging area, the supply position of the target can be detected without moving the imaging device or the target, regardless of the supply deviation of the target. be able to.

Further, according to the embodiment of the present invention, the setting area and the imaging area are divided into a plurality of sections, and by comparing the presence or absence of the standard pattern in each section, it is possible to Even if there is a deviation in the supply angle, it can be absorbed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of an automatic wire bonding apparatus to which the position detection method according to the present invention is applied, FIG. 2 is a block diagram of an example of the position detection apparatus of FIG. 1, and FIG. Figure 4 is a diagram showing an example of the standard pattern, Figure 5 is a diagram showing the position of the standard pattern in Figure 4 in the pattern in Figure 3, and Figure 6 is a diagram showing the position of the standard pattern in Figure 4 during detection. 7 is a diagram showing the position of the standard pattern of FIG. 4 in the pattern of FIG. 6, and FIG. 8 is an example of the processing circuit 92 of FIG. 2. FIG. 9 is a configuration diagram of an embodiment of the area division circuit in FIG. 8, FIG. 10 is a configuration diagram of an embodiment of the processing circuit 35 in FIG. Figure 12 is a diagram showing an example of the standard pattern existing in each division of the pattern in Figure 7.
FIG. 3 is a block diagram of an embodiment of the starting circuit shown in FIG. 10. 6... Imaging device, 9... Position detection device, 32.35
...processing circuit. Figure 1 Figure 2 L + +
JFig. 3 Fig. 4 Fig. 5 Fig. 6 B Fig. 9 Fig. 1 O Fig. l・ Fig. 1 1 Fig. 1 2

Claims (1)

[Claims] 1. means for imaging a predetermined partial region of the object; and a means for imaging a predetermined partial region of the object, which is set on the object and arranged at multiple positions within a pattern of the entire region for the entire region larger than the partial region imaged by the imaging means. , means for storing in advance the respective positions of at least one type of standard pattern existing as the partial pattern, and determining the position of a plurality of partial patterns matching the standard pattern from the pattern signal belonging to the partial area output from the imaging means. A combination of a means for detecting a position and a standard pattern position having the same relative positional relationship as the relative positional relationship of the plurality of partial patterns detected in the partial area among the stored positions of the plurality of standard patterns. and means for detecting the position of the target object based on the selection result.