JPH03218506A - Integrated circuit - Google Patents
Integrated circuitInfo
- Publication number
- JPH03218506A JPH03218506A JP2237045A JP23704590A JPH03218506A JP H03218506 A JPH03218506 A JP H03218506A JP 2237045 A JP2237045 A JP 2237045A JP 23704590 A JP23704590 A JP 23704590A JP H03218506 A JPH03218506 A JP H03218506A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- mos transistor
- output
- conductivity type
- type mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 8
- 230000006866 deterioration Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
- G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
- G05F3/247—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the supply voltage
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
- H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野」
本発明は定電圧回路を含み、時計用集積回路（１ｎｔｅ
ｇｒａｔｅｄ Ｃ１ｒｃｕｉｔ：以下ＩＣという）など
低消費電力が要求されるＩＣに関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention includes a constant voltage circuit, and is applied to a watch integrated circuit (1nte
This invention relates to ICs that require low power consumption, such as rated C1rcuits (hereinafter referred to as ICs).
［従来の技術］
第６図は従来のＩＣの定電圧回路の一例を示す回路図で
ある。図示のように従来の定電圧回路は基準電圧発生回
路（２４）、差動増幅回路（２６）、モノチャネル出力
ドライバ（２８）及び負帰還増幅部（３０）から構成さ
れている。基準電圧発生回路（２４）はデブレッション
型ＰＭＯＳトランジスタ（５０）、エンハンスメント型
ＰＭＯＳトランジスタ（５２）及びエンハンスメント型
ＮＭＯＳトランジスタ（５４）， （５Ｂ）から構成
されている。また、差動増幅回路（２６）は、エンハン
スメント型ＰＭＯＳトランジスタ（５８）． （６０
）． （６２）及びエンハンスメント型ＮＭＯ Ｓト
ランジスタ（＄４）． （ａｌｌ）から構成されている
。[Prior Art] FIG. 6 is a circuit diagram showing an example of a conventional IC constant voltage circuit. As shown in the figure, the conventional constant voltage circuit includes a reference voltage generation circuit (24), a differential amplifier circuit (26), a monochannel output driver (28), and a negative feedback amplifier section (30). The reference voltage generation circuit (24) is composed of a depletion type PMOS transistor (50), an enhancement type PMOS transistor (52), and an enhancement type NMOS transistor (54), (5B). The differential amplifier circuit (26) also includes enhancement type PMOS transistors (58). (60
). (62) and enhancement type NMOS transistor ($4). (all).
モノチャネル出力ドライバ（２８）はエンハンスメント
型ＮＭＯＳトランジスタ（６８）から構成されている。The mono-channel output driver (28) consists of an enhancement type NMOS transistor (68).
負帰還増幅部（３０）は回路負荷（３２）に並列接続さ
れた抵抗（７０）， （７２）から構成されており、抵
抗（７０）と（７２）との接続点はＰＭＯＳトランジス
タ（６２）のゲートに接続されている。The negative feedback amplifier (30) is composed of resistors (70) and (72) connected in parallel to the circuit load (32), and the connection point between the resistors (70) and (72) is a PMOS transistor (62). connected to the gate.
基準電圧発生回路（２４）において、デプレッション型
ＰＭＯＳトランジスタ（５０）とエンハンスメント型Ｐ
ＭＯＳトランジスタ（５２）とのトランジスタサイズが
等しく、かつエンハンスメント型ＮＭＯＳトランジスタ
（５４）と（５６）とのトランジスタサイズが等しい場
合には、ＰＭＯＳトランジスタ（５２）とＰＭＯＳトラ
ンジスタ（５０）とのスレッショルド電圧の差電圧がＶ
ＤＤを基準とした一定電圧からなる基準電圧（２５）と
して出力される。この基準電圧（２５）は差動増幅回路
（２６）の非反転入力であるＰＭＯＳトランジスタ（６
０）のゲートに入力される。そして、モノチャネル出力
ドライバ（２８）のドレイン（２９）からの出力が分割
抵抗（７０）， （７２）を介して差動増幅回路（２６
）の反転入力であるＰＭＯＳトランジスタ（６２）のゲ
ートに負帰還入力されることにより、モノチャネル出力
ドライバ（２８）のドレインから定電圧が出力され、回
路負荷（３２）に供給されている。In the reference voltage generation circuit (24), a depletion type PMOS transistor (50) and an enhancement type PMOS transistor (50) are connected.
When the transistor size of the MOS transistor (52) is the same, and the transistor size of the enhancement type NMOS transistors (54) and (56) is the same, the threshold voltage of the PMOS transistor (52) and the PMOS transistor (50) is the same. The differential voltage is V
It is output as a reference voltage (25) consisting of a constant voltage with DD as a reference. This reference voltage (25) is applied to the PMOS transistor (6) which is the non-inverting input of the differential amplifier circuit (26).
0) is input to the gate. The output from the drain (29) of the monochannel output driver (28) is then passed through the dividing resistors (70) and (72) to the differential amplifier circuit (26).
), a constant voltage is output from the drain of the monochannel output driver (28) and supplied to the circuit load (32).
ところで、出力ドライバをモノチャネルで構成する理由
は、Ｐチャネル側の出力ドライバを省くことにより出力
ドライバ部の消費電流を減少させることにある。By the way, the reason for configuring the output driver as a monochannel is to reduce the current consumption of the output driver section by omitting the output driver on the P channel side.
［発明が解決しようとする課題コ
しかし、上述のような従来の定電圧回路ではＰチャネル
側の出力ドライバがないため、電源電圧が変動した場合
には定電圧出力が安定せずＩＣの誤動作の原因となった
り、特性の劣化を招いたりした。例えば、時計用ＩＣな
どのように電池を使用しブザー出力機能を有するＩＣの
場合には、ブザー鳴鐘時にはＩＣに供給される電源電圧
が小さくなってしまう。これは、電池の電流負荷が大き
くなり電池の内部インピーダンスによる電圧降下が大き
くなることに起因している。[Problems to be Solved by the Invention] However, since the conventional constant voltage circuit as described above does not have an output driver on the P-channel side, the constant voltage output becomes unstable when the power supply voltage fluctuates, leading to IC malfunction. or caused deterioration of characteristics. For example, in the case of an IC such as a watch IC that uses a battery and has a buzzer output function, the power supply voltage supplied to the IC decreases when the buzzer sounds. This is because the current load on the battery increases and the voltage drop due to the internal impedance of the battery increases.
第７図はこのようにＩＣに供給される電源電圧が周期的
に降下したときの動作を示すタイミングチャートである
。電源電圧ＶＤＤ−Ｖｓｓが降下すると、差動増幅回路
（２６）の出力Ｖ ａ （２７）は変動する。FIG. 7 is a timing chart showing the operation when the power supply voltage supplied to the IC drops periodically in this manner. When the power supply voltage VDD-Vss drops, the output V a (27) of the differential amplifier circuit (26) fluctuates.
この出力Ｖ ａ （２７）は図示のように回路自体の容
量（６Ｂ）や回路負荷（３２）の容量成分の影響により
遅延する。このためＮチャネル出力ドライバ（２８）の
ゲートーソース電圧ＶＧＳは一定にはならない。そして
、ゲートーソース電圧ｖＧＳの電圧は電源電圧ＶＤＤ−
Ｖｓｓが元の大きさに戻る瞬間に大きくなる。As shown in the figure, this output V a (27) is delayed due to the influence of the capacitance (6B) of the circuit itself and the capacitance component of the circuit load (32). Therefore, the gate-source voltage VGS of the N-channel output driver (28) is not constant. Then, the voltage of the gate-source voltage vGS is the power supply voltage VDD−
It increases at the moment Vss returns to its original size.
ゲートーソース電圧ｖＧＳの電圧が大きくなると、Ｎチ
ャネル出力ドライバ（２８）の駆動能力は大となり、そ
の出力はＶｓｓ側に引っ張られてしまう。電源電圧の変
動の周波数が低い場合にはＶｓｓ側に引っ張られた定電
圧出力もやがて一定電圧に収束する。しかし、電源電圧
の変動の周波数が高い場合には一定電圧に収束する前に
、再びｖＳＳ側に引っ張られてしまう。When the voltage of the gate-source voltage vGS increases, the driving ability of the N-channel output driver (28) increases, and its output is pulled toward the Vss side. When the frequency of fluctuations in the power supply voltage is low, the constant voltage output pulled toward the Vss side eventually converges to a constant voltage. However, if the frequency of fluctuations in the power supply voltage is high, the voltage will be pulled toward vSS again before it converges to a constant voltage.
第８図及び第９図は電源電圧の変動の周波数が高い場合
の定電圧出力を示すタイミングチャートであり、定電圧
出力が時間の経過と共にｖＳＳ側に引っ張られてしまい
、ある状態で飽和してそれ以上ｖＳＳ側に引っ張られず
、単に脈動する。Figures 8 and 9 are timing charts showing the constant voltage output when the frequency of fluctuations in the power supply voltage is high, and the constant voltage output is pulled toward vSS over time and becomes saturated in a certain state. It is no longer pulled towards the vSS side and simply pulsates.
従って、このような場合には平均的な定電圧出力が通常
時に比べて大きくなってしまう。定電圧出力を液晶表示
に用いる場合にはブザー鳴鐘時には、表示コントラスト
が強くなりすぎることによる表示の劣化を招くなど、従
来の定電圧回路では、重負荷時に出力電圧が安定しない
という問題点があった。Therefore, in such a case, the average constant voltage output becomes larger than in normal times. When using a constant voltage output for a liquid crystal display, when the buzzer sounds, the display contrast becomes too strong, leading to display deterioration.With conventional constant voltage circuits, the output voltage is unstable under heavy loads. there were.
本発明は、このよう問題点を解決するためになされたも
のであり、重負荷駆動時にも出力電圧が安定するように
した定電圧回路を有するＩＣを提供することを目的とす
る。The present invention has been made to solve these problems, and an object of the present invention is to provide an IC having a constant voltage circuit whose output voltage is stable even when driving with a heavy load.
［課題を解決するための手段］
本発明に係る集積回路は、基準電圧発生回路の出力信号
を基準信号として入力し、帰還増幅回路の出力を負帰還
信号として入力する差動増幅回路及び差動増幅回路の出
力により駆動されるモノチャネル出力ドライバを有する
定電圧回路と、この定電圧回路の出力に接続された回路
負荷と、この回路負荷に並列接続され、重負荷が所定の
周波数で駆動されるときに駆動されるＭＯＳトランジス
タとを有する。そして、ＭＯＳトランジスタを駆動制御
する手段として、重負荷が所定の周波数で駆動されると
きにＣＰＵから制御信号がセットされるラッチ回路を有
する。[Means for Solving the Problems] An integrated circuit according to the present invention includes a differential amplifier circuit that inputs an output signal of a reference voltage generation circuit as a reference signal, and inputs an output of a feedback amplifier circuit as a negative feedback signal, and a differential A constant voltage circuit having a mono-channel output driver driven by the output of an amplifier circuit, a circuit load connected to the output of this constant voltage circuit, and a heavy load connected in parallel to this circuit load and driven at a predetermined frequency. It has a MOS transistor that is driven when the As means for driving and controlling the MOS transistors, a latch circuit is provided to which a control signal is set by the CPU when a heavy load is driven at a predetermined frequency.
また、定電圧回路は次のａ）〜ｆ）の各ＭＯＳトランジ
スタを有する。Further, the constant voltage circuit has the following MOS transistors a) to f).
ａ）ソースが第１の電源に接続され、ゲートには第１の
電源を基準とした一定電圧が供給される第１の第１導電
型ＭＯＳトランジスタ。a) A first first conductivity type MOS transistor whose source is connected to a first power source and whose gate is supplied with a constant voltage based on the first power source.
ｂ）ソースが前記第１の第１導電型ＭＯＳトランジスタ
のドレインに接続され、ゲートには第１の電源を基準と
した一定電圧が基準電圧として供給される第２の第１導
＠型ＭＯＳトランジスタ。b) a second first conductivity type MOS transistor whose source is connected to the drain of the first first conductivity type MOS transistor, and whose gate is supplied with a constant voltage based on the first power supply as a reference voltage; .
Ｃ）ソースが前記第１の第１導電型ＭＯＳトランジスタ
のドレインに接続される第３の第１導電型ＭＯＳトラン
ジスタ。C) a third MOS transistor of the first conductivity type, the source of which is connected to the drain of the first MOS transistor of the first conductivity type;
ｄ）ソースが第２の電源に接続され、ドレインが前記第
２の第１導電型ＭＯＳトランジスタに接続され、ゲート
には前記第３の第１導電型ＭＯＳトランジスタのドレイ
ンと同電位の電圧が供給されるｓ１の第２導電型ＭＯＳ
トランジスタ。d) A source is connected to a second power supply, a drain is connected to the second first conductivity type MOS transistor, and a voltage having the same potential as the drain of the third first conductivity type MOS transistor is supplied to the gate. The second conductivity type MOS of s1
transistor.
ｅ）ソースが第２の電源に接続され、ドレインが前記第
３の第１導電型ＭＯＳトランジスタのドレインに接続さ
れ、ゲートには前記第３の第１導電型ＭＯＳトランジス
タのドレインと同電位の電圧が供給される第２の第２導
電型ＭＯＳトランジスタ。e) The source is connected to a second power supply, the drain is connected to the drain of the third first conductivity type MOS transistor, and the gate is connected to a voltage having the same potential as the drain of the third first conductivity type MOS transistor. a second second conductivity type MOS transistor to which is supplied;
ｆ）ソースが第２の電源に接続され、ゲートには前記第
２の第１導電型ＭＯＳトランジスタのドレインと同電位
の電圧が供給され、ドレインには、前記第３の第１導電
型ＭＯＳトランジスタのゲートと、回路負荷が接続され
ている第３の第２導電型ＭＯＳトランジスタ。f) The source is connected to a second power supply, the gate is supplied with a voltage having the same potential as the drain of the second first conductivity type MOS transistor, and the drain is connected to the third first conductivity type MOS transistor. a third second conductivity type MOS transistor, the gate of which is connected to the circuit load;
また、本発明に係る集積回路は、回路負荷に並列接続さ
れた前記ＭＯＳトランジスタは、ソースが第１の電源に
接続され、ドレインが前記第３の第２導電型ＭＯＳトラ
ンジスタのドレインと電気的に接続されている第４の第
１導電型ＭＯＳトランジスタから構成されている。また
、第１の電源及び第２の電源のうち少なくとも一方をＯ
Ｎ／ＯＦＦするスイッチ手段を有する。Further, in the integrated circuit according to the present invention, the MOS transistor connected in parallel to the circuit load has a source connected to a first power supply and a drain electrically connected to the drain of the third second conductivity type MOS transistor. It is composed of a fourth MOS transistor of the first conductivity type connected to each other. Further, at least one of the first power source and the second power source is turned off.
It has a switch means for turning on and off.
［作 用］
本発明においては、回路負荷に並列接続されたＭＯＳト
ランジスタが重負荷駆動時にオンするので、定電圧回路
の容量及び回路負荷内の容量の電荷が急速に放電されて
、帰還増幅器の出力が電圧変動に対応したものとなり、
出力段のモノチャネル出力ドライバは適切に制御され、
電源変動があってもその出力変動が少なくなる。[Function] In the present invention, since the MOS transistor connected in parallel to the circuit load is turned on when driving a heavy load, the capacitance of the constant voltage circuit and the charge of the capacitance in the circuit load are rapidly discharged, and the feedback amplifier is The output corresponds to voltage fluctuations,
The mono-channel output driver in the output stage is well controlled and
Even if there are power fluctuations, the output fluctuations will be reduced.
〔実施例コ 第１図は本発明の一実施例に係るＩＣの回路図である。[Example FIG. 1 is a circuit diagram of an IC according to an embodiment of the present invention.
Ｃ Ｐ Ｕ （１０）は重負荷を所定の周波数で駆動す
るときに、データパス（ｌ２）を介してブザーレジスタ
（１４）及び重負荷制御レジスタ（ｌ６）にそれぞれ制
御信号をセットする。ブザーレジスタ（１４）はアンド
ゲート（ｌ８）に対してゲート信号を送る。アンドゲー
ト（ｌ８）がゲート信号により開になると、ブザークロ
ック信号（ｌ７）がブザードライバ（２０）に送り出さ
れ、そこで増幅される。ブザードライバ（２０）の出力
はブザー出力端子（３Ｂ）を介してトランジスタ（４０
）を駆動する。圧電ブザー（４２）及び昇圧コイル（４
４）からなるブザー回路（４６）はトランジスタ（４０
）の駆動に伴って鳴鐘する。When driving a heavy load at a predetermined frequency, the CPU (10) sets control signals to the buzzer register (14) and the heavy load control register (16) through the data path (12), respectively. The buzzer register (14) sends a gate signal to the AND gate (l8). When the AND gate (l8) is opened by the gate signal, the buzzer clock signal (l7) is sent to the buzzer driver (20), where it is amplified. The output of the buzzer driver (20) is connected to the transistor (40) via the buzzer output terminal (3B).
) to drive. Piezoelectric buzzer (42) and boost coil (4
A buzzer circuit (46) consisting of a transistor (40
) is activated.
定電圧回路（２２）は、基準電圧発生回路（２４）、差
動増幅回路（２Ｂ）、モノチャネル出力ドライバ（２８
）及び負帰還増幅部（３０）から構成されている。ＶＤ
Ｄ端子と定電圧回路（２２）の出力（２９）との間に回
路負荷（３２）及びＰＭＯＳ出力ドライバ（３４）が接
続されている。定電圧回路（２２）の出力（２９）は定
電圧出力端子（３Ｂ）に接続されている。この定電圧出
力端子（３８）には例えば液晶表示回路（図示せず）等
が接続される。The constant voltage circuit (22) includes a reference voltage generation circuit (24), a differential amplifier circuit (2B), and a monochannel output driver (28).
) and a negative feedback amplifier section (30). V.D.
A circuit load (32) and a PMOS output driver (34) are connected between the D terminal and the output (29) of the constant voltage circuit (22). An output (29) of the constant voltage circuit (22) is connected to a constant voltage output terminal (3B). For example, a liquid crystal display circuit (not shown) is connected to this constant voltage output terminal (38).
第２図は定電圧回路（２２）の詳細を示した回路図であ
り、この回路自体は従来の第６図に示したものと同一で
ある。この実施例においては回路負荷（３２）に並列に
ＰＭＯＳ出力ドライバ（３４）が接続されており、この
ＰＭＯＳ出力ドライバ（３４）は重負荷制御レジスタ（
１Ｂ）の信号に基づいて駆動される。FIG. 2 is a circuit diagram showing details of the constant voltage circuit (22), and this circuit itself is the same as the conventional one shown in FIG. 6. In this embodiment, a PMOS output driver (34) is connected in parallel to the circuit load (32), and this PMOS output driver (34) is connected to the heavy load control register (
1B).
つまり、ＩＣがブザー（４Ｂ）のように重負荷を駆動す
るときにはＣ Ｐ Ｕ （１０）が重負荷制御レジスタ
（１Ｂ）に“１ ′をセットし、それをＰＭＯＳ出力ド
ライバ（３４）のゲートに印加することによりオン駆動
させる。In other words, when the IC drives a heavy load such as a buzzer (4B), the CPU (10) sets the heavy load control register (1B) to "1'" and sends it to the gate of the PMOS output driver (34). It is turned on by applying the voltage.
従って、第７図に示した場合と同様に、電源電圧Ｖ Ｄ
Ｄ− Ｖ ＳＳが降下した状態から元の値に戻ったとき
には、モノチャネル出力ドライバ（２８）のゲート電圧
が大となりその駆動能力が大きくなって出力電圧がｖＳ
Ｓ側に引っ張られる。しかし、ＰＭＯＳ出力ドライバ（
３４）がオンしているので、定電圧回路の容量（６８）
の電荷や回路負荷（３２）の容量成分の電荷の放電回路
が生成されて急速に放電されるため、モノチャネル出力
ドライバ（２８）のゲート電圧がその出力電圧に対応し
た値に戻る。従って、電源電圧が周期的に変動しても、
一旦は出力電圧がｖＳＳ側に引っ張られるが、上述のよ
うにＰＭＯＳ出力ドライバ（３４）がオンしているので
ＶＤＤ側に引き戻され、定格出力を基準値として単に脈
動するだけで、定電圧出力の絶対値が累積的に大きくな
るということはなく、安定した出力が得られる。Therefore, similarly to the case shown in FIG. 7, the power supply voltage V D
When D-VSS returns to its original value from a dropped state, the gate voltage of the monochannel output driver (28) increases, its driving capability increases, and the output voltage increases to vS.
It is pulled to the S side. However, the PMOS output driver (
Since 34) is on, the capacity of the constant voltage circuit (68)
A discharge circuit is generated and rapidly discharges the charge of the capacitive component of the circuit load (32), so that the gate voltage of the monochannel output driver (28) returns to a value corresponding to its output voltage. Therefore, even if the power supply voltage fluctuates periodically,
Once the output voltage is pulled to the vSS side, as mentioned above, the PMOS output driver (34) is on, so it is pulled back to the VDD side, and it simply pulsates with the rated output as the reference value, resulting in a constant voltage output. The absolute value does not increase cumulatively, and a stable output can be obtained.
第３図及び第４図は重負荷時の動作を示すタイミングチ
ャートであり、上述のように、定電圧出力の絶対値が累
積的に大きくなっていないことが分かる。FIGS. 3 and 4 are timing charts showing the operation under heavy load, and it can be seen that the absolute value of the constant voltage output does not increase cumulatively as described above.
第５図は本発明の他の実施例に係るＩＣの回路図である
。この実施例においては、ＩＣの試験或いはより低消費
電力化を実現するために、第２図の実施例に対して電源
スイッチ（８０）． （８２）を追加している。FIG. 5 is a circuit diagram of an IC according to another embodiment of the present invention. In this embodiment, in order to test the IC or realize lower power consumption, the power switch (80). (82) has been added.
なお、ＰＭＯＳ出力ドライバ（３４）は重負荷が駆動さ
れている間ＯＮＬているので、ＩＣの消費電流は増大す
ることになるが、電源電圧が変動するような重負荷の駆
動は、ブザーを鳴鐘したりランプやＬＥＤを点灯したり
する場合だけであり、ＰＭＯＳドライバ（３４）をＯＮ
することによって増大する消費電流は、システム全体の
消費電流を考慮するとほとんど無視し得る程度のもので
ある。Note that the PMOS output driver (34) remains ON while a heavy load is being driven, so the current consumption of the IC will increase. This is only when you want to ring a bell or turn on a lamp or LED, and turn on the PMOS driver (34).
The increased current consumption due to this is almost negligible when considering the current consumption of the entire system.
また、ＰＭＯＳ出力ドライバ（３４）を制御するための
回路は上述の重負荷制御レジスタ（ｌ６）だけでなく、
制御信号をラッチできるものであれば他の回路例えばフ
リップフロップ回路でもよい。Moreover, the circuit for controlling the PMOS output driver (34) is not only the above-mentioned heavy load control register (l6), but also the circuit for controlling the PMOS output driver (34).
Any other circuit, such as a flip-flop circuit, may be used as long as it can latch the control signal.
また、上記の実施例ではＶＤＤを基準として定電圧を出
力する定電圧回路の例を説明したが、ｖＳＳを基準とし
た定電圧回路にも同様に本発明は適用できることはいう
までもない。Further, in the above embodiment, an example of a constant voltage circuit that outputs a constant voltage with VDD as a reference has been described, but it goes without saying that the present invention can be similarly applied to a constant voltage circuit that uses vSS as a reference.
この発明のＩＣは時計用マイクロコンピュータに特に有
効である。The IC of the present invention is particularly effective for microcomputers for watches.
［発明の効果］
以上のように本発明によれば、定電圧回路の出力に接続
された回路負荷に並列にＰＭＯＳトランジスタを接続し
て重負荷駆動時に駆動するようにしたので、回路負荷の
容量成分の電荷を急速に放電させることができ、これに
より電源変動に対する帰還制御が適切になされるので、
電源電圧が不安定な状態であっても、安価で低消費電力
でかつ安定した電圧レベルを出力できる。[Effects of the Invention] As described above, according to the present invention, the PMOS transistor is connected in parallel to the circuit load connected to the output of the constant voltage circuit and is driven when driving a heavy load, so that the capacitance of the circuit load is reduced. The charges of the components can be rapidly discharged, which allows for appropriate feedback control against power supply fluctuations.
Even if the power supply voltage is unstable, it is possible to output a stable voltage level at low cost and with low power consumption.
第１図は本発明の一実施例に係る．Ｉ Ｃの回路図、第
２図は第１図の定電圧回路の回路図、第３図及び第４図
は第２図の回路の動作を示すタイミングチャート、第５
図はこの発明の他の実施例に係る定電圧回路の回路図で
ある。
第６図は従来の定電圧回路の回路図、第７図、第８図及
び第９図は第６図の回路の動作を示すタイミングチャー
トである。
図において、（１６）は重負荷制御レジスタ、（２２）
は定電圧回路、（２８）はモノチャネル出力ドライノく
、（３２）は回路負荷、（３４）はＰＭＯＳ出力ドライ
ノくである。FIG. 1 relates to an embodiment of the present invention. Figure 2 is a circuit diagram of the constant voltage circuit in Figure 1, Figures 3 and 4 are timing charts showing the operation of the circuit in Figure 2, and Figure 5 is a circuit diagram of the IC.
The figure is a circuit diagram of a constant voltage circuit according to another embodiment of the present invention. FIG. 6 is a circuit diagram of a conventional constant voltage circuit, and FIGS. 7, 8, and 9 are timing charts showing the operation of the circuit of FIG. 6. In the figure, (16) is a heavy load control register, (22)
is a constant voltage circuit, (28) is a mono-channel output driver, (32) is a circuit load, and (34) is a PMOS output driver.
Claims (5)
力し、帰還増幅回路の出力を負帰還信号として入力する
差動増幅回路及び差動増幅回路の出力により駆動される
モノチャネル出力ドライバを有する定電圧回路と、 この定電圧回路の出力に接続された回路負荷と、この回
路負荷に並列接続され、重負荷が所定の周波数で駆動さ
れるときに駆動されるＭＯＳトランジスタと を有する集積回路。(1) It has a differential amplifier circuit that inputs the output signal of the reference voltage generation circuit as the reference signal and inputs the output of the feedback amplifier circuit as the negative feedback signal, and a monochannel output driver driven by the output of the differential amplifier circuit. An integrated circuit comprising: a constant voltage circuit; a circuit load connected to the output of the constant voltage circuit; and a MOS transistor connected in parallel to the circuit load and driven when a heavy load is driven at a predetermined frequency.
から制御信号がセットされ、前記ＭＯＳトランジスタを
駆動するラッチ回路を有する請求項１記載の集積回路。(2) When a heavy load is driven at a predetermined frequency, the CPU
2. The integrated circuit according to claim 1, further comprising a latch circuit to which a control signal is set from the latch circuit for driving said MOS transistor.
電源を基準とした一定電圧が供給される第１の第１導電
型ＭＯＳトランジスタと、 ｂ）ソースが前記第１の第１導電型ＭＯＳトランジスタ
のドレインに接続され、ゲートには第１の電源を基準と
した一定電圧が基準電圧として供給される第２の第１導
電型ＭＯＳトランジスタと、ｃ）ソースが前記第１の第
１導電型ＭＯＳトランジスタのドレインに接続される第
３の第１導電型ＭＯＳトランジスタと、 ｄ）ソースが第２の電源に接続され、ドレインが前記第
２の第１導電型ＭＯＳトランジスタに接続され、ゲート
には前記第３の第１導電型ＭＯＳトランジスタのドレイ
ンと同電位の電圧が供給される第１の第２導電型ＭＯＳ
トランジスタと、ｅ）ソースが第２の電源に接続され、
ドレインが前記第３の第１導電型ＭＯＳトランジスタの
ドレインに接続され、ゲートには前記第３の第１導電型
ＭＯＳトランジスタのドレインと同電位の電圧が供給さ
れる第２の第２導電型ＭＯＳトランジスタと、 ｆ）ソースが第２の電源に接続され、ゲートには前記第
２の第１導電型ＭＯＳトランジスタのドレインと同電位
の電圧が供給され、ドレインには、前記第３の第１導電
型ＭＯＳトランジスタのゲートと、前記回路負荷が接続
されている第３の第２導電型ＭＯＳトランジスタと を含む請求項１記載の集積回路。(3) The constant voltage circuit includes: a) a first first conductivity type MOS transistor whose source is connected to a first power supply and whose gate is supplied with a constant voltage based on the first power supply; b) ) a second first conductivity type MOS transistor whose source is connected to the drain of the first first conductivity type MOS transistor, and whose gate is supplied with a constant voltage based on the first power supply as a reference voltage; c) a third first conductivity type MOS transistor whose source is connected to the drain of the first first conductivity type MOS transistor; d) a source connected to a second power supply and a drain connected to the second first conductivity type MOS transistor; a first second conductivity type MOS connected to the first conductivity type MOS transistor and having a gate supplied with a voltage having the same potential as the drain of the third first conductivity type MOS transistor;
a transistor; e) a source connected to a second power source;
a second second conductivity type MOS whose drain is connected to the drain of the third first conductivity type MOS transistor, and whose gate is supplied with a voltage having the same potential as the drain of the third first conductivity type MOS transistor; a transistor; 2. The integrated circuit according to claim 1, comprising a gate of a type MOS transistor and a third second conductivity type MOS transistor to which the circuit load is connected.
タは、ソースが第１の電源に接続され、ドレインが前記
第３の第２導電型ＭＯＳトランジスタのドレインと電気
的に接続されている第４の第１導電型ＭＯＳトランジス
タから構成されている請求項３記載の集積回路。(4) The MOS transistor connected in parallel to the circuit load has a fourth source connected to the first power source and a drain electrically connected to the drain of the third second conductivity type MOS transistor. 4. The integrated circuit according to claim 3, comprising a first conductivity type MOS transistor.
をＯＮ／ＯＦＦするスイッチ手段を有する請求項４記載
の集積回路。(5) The integrated circuit according to claim 4, further comprising a switch means for turning on/off at least one of the first power source and the second power source.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900016092A KR0135967B1 (en) | 1989-10-20 | 1990-10-11 | Integrated circuit |
| US07/595,967 US5235520A (en) | 1989-10-20 | 1990-10-11 | Integrated circuit having a function for generating a constant voltage |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1-273068 | 1989-10-20 | ||
| JP27306889 | 1989-10-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03218506A true JPH03218506A (en) | 1991-09-26 |
| JP3131988B2 JP3131988B2 (en) | 2001-02-05 |
Family
ID=17522699
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP02237045A Expired - Lifetime JP3131988B2 (en) | 1989-10-20 | 1990-09-10 | Integrated circuit |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP3131988B2 (en) |
| KR (1) | KR0135967B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004356159A (en) * | 2003-05-27 | 2004-12-16 | Ricoh Co Ltd | Semiconductor device and its manufacturing method |
-
1990
- 1990-09-10 JP JP02237045A patent/JP3131988B2/en not_active Expired - Lifetime
- 1990-10-11 KR KR1019900016092A patent/KR0135967B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004356159A (en) * | 2003-05-27 | 2004-12-16 | Ricoh Co Ltd | Semiconductor device and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| KR0135967B1 (en) | 1998-05-15 |
| KR910008531A (en) | 1991-05-31 |
| JP3131988B2 (en) | 2001-02-05 |
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