JPH03218031A - Semiconductor integrated circuit device and preform bonding material used in the same - Google Patents

Abstract

PURPOSE:To make the thermal resistance of a die bonding part low, prevent the deformation of a semiconductor chip, and improve the reliability, by interposing a high thermal conductivity plate composed of high thermal conductivity material in a bonding layer composed of bonding material. CONSTITUTION:A metallized layer 5 is formed on the rear of a semiconductor chip 1 for bonding to the brazing material (bonding material) 4. A metallized layer 6 of three-layered structure is formed on the main surface of a die bonding substrate 2 in the same manner as the chip 1. A high thermal conductivity plate 3 is formed by using high thermal conductivity material having a thermal expansion coefficient nearly equal to the intermediate value between the chip 1 and the substrate 2. Fluid grooves 3a having semicircular sections are formed on both surfaces of the plate 3. The brazing material 4 easily flows in the grooves 3 toward the outer periphery, and can be formed as thin as possible. Thereby the thermal conductivity of the bonding layer can be improved, the heat dissipating efficiency can be enhanced, the deterioration of element characteristics and the decrease of reliability of the bonding layer can be prevented, the thermal conductivity is increased, the deformation of the chip is prevented, and handling properties and reliability can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a manufacturing technology for semiconductor integrated circuit devices, and particularly to a die bonding technology for semiconductor integrated circuit devices.
The present invention relates to a technology that is effective when applied to a semiconductor integrated circuit device and a preform bonding material used therein, which enables a die bonding part to have a high thermal conductivity and a highly precise structure, and which can improve heat dissipation efficiency.

[Prior Art] In recent years, as semiconductor integrated circuit devices have become denser and more highly integrated, power consumption density has increased sharply, and heat problems in electronic computers and the like have become more severe. Under these circumstances, cooling technology from the back side of semiconductor chips is becoming important, and reducing thermal resistance in the thermal path in die bonding technology has become an important issue. Furthermore, the problem of chip deformation when the back surface of a semiconductor chip is fixed has become more apparent due to improvements in dimensional accuracy.

Conventional die bonding technology includes, for example, LSI Design and Manufacturing Technology JP118-P119 published by Denki Shoin Co., Ltd. in 1987, or rLSI Handbook J published by the Institute of Electronics and Communication Engineers, November 30, 1987.
As described in documents such as P406 to P408, the eutectic bonding method, the solder bonding method, and the resin bonding method are used as bonding methods for bonding a semiconductor chip to a die bonding substrate.

For example, the eutectic synthesis method is widely used because the melting point of Au-Si eutectic alloy is relatively low at 370°C. This eutectic alloy method uses 400°C in an N2 or N2+H2 atmosphere to prevent oxidation during die bonding.
This is a method of bonding by pressing the back surface of a semiconductor chip onto an Au-plated Gui pad while heating it to around 0.degree. C. to cause an Au-Si eutectic reaction. At this time, in order to facilitate the eutectic reaction, a method of applying vibration to the bonded portion is used. In addition, in order to make this alloy layer even better, Au is vapor-deposited on the back surface of the semiconductor chip, or A
A method of sandwiching U foil is used.

[Problems to be Solved by the Invention] However, in the above-mentioned prior art, consideration has not been given to increasing the thermal conductivity of the die bonding portion that fixes the back surface of the semiconductor chip and the die bonding substrate, and to preventing deformation of the semiconductor chip. However, there is a disadvantage that the die bonding part has high thermal resistance and thermal stress occurs.

Therefore, in the conventional die bonding technology, there is a problem in that reliability of the die bonding portion in the semiconductor integrated circuit device and the micro-connection portion on the element surface cannot be obtained.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor integrated circuit device and a semiconductor integrated circuit device, which can reduce thermal resistance by increasing thermal conductivity of a die bonding part, and can prevent deformation of semiconductor chips and improve reliability by alleviating thermal stress. An object of the present invention is to provide a preform bonding material used therefor.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.

That is, the semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device in which a semiconductor chip is mounted on a die bonding substrate via a bonding material, and the bonding layer made of the bonding material has a plate shape made of a highly thermally conductive material. A high thermal conductivity plate is interposed.

Further, the high thermal conductivity plate has a thermal expansion coefficient between that of the semiconductor chip and that of the die bonding substrate.

Further, the high heat conduction plate has grooves formed on both sides of the high heat conduction plate, or a plurality of through holes extending through both sides.

Further, in the preform bonding material used in the semiconductor integrated circuit device of the present invention, the high thermal conductivity plate is interposed in a bonding layer between the semiconductor chip and the die bonding substrate.

[Function] According to the semiconductor integrated circuit device described above, high thermal conductivity can be achieved by interposing a plate-like high thermal conductive plate made of a high thermal conductive material in the bonding layer between the semiconductor chip and the die bonding substrate. A bonding layer is formed to improve the heat dissipation efficiency of the semiconductor integrated circuit device.

In addition, by making the high thermal conductivity plate have a thermal expansion coefficient between that of the semiconductor chip and that of the die bonding substrate, thermal stress caused by the difference in thermal expansion coefficient between the semiconductor chip and the die bonding substrate can be avoided. can be alleviated.

Furthermore, by forming grooves on both sides of the high thermal conductivity plate or a plurality of through holes penetrating both sides, the bonding material can flow to the outer periphery through the grooves or flow out into the through holes, forming a bonding layer. Since it can be made as thin as possible, it is possible to further increase the thermal conductivity of the die bonding layer.In addition, the preform bonding material used in the semiconductor integrated circuit device described above has a high thermal conductivity plate that connects the semiconductor chip and the die bonding substrate. By being formed between layers, the die bonding process can be easily performed.

[Embodiment 1] Figure 1 is a sectional view showing the main parts of a semiconductor integrated circuit device which is an embodiment of the present invention, and Figures 2 (a), (b) and (C).
3 is a perspective view showing a high thermal conductivity plate used in the semiconductor integrated circuit device of this embodiment, and FIG. 3 is a sectional view showing a preform bonding material most suitable for the semiconductor integrated circuit device of this embodiment.

First, the configuration of the semiconductor integrated circuit device of this embodiment will be explained with reference to FIG.

The semiconductor integrated circuit device of this embodiment is, for example, a semiconductor integrated circuit device in which a semiconductor chip 1 is mounted on a die bonding substrate 2, and the back surface of the semiconductor chip 1 is a brazing material (bonding material) 4 with a high thermal conductivity plate 3 interposed therebetween. is melted and fixed onto the main surface of the die bonding substrate 2.

A metallized layer 5 is formed on the back surface of the semiconductor chip 1 so that it can be joined to a brazing material 4. In addition, the metallized layer 5
For example, from the bottom layer, an adhesive layer such as Cr, Ti, W, etc., N
A composite film with a three-layer structure is formed by combining barrier layers such as i, Pt, Pd, Cu, and Mo, and antioxidation layers such as Au.

The die bonding substrate 2, like the semiconductor chip 1,
A metallized layer 6 having a three-layer structure is formed on its main surface.

The high thermal conductivity plate 3 is made of a high thermal conductivity material having a coefficient of thermal expansion near the middle between the semiconductor chip 1 and the die bonding substrate 2. For example, semiconductor chip 1
is Si (silicon), and die bonding substrate 2 is Aj!
203 (alumina), the respective thermal expansion coefficients are 4.2X 10-'+jeg-',
6. 7 X I Q-'deg-', so 5. I X 1 0-'deg-'
Mo (molybdenum) or the like is used, which has a coefficient of thermal expansion of . Alternatively, the semiconductor chip 1 may be made of GaAs (6.5”
1 0-'deg-'), die bonding substrate 2
is made of alumina (6.7
u-W composite material (6.5 x 1 0-'deg-'
) etc. are irritating.

Further, as shown in FIGS. 2(a) to 2(C), the high thermal conductivity plate 3 has flow grooves 3a each having a semicircular cross section formed on both sides thereof. The flow groove 3a allows the brazing filler metal 4 to easily flow in the outer circumferential direction, so that the brazing filler metal 4 can be made as thin as possible.

For example, in FIG. 2(a), there are stripes on both sides of the high thermal conductivity plate 30, and in FIG. Flow grooves 3a are formed, and the direction and position of the flow grooves 3a are shifted from each other on each surface, so that the strength of the high thermal conductivity plate 3 itself is maintained.

The brazing filler metal 4 is, for example, Pb-Sn, Au-Sn, Pb-
Ag-based solder is used, and the brazing material 4 as shown in Fig. 3 is used.
The preform brazing material 7 has a high thermal conductivity plate 3 interposed therebetween. For example, if the brazing filler metal 4 is Pb-lQ%S
In the case of the preform brazing filler metal 7 of n, the die bonding layer 8 is the brazing filler metal 4 alone, and the thermal conductivity = Q. Q 5 2c
al/cm - sec - deg), M
With the intervention of the high thermal conductivity plate 3 due to O, the Cu-W
Composite materials can have approximately eight times the thermal conductivity.

Next, the operation of this embodiment will be explained.

In the semiconductor integrated circuit device of this embodiment configured as described above, the high thermal conductivity plate 3 is interposed in the preform brazing material 7, thereby increasing the thermal conductivity of the die bonding layer 8 by the brazing material 4. be able to.

In this case, by forming the flow grooves 3a on both sides of the high thermal conductivity plate 3, the brazing filler metal 4 can be made as thin as possible, so that the die bonding layer 8 can be made to have a higher thermal conductivity.

Further, by using the high thermal conductivity plate 3, thermal stress caused by the difference in thermal expansion coefficient between the semiconductor chip 1 and the die bonding substrate 2 can be alleviated.

Therefore, according to the semiconductor integrated circuit device of this embodiment, the heat dissipation of the semiconductor chip 1 is improved, and it is possible to prevent deterioration of element characteristics and reliability of the die bonding layer 8 due to thermal stress.

Further, by using the preform brazing material 7 as shown in FIG. 3 in the semiconductor integrated circuit device of this embodiment, the die bonding process of the semiconductor chip 1 is facilitated, and in particular, the highly thermally conductive plate 3 is made into an ultra-thin film. It is possible to improve handling performance when

[Embodiment 2] FIG. 4 is a sectional view showing a main part of a semiconductor integrated circuit device according to another embodiment of the present invention.

The semiconductor integrated circuit device of this embodiment is a semiconductor integrated circuit device in which a semiconductor chip 1 is mounted on a die bonding substrate 2 as shown in FIG. Die bonding substrate 2 by silicon rubber (bonding material) 9 with high thermal conductivity plate 3 interposed
It is a point fixed on the main surface of.

That is, in the bonding using the silicone rubber 9 of this embodiment, the die bonding substrate 2 is made of Cu (1
7. OXIQ-'deg-'), etc., and is applied when the semiconductor chip 1 of S1, GaAs, etc. is die-bonded.

In addition, the high thermal conductivity plate 3 in this case is Cu-W (8.5
-') , Cu-Mo (8.O X 1 0-@d
eg -'), Af-S i (13.5X1
0-'deg-'), Ni (12.8XIO
-'deg -') , Fe (12.OX1 0
-'deg-'), Mo(5.IX1hi1deg-1
) is used, and similarly to the first embodiment, flow grooves 3a are formed on both sides thereof.

Furthermore, in order to increase the thermal conductivity of the silicone rubber 9 itself, Ag. Contains various fillers such as diamond powder.

Therefore, according to the semiconductor integrated circuit mounting of this embodiment, especially when the difference in thermal expansion coefficient between the semiconductor chip 1 and the die bonding substrate 2 is large, the die bonding layer 8 can be made to have high thermal conductivity as in the first embodiment. At the same time, it is possible to reduce the influence of thermal stress caused by the difference in thermal expansion coefficient between the semiconductor chip 1 and the die bonding substrate 2.

[Embodiment 3] Fig. 5 is a sectional view showing the main parts of a semiconductor integrated circuit device according to another embodiment of the present invention, and Fig. 6 is a diagram showing a high thermal conductivity plate used in the semiconductor integrated circuit device of this embodiment. FIG.

The semiconductor integrated circuit device of this embodiment is a semiconductor integrated circuit device in which a semiconductor chip 1 is mounted on a die bonding substrate 2 as shown in FIG. The point is that a plurality of through holes 3b are formed.

That is, as shown in FIG. 6, the high thermal conductivity plate 3 of this embodiment has a plurality of cylindrical through holes 3b formed on both sides thereof, and the brazing material 4 or silicone rubber 9 is press-welded to provide an escape area. When lost, these amounts are adjusted by flowing out into the through hole 3b, and the structure is such that the die bonding layer 8 can be made as thin as possible in order to achieve high thermal conductivity.

Therefore, according to the semiconductor integrated circuit device of this embodiment, the brazing filler metal 4 or the silicone rubber 9 is not flowed toward the outer periphery as in the first and second embodiments, but flows into the through holes 3b of the high thermal conductivity plate 3. By doing so, the brazing material 4 or the silicone rubber 9 can be made as thin as possible within the size range of the high thermal conductivity plate 3. This results in
As in Examples 1 and 2, the die bonding layer 8 can be made to have high thermal conductivity, and the heat dissipation of the semiconductor chip 1 can be improved, while the difference in thermal expansion coefficient between the semiconductor chip 1 and the die bonding substrate 2 can be improved. It is possible to reduce the effects of heat stress caused by

As above, the invention made by the present inventor has been specifically explained based on Examples 1 to 3. However, the present invention is not limited to the above-mentioned Examples, and can be modified in various ways without departing from the gist thereof. It goes without saying that there is.

For example, in the semiconductor integrated circuit devices of Examples 1 and 2, the flow grooves 3a with semicircular cross sections are formed on both sides of the high thermal conductivity plate 3 in the arrangement shown in FIGS. 2(a) to 2(C). Although described above, the present invention is not limited to the above-mentioned embodiments. For example, the shape of the flow groove 3a can be applied to a semi-elliptical or polygonal cross section, and the arrangement of the flow groove 3a can also be applied. Various other deformations such as a lattice shape are also possible.

Further, the high thermal conductivity plate 3 in Example 3 is not limited to the case where the cylindrical through hole 3b is formed,
For example, the present invention can also be applied to a high thermal conductivity plate 3 in which a rectangular cylinder-shaped through hole 3b such as a square prism is formed.

[Effects of the Invention] Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.

(1). In a semiconductor integrated circuit device in which a semiconductor chip is mounted on a die bonding substrate via a bonding material, a plate-like high thermal conductivity plate made of a highly thermally conductive material is interposed in the bonding layer made of the bonding material. Since high thermal conductivity is possible, the heat dissipation efficiency of the semiconductor integrated circuit device can be improved.

(2). Since the high thermal conductivity plate has a thermal expansion coefficient between that of the semiconductor chip and that of the die bonding substrate, it can reduce thermal stress caused by the difference in thermal expansion coefficient between the semiconductor chip and the die bonding substrate. Since thermal stress can be relaxed, it is possible to prevent deterioration of device characteristics and decrease in reliability of the bonding layer due to thermal stress.

(3). By forming grooves or multiple through holes on both sides of the high heat conductive plate,
Since the bonding layer can be made as thin as possible by flowing the bonding material through the groove to the outer periphery or flowing into the through hole, it is possible to further increase the thermal conductivity of the semiconductor integrated circuit device.

(4). In the preform bonding material used for semiconductor integrated circuit devices, a high thermal conductivity plate is formed interposed in the bonding layer between the semiconductor chip and the die bonding substrate, thereby facilitating the die bonding process and, in particular, It is possible to improve handling properties when the high thermal conductivity plate is made into an ultra-thin film.

[5). According to (1) to (4) above, it is possible to obtain a semiconductor integrated circuit device and a preform bonding material used therein, which can prevent deformation of semiconductor chips by alleviating thermal stress and improve reliability.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing the main parts of a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIGS. 2(a), (b), and (C) are used in the semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view showing a preform bonding material most suitable for the semiconductor integrated circuit device of Example 1, and FIG. 4 is a main part of the semiconductor integrated circuit device of Example 2 of the present invention. FIG. 5 is a sectional view showing the main parts of a semiconductor integrated circuit device according to the third embodiment of this invention. FIG. FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 2... Die bonding board, 3... High thermal conductivity plate, 3a... Flow groove, 3b
...Through hole, 4...Brazing material (bonding material), 5.6...
- Metallized layer, 7... Preform brazing material (preform bonding material), 8... Die bonding layer, 9...
・Nilicon rubber (bonding material).

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device in which a semiconductor chip is mounted on a die bonding substrate via a bonding material, wherein the bonding layer formed by the bonding material has a plate-like high thermal conductivity formed from a high thermal conductivity material. A semiconductor integrated circuit device characterized in that a plate is interposed. 2. The semiconductor integrated circuit device according to claim 1, wherein the high thermal conductivity plate has a thermal expansion coefficient between that of the semiconductor chip and that of the die bonding substrate. 3. The semiconductor integrated circuit device according to claim 1, wherein the high heat conduction plate has grooves formed on both sides thereof, or a plurality of through holes extending through both sides of the high heat conduction plate. 4. The preform bonding material used in a semiconductor integrated circuit device according to claim 1, 2 or 3, wherein the high thermal conductivity plate is interposed in a bonding layer between the semiconductor chip and the die bonding substrate.