JPH03217060A - Nonvolatile semiconductor memory - Google Patents
Nonvolatile semiconductor memoryInfo
- Publication number
- JPH03217060A JPH03217060A JP9013290A JP1329090A JPH03217060A JP H03217060 A JPH03217060 A JP H03217060A JP 9013290 A JP9013290 A JP 9013290A JP 1329090 A JP1329090 A JP 1329090A JP H03217060 A JPH03217060 A JP H03217060A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- semiconductor memory
- layer
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000010410 layer Substances 0.000 claims abstract description 28
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 230000015556 catabolic process Effects 0.000 claims abstract description 8
- 239000002356 single layer Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000005684 electric field Effects 0.000 claims abstract description 4
- 238000007667 floating Methods 0.000 claims abstract description 4
- 238000009792 diffusion process Methods 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 11
- 239000001301 oxygen Substances 0.000 abstract description 11
- 229910052760 oxygen Inorganic materials 0.000 abstract description 11
- 150000004767 nitrides Chemical class 0.000 abstract description 7
- 125000004430 oxygen atom Chemical group O* 0.000 abstract description 4
- 230000007423 decrease Effects 0.000 abstract description 3
- 238000013329 compounding Methods 0.000 abstract 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 125000004433 nitrogen atom Chemical group N* 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000007688 edging Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- ZAOJWJAARUYTMA-UHFFFAOYSA-N 4-chloro-2-(5-chloro-2-hydroxy-3-nitrophenyl)sulfanyl-6-nitrophenol Chemical compound C1=C(Cl)C=C([N+]([O-])=O)C(O)=C1SC1=CC(Cl)=CC([N+]([O-])=O)=C1O ZAOJWJAARUYTMA-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】 （イ）産業上の利用分野 この発明は不揮発性半導体記憶装置に関する。[Detailed description of the invention] (b) Industrial application field The present invention relates to a nonvolatile semiconductor memory device.
さらに詳しくは、電気的プログラム可能な不揮発性半導
体記憶装置に関する。More specifically, the present invention relates to an electrically programmable nonvolatile semiconductor memory device.
（口）従来の技術
電気的プログラム可能な不揮発性半導体記憶装置（以下
ＯＴＰＲＯＭ）は、ユーザ側でプログラミングできるＲ
ＯＭとして汎用されている。(Note) Conventional technology Electrically programmable non-volatile semiconductor memory devices (hereinafter referred to as OTPROMs) are R
It is commonly used as OM.
」二記Ｏ Ｔ Ｐ Ｒ Ｏ Ｍは、半導体括板内にチャ
ンネルを構成しうるｌ対の不純物拡散領域からなる第ｆ
ｉｌｌ極と、このチャンネルヘ電界を｛ｔ 与しうるフ
ローティングゲートと、上記第１電極上に、電圧印加に
より絶縁破壊を生じうる絶縁層を介して積層され、外部
からの電圧が印加できるよう構成された第２電極とを備
えて構成されている。"2 O T P R O M is an f-th region consisting of l pairs of impurity diffusion regions that can constitute a channel in a semiconductor substrate.
An ill pole, a floating gate that can apply an electric field to this channel, and an insulating layer that can cause dielectric breakdown when voltage is applied are laminated on the first electrode, so that an external voltage can be applied. and a second electrode.
この上うな構成のＯＴＦＲＯＭにおいては、」二記絶縁
層は、例えば上層が窒化膜（Ｓ＋ｓＮ４等）、下層が酸
化膜（ＳｉＯ，）からなる多層積層膜で構成されている
。そして第１及び第２の電極間に高電圧（例えば１８Ｖ
程度）を印加しこの絶縁層を破壊することにより、プロ
グラムされることとなる。In the OTFROM having the above structure, the insulating layer 2 is composed of a multilayer stacked film in which the upper layer is a nitride film (S+sN4, etc.) and the lower layer is an oxide film (SiO, etc.). and a high voltage (e.g. 18V) between the first and second electrodes.
Programming is performed by applying a certain amount of heat to the insulating layer to destroy the insulating layer.
このプログラム１１１ｊは電極間の抵抗は大きいがプロ
グラム後は低抵抗となる。Although the resistance between the electrodes is large in this program 111j, the resistance becomes low after programming.
（ハ）発明が解決しようとする課題
絶縁層が上記のごとき多層積層膜で構成される場合、各
膜で誘電率（ε）及び模厚がそれぞれ異なるものとなる
（例えば上記Ｓｉ．，ｌ’Ｊａ膜の場合ε一８程度、膜
厚−１００〜３００人で、Ｓ ｉ Ｏ ２膜の場合ε−
３．８程度、膜厚＝１０−１００人である）。(c) Problems to be Solved by the Invention When the insulating layer is composed of a multilayer film as described above, each film has a different dielectric constant (ε) and a different thickness (for example, the Si. In the case of Ja film, ε is about 8, and the film thickness is -100 to 300, and in the case of SiO2 film, ε is
3.8, film thickness = 10-100 people).
絶縁破壊を実行する電圧は低い方が好ましく、例えばＥ
ＰＲＯＭに利用する場合このメモリに使用されている電
圧（１２．５Ｖまで）まで低下させる必要がある。これ
には上記絶縁層を薄くすることが考えられる。The voltage at which dielectric breakdown occurs is preferably low; for example, E
When used in PROM, it is necessary to lower the voltage to the voltage used in this memory (up to 12.5V). One possible solution to this is to make the insulating layer thinner.
しかしながら、誘電率の異なる界面が存在する多層絶縁
膜を薄くすると、破壊を意図しない部分まで破壊が生じ
ることがあり、信頼性の点で問題がある。However, when a multilayer insulating film in which interfaces with different dielectric constants exist is thinned, destruction may occur in areas that are not intended to be destroyed, which poses a problem in terms of reliability.
この発明はかかる状況に鑑み為されたものであり、薄く
かつ信頼性の高い絶縁層を宵ずる電気的プログラム可能
な不揮発性半導体記憶装置を提供しようとするものであ
る。The present invention has been made in view of the above situation, and it is an object of the present invention to provide an electrically programmable nonvolatile semiconductor memory device having a thin and highly reliable insulating layer.
（二）課題を解決するための手段
かくしてこの発明によれば、（ａ）基板内にヂャ３
ンネルを構成しうるｌ分の不純物拡散領域からなる第１
電極と、（ｂ）このチャンネルへ電界を付与しうるフロ
ーティングゲートと、（Ｃ）」二記第１電極」二に、電
圧印加により絶縁破壊を生じうる絶縁層を介して積層さ
れ、外部からの電圧が印加できるよう構成された第２電
極とを備えた、電気的書き込み可能な不揮発性半導体記
憶装置であって、」二記絶縁層が、単層のオギシ−ナイ
トライド膜からなることを特徴とする不揮発性半導体記
憶装置が提供される。(2) Means for Solving the Problems Thus, according to the present invention, (a) a first impurity diffusion region consisting of one impurity diffusion region capable of forming a channel in a substrate;
An electrode, (b) a floating gate capable of applying an electric field to this channel, and (C) "first electrode" (ii) are laminated via an insulating layer that can cause dielectric breakdown when voltage is applied, and are An electrically writable nonvolatile semiconductor memory device comprising a second electrode configured to apply a voltage, characterized in that the insulating layer is made of a single layer of oxy-nitride film. A nonvolatile semiconductor memory device is provided.
この発明の半導体記憶装置（以下半導体メモリという）
は、１回限り電気的プログラム可能な半導体メモリ（Ｏ
ＴＦＲＯＭ）において、プログラム用の静電破壊可能な
絶縁層を下記するもので構成する以外は、当該分野で公
知の飼料を用いて公知の方法により製造することができ
る。Semiconductor storage device of this invention (hereinafter referred to as semiconductor memory)
is a one-time electrically programmable semiconductor memory (O
TFROM) can be manufactured by a known method using materials known in the art, except that the insulating layer capable of being destroyed by electrostatic discharge for programming is constituted by the following.
この発明の半導体メモリにおいて、上記絶縁層は単層で
構成される。そしてこの絶縁層はオギンーナイトライド
膜からなる。該オキシーナイｉ・ライド膜は、通常のナ
イトライド膜を酸素雰囲気中４
に接触させることにより該膜中に酸素原子が浸入化合し
て得られるものを意味する。該オギンーナイトライド膜
において該膜中の酸素原子と窒素原子との組成比は、表
面では酸素リッチであるが、深さ方向に酸素組成比が減
少ずる。そして底而ては窒素リッヂとなることが好まし
い。また上記ナイトライド膜としてはＳｉａＮｔ等のシ
リコンナイトライド膜を好ましいものとして挙げること
ができる。In the semiconductor memory of the present invention, the insulating layer is composed of a single layer. This insulating layer is made of an Ogin-nitride film. The oxy-nitride film is obtained by bringing an ordinary nitride film into contact with an oxygen atmosphere and oxygen atoms entering the film and combining with it. In the Ogin-nitride film, the composition ratio of oxygen atoms to nitrogen atoms in the film is oxygen-rich at the surface, but the oxygen composition ratio decreases in the depth direction. And it is preferable that the bottom becomes a nitrogen ridge. Further, as the nitride film, a silicon nitride film such as SiaNt can be preferably mentioned.
この絶縁層において、オキシ−ナイトライド膜の単層か
ら構成されるとは、酸素原子及び窒素原子のいずれもが
存在しうる膜でかつ誘電率が異なる界面を有しないもの
を意味する。このためには例えばオキシーナイトライト
膜が上記酸素雰囲気中での酸素の浸透により形成される
場合、該膜の表面が窒素原子を含まない酸化膜に変化す
る場合はこの酸化膜が除去されることを意味する。上記
酸化膜の除去は、例えば当該分野で公知のエッヂング等
の手法をもって行うことができる。この一例としてはエ
ッヂング液としてフッ酸を用いかつこのエッヂングがも
はや進行しなくなったところで終了ずることにＪ；り、
酸化膜を完全に除去することができる。In this insulating layer, being composed of a single layer of oxy-nitride film means that it is a film in which both oxygen atoms and nitrogen atoms can exist and does not have an interface with a different dielectric constant. For this purpose, for example, if an oxynitrite film is formed by the penetration of oxygen in the oxygen atmosphere, and if the surface of the film changes to an oxide film that does not contain nitrogen atoms, this oxide film must be removed. means. The oxide film can be removed by, for example, a method known in the art such as etching. One example of this is to use hydrofluoric acid as the edging liquid and to end the edging process when it no longer progresses.
The oxide film can be completely removed.
」二記絶縁層を横成するオキシーナイトライ１・膜は、
２０〜１００人の膜厚に形成されることが好ましい。２
０人よりも薄いときは信頼性の点で不安を残し、１００
人よりも厚いときは破壊電圧が高くなって汎用性の点で
好ましくない。”The oxynitride 1 film forming the insulating layer 2 is:
It is preferable to form the film to a thickness of 20 to 100 people. 2
If the number is less than 0, there will be concerns about reliability, and 100
If it is thicker than a human body, the breakdown voltage will be high, which is undesirable in terms of versatility.
（ホ）作用
この発明によれば、第１電極と第２電極との間に形成さ
れる絶縁層は、誘電率が異なる界面を有しないオギンー
ナイトライド膜の単層で構成されているので、絶縁層全
体にわたってほぼ一様な性質を有する安定なものとなる
。(E) Effect According to the present invention, the insulating layer formed between the first electrode and the second electrode is composed of a single layer of Ogin-nitride film that does not have an interface with different dielectric constants. , the insulating layer becomes stable with substantially uniform properties over the entire insulating layer.
以下実施例によりこの発明を詳細に説明するが、これに
よりこの発明は限定されるものではない。EXAMPLES The present invention will be explained in detail below with reference to Examples, but the present invention is not limited thereby.
（へ）実施例
この発明の不揮発性半導体記憶装置の一例であるＯＴＰ
ＲＯＭの製造工程に関して、下記第１〜３図に堰づいて
説明する。(f) Example OTP which is an example of the non-volatile semiconductor memory device of this invention
The manufacturing process of the ROM will be explained with reference to FIGS. 1 to 3 below.
）まず、Ｐ型シリコン（Ｓｉ）半導体基板（１）上に、
ゲート酸化膜を形成した後、多結晶ノリコン（ｐｏｌｙ
ｓｉ）膜からなる電極（２）を形成する。) First, on a P-type silicon (Si) semiconductor substrate (1),
After forming the gate oxide film, polycrystalline
An electrode (2) made of si) film is formed.
）次いてその」二にシリコン酸化ＩＪ（ＳｉＯ，）（３
）を堆積後、ｎ型不純物を拡散Ｌ１二人し、さらに熱処
理を行うことにより、Ｐ型Ｓｉ基板上に１１ Ｂ＋”不
純物領域（ブし１グラム用の第１電極）（４）を形成す
る。) Next, silicon oxide IJ (SiO,) (3
) is deposited, an n-type impurity is diffused into L1, and further heat treatment is performed to form an 11 B+” impurity region (first electrode for 1 gram) (4) on the P-type Si substrate. .
ｉｉｉ ） Ｊｚ記堆積されたＳ１０２において、第１
電極」二の所定の部分にプログラム用窓（５）をエッヂ
ングを用いて開１ノ、次いでＳｉＯＪ二にナイトライド
膜（例えばＳ ｉａＮ４） （６）をＬＰＣＶＤ法によ
り、薄く（例えば５０人）堆積する（第１図参照）。iii) In the deposited S102, the first
A programming window (5) is opened in a predetermined portion of the electrode 2 using etching, and then a nitride film (for example, SiaN4) (6) is deposited thinly (for example, 50 times) on the SiOJ 2 by the LPCVD method. (See Figure 1).
ｉｖ）次に、上記ｃ１１）で得られたものを、酸素雰囲
気中で９００゜Ｃで熱処理を行う。これにより」二記ナ
イトライド膜はオギシーナイトライド膜（６１）となる
。このオキシーナイ１−ライド膜中では、酸素不純物濃
度は、表面では高くほぼ酸化膜（７）となり、厚さ方向
に従って次第に減少している（第２図参照）。iv) Next, the material obtained in c11) above is heat treated at 900°C in an oxygen atmosphere. As a result, the nitride film described in "2" becomes an ogish nitride film (61). In this oxy-1-ride film, the oxygen impurity concentration is high at the surface, almost becoming an oxide film (7), and gradually decreases in the thickness direction (see FIG. 2).
７
■）次いで上記で得られたオキシ−ナイトライド膜を、
フッ酸に浸漬して該膜表面の酸素高濃度領域（いわゆる
酸化膜領域）を除去する。7) Next, the oxy-nitride film obtained above was
The high oxygen concentration region (so-called oxide film region) on the surface of the film is removed by immersion in hydrofluoric acid.
ｖｉ）この後、」二記酸化膜（７）が除去されたオキシ
−ナイトライド膜（８）上にボリンリコン（第２電極）
（９）を堆積し、次いでｎ型不純物を拡散してこのポリ
ソリコンの低抵抗化を図ることにＪ；り、第３図に示ず
構造のＯＴＰＲＯＭが得られることとなる。vi) After this, borinlicon (second electrode) is placed on the oxy-nitride film (8) from which the second oxide film (7) has been removed.
By depositing (9) and then diffusing n-type impurities to lower the resistance of this polysilicon, an OTPROM having a structure not shown in FIG. 3 is obtained.
上記のようにして製造されたＯＴＦＲＯＭは、プログラ
ム電圧が１２．５Ｖ以下でオキシーナイｉ・ライド膜（
絶縁層）を破壊することが可能であった。The OTFROM manufactured as described above has an oxynide film (
It was possible to destroy the insulating layer).
また、この絶縁層の膜厚が薄いにもかかわらず意図しな
い部分での絶縁破壊が生じず信頼性も向上したものであ
った。Furthermore, despite the thinness of this insulating layer, no dielectric breakdown occurred in unintended areas, and reliability was improved.
（１・）発明の効果
この発明によれば、薄くてかつ性能の良好な絶縁層を形
成でき、信頼性が高い電気的プログラム可能な不揮発型
半導体記憶装置を提供することができる。(1.) Effects of the Invention According to the present invention, a thin insulating layer with good performance can be formed, and a highly reliable electrically programmable nonvolatile semiconductor memory device can be provided.
８
またこの発明の記憶装置は、絶縁膜の低抵抗化が図られ
ているので、ＥＰｒ｛ＯＭに利用することができる。8. Furthermore, since the memory device of the present invention has a low resistance insulating film, it can be used for EPr{OM.
第１〜３図は、この発明の不揮発型半導体記憶装置の一
例のＯ Ｔ Ｐ ｒ｛．Ｏ Ｍに関して、その製造工程
の各段階で得られる各積層構造をそれぞれ説明する部分
構成説明図である。
第
１
図
第
２
図
４１６1 to 3 show OTP r{. of an example of a nonvolatile semiconductor memory device of the present invention. FIG. 2 is a partial structural explanatory diagram illustrating each laminated structure obtained at each stage of the manufacturing process of OM. Figure 1 Figure 2 Figure 416
Claims (1)
物拡散領域からなる第１電極と、（ｂ）このチャンネル
へ電界を付与しうるフローティングゲートと、（ｃ）上
記第１電極上に、電圧印加により絶縁破壊を生じうる絶
縁層を介して積層され、外部からの電圧が印加できるよ
う構成された第２電極とを備えた、電気的書き込み可能
な不揮発性半導体記憶装置であって、 上記絶縁層が、単層のオキシ−ナイトライド膜からなる
ことを特徴とする不揮発性半導体記憶装置。[Claims] 1. (a) a first electrode consisting of a pair of impurity diffusion regions that can form a channel in the substrate; (b) a floating gate that can apply an electric field to this channel; (c) An electrically writable non-volatile semiconductor, comprising a second electrode laminated on the first electrode via an insulating layer that can cause dielectric breakdown when voltage is applied, and configured to allow external voltage to be applied. A non-volatile semiconductor memory device, wherein the insulating layer is made of a single layer of oxy-nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013290A JP2568715B2 (en) | 1990-01-22 | 1990-01-22 | Nonvolatile semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013290A JP2568715B2 (en) | 1990-01-22 | 1990-01-22 | Nonvolatile semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03217060A true JPH03217060A (en) | 1991-09-24 |
| JP2568715B2 JP2568715B2 (en) | 1997-01-08 |
Family
ID=11829068
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013290A Expired - Fee Related JP2568715B2 (en) | 1990-01-22 | 1990-01-22 | Nonvolatile semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2568715B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7991124B2 (en) | 2005-03-14 | 2011-08-02 | Scenera Technologies, Llc | Method and system for collecting contemporaneous information relating to a critical event |
-
1990
- 1990-01-22 JP JP2013290A patent/JP2568715B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7991124B2 (en) | 2005-03-14 | 2011-08-02 | Scenera Technologies, Llc | Method and system for collecting contemporaneous information relating to a critical event |
| US8619947B2 (en) | 2005-03-14 | 2013-12-31 | Scenera Technologies, Llc | Method and system for collecting contemporaneous information relating to an event |
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| JP2568715B2 (en) | 1997-01-08 |
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