JPH03212749A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To restrict a specific part of a shared memory and to protect it by permitting an access only when a processor number coincides with a block number capable of accessing each block of the shared memory. CONSTITUTION:A memory access permission flag part 14 sets up the area of a block number N in the shared memory 9 so as to access the area only from a processor having a block number '3'. When a memory space corresponding to the block number N is accessed, a NAND gate 16 is opened, a chip enable signal outputted from a decoder 12 is made effective and the memory space corresponding to the block number N of the memory 9 can be accessed. Since the use of a specific part in the memory 9 can be restricted to a specific processor, the memory 9 can be protected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor system in which a plurality of processors have a shared memory and are connected via a shared bus.

[Conventional technology]

In a multiprocessor system, as shown in FIG. 5, a plurality of processors la, lb, etc. are connected to a shared memory 9 via a shared bus 5.
These multiple processors la, lb.

The shared memory 9 is accessed from time to time.

In this way, multiple processors la, lb,...
By performing processing in parallel, the processing speed of the entire system is increased (for example, Suzuki et al.'s ``High-speed Parallel Processing Workstation (TOP-1)''
J, Information Processing Society of Japan 37th (late 1986) National Conference Proceedings 1, pp. 171-173).

As shown in FIG. 6, the shared memory 9 generally includes a plurality of memory chips 9a, 9b, . . . , each of which is assigned to a different address space. When each processor la, lb, . . . accesses the shared memory 9, an address signal is supplied via the shared bus 5 and the bus interface 11 in the memory system 20,
The memory chip containing the address specified by 3 is enabled, and data is written or read via the bus interface 11.

[Problem to be solved by the invention]

However, in a conventional multiprocessor system, all processors la, lb, etc. have equal access to the shared memory 9, and any processor la, lb, etc. can access an arbitrary address in the shared memory 9.
Since access is performed from lb, . . . , the following inconvenience may occur under certain operating conditions.

For example, if a certain processor malfunctions, the contents of the shared memory 9 may be rewritten and become different from the original data. If this erroneous data is read by another normally operating processor, the results obtained by the other processor's processing will be erroneous. That is, there is a disadvantage that malfunction of one processor adversely affects the operation of another processor.

In particular, when debugging a system program, if a debugger program is run on a specific processor, the memory blocks used by that processor must be made unavailable to other processors.
Such processing was not possible with conventional multiprocessor systems.

An object of the present invention is to protect shared memory by limiting processors that can access a specific portion of shared memory to specific processors.

[Means to solve the problem]

In order to achieve the above object, the multiprocessor system of the present invention allocates individual processor numbers to each of the plurality of processors, divides the address space of a shared memory shared by the plurality of processors into a plurality of blocks, and When accessing the shared memory from a processor, the processor number is detected, and the shared memory is accessed only when the processor number matches a pre-recorded processor number that can access each block of the shared memory. It is characterized by allowing.

[Effect]

In the multiprocessor system of the present invention, when accessing the shared memory, in addition to normal signals such as address and data, a processor number for identifying the source of the access is output. The memory system side detects this processor number and the address being accessed,
Actual access to the shared memory is controlled based on data indicating the relationship between a pre-recorded address and a processor number that can access that address.

〔Example〕

DETAILED DESCRIPTION OF THE INVENTION Hereinafter, features of the present invention will be specifically described based on examples with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of a processor in a multiprocessor system of the present invention.

In the processor of this embodiment as well, a CPU 2 is connected to a shared bus 5 via a cache memory 3 and a bus interface 4, as in the conventional processor.

Further, a memory management unit 6 is provided between the CPU 2 and the bus interface 4, and the CPU 2 also has an F
PU7 is connected.

In this embodiment, in addition to the above configuration, a processor number setting unit 8 is provided, and the value set here, that is, the processor number assigned to each processor, is stored in the shared memory 9 ( 3) is output through the bus interface 4.

For example, as shown in FIG. 2, the processor number setting section 8 includes a switch section 81 consisting of switches 81a to 81d.
．． Pull-up resistors 82a-82d, buffers 838-8
3b, etc., and a predetermined numerical value can be set as the processor number. In addition, the switches 818 to 81
d is D' I P (dual 1nline
package) switch, jumper wire, ROM (
read only memory), etc. can be used. In this embodiment, since the switch section 81 has 4 bits, the processor number can be set in the range of 0 to 15. Note that here, the switch 81a side is LSD(l
east 51gn1ficant digit).

FIG. 3 shows an example of the configuration of the memory system 10 in the multiprocessor system of the present invention. Similar to the conventional memory system 20 shown in FIG. Interface 11.
Decoder 12. A multiplexer 13 and the like are provided, and in this embodiment, in addition to these, a memory access permission flag section 14 and a memory access permission determination circuit 15 are provided.

The memory access permission flag unit 14 is a RAM (ra
For example, the address space of the shared memory 9 is divided into a plurality of blocks and sequentially assigned block numbers are used as address inputs, and an access permission flag set in the RAM is used as data output. That is, data indicating which processor can access a predetermined address space of the shared memory 9 is written in the memory access permission flag section 14. Note that the block number is assigned as part of the address.

The access permission flag from the memory access permission flag unit 14 is supplied to the memory access permission determination circuit 15 together with the processor number obtained from the shared bus 5 via the bus interface 11, and it is determined whether access to the shared memory 9 is possible. It will be judged. When it is determined that access is possible, the decoder 1
2 is supplied to the chip enable terminal CB of the shared memory.

The configuration example of the memory access permission determination circuit 15 described above is shown in the fourth example.
As shown in the figure.

The 4-bit processor number from the bus interface 11 is decoded by the decoder 17 into a 16-bit output number as shown in Table 1.

(Hereinafter, blank spaces) Table 1 Then, in the AND circuit 18, an AND operation is performed between each bit of the output number from the decoder 17 and each bit of the access permission flag. Further, all bits of the result of the AND operation are subjected to an R operation in the OR circuit 19, and if 1 is output, it is determined that access is possible, and if 0 is output, it is determined that access is not possible.

For example, when setting the processor number of processor 1 shown in FIG.
The output of 3a, 83b, 83c, 83d is 1.1,
It becomes 0.0. Here, since the switch 81a is on the LSD side, the binary data of the processor number obtained from the processor number setting section 8 is 0011.

This 4-bit processor number is passed through the bus interface 4 to the shared bus 5 when accessing the shared memory 9.
is output to the memory access permission determination circuit 15 via the bus interface 11 of the memory system 10.
The signal is supplied to the decoder 17, and a 16-bit output signal o001000000000000 is obtained as shown in Table 1.

Further, in the memory access permission flag unit 14, for example, for the area of block number N of the shared memory 9,
Assuming that the setting is such that access is possible only from the processor whose processor number is 3, when the memory space corresponding to block number N is accessed, the 16-bit output from the memory access permission flag unit 14 is ,0001000000000000. Therefore, the data of the fourth bit from the higher order of the AND circuit 18 is 1.
Therefore, the output of the OR circuit 19 also becomes 1. therefore,
The NAND gate 16 is opened, the chip enable signal from the decoder 12 is enabled, and the memory space corresponding to block number N of the shared memory 9 can be accessed.

On the other hand, if an attempt is made to access from a processor whose processor number is not 3, the data of the fourth bit from the top of the output of the memory access permission flag section 14 will be 0, so the output of the coder 17 and the access permission flag will not match. AND circuit 1g.

The output of the OR circuit 19 becomes 0. In other words, access to the shared memory 9 becomes impossible.

〔Effect of the invention〕

As described above, according to the present invention, the shared memory of a multiprocessor is divided into multiple blocks, and processor access is prohibited or permitted in block units. Memory can be protected for limited use. therefore,
For example, when debugging a system program,
When running a debugger program on a specific processor, you can prevent the memory blocks used by that processor from being used by other processors.
Debugging work can be performed without any problems.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of one processor in the multiprocessor system of the present invention, FIG. 2 is a circuit diagram showing an example of the configuration of a processor number setting section provided in the processor of FIG. 1, and FIG. 4 is a block diagram showing an example of the configuration of a memory system in the multiprocessor system of the present invention, FIG. 4 is a block diagram showing an example of the configuration of a memory access permission determination circuit provided in the memory system of FIG. 3, and FIG. FIG. 6 is a block diagram showing a general configuration of a processor system. FIG. 6 is a block diagram showing an example of the configuration of a memory system in a conventional multiprocessor system. ! , la, lb: Processor 2: CPU 3: Cache memory 4: Bus interface 5: Shared bus 6: Memory management unit 7: FP
U 3: Processor number setting unit 9: Shared memory 9a, 9b: Memory chip 10.20: Memory system 11: Bus interface 12: Decoder 13: Multiplexer 14: Memory access permission flag unit 15: Memory access permission determination circuit 16: NAND Circuit 17; Decoder 18: AND circuit 19: OR circuit 81: Switch section 81a
~81d: Switches 82a~82d Nibble-up resistor 33a ~83d: Buffer

Claims (1)

[Claims] 1. Assign an individual processor number to each of the plurality of processors, divide the address space of the shared memory shared by the plurality of processors into a plurality of blocks, and when the processor accesses the shared memory, the processor A multiprocessor system that detects a processor number and permits access to the shared memory only when the processor number matches a prerecorded processor number that can access each block of the shared memory.