JPH03205985A - Multiprocessor type moving image encoder and bus control method - Google Patents

Abstract

PURPOSE:To utilize the throughput of a multiprocessor at a maximum by dividing a picture into plural blocks and sharing a processing task respectively equally for plural unit processor modules. CONSTITUTION:The picture is divided into the plural blocks by a task control part 7 and while referring a task table 8 storing information required for controlling the unit processors, a processing block and a processing task optimum to each unit processor module 11 are decided. Then, encoding is executed while sharing the processing task respectively equally for the plural unit processor modules 11. Plural shared memories 10 to store local decoding data or data under encoding and parameter are connected through plural memory buses, which are independently provided, to the respective plural unit processor modules 11 and the plural memory buses can be utilized for the access of the shared memory. Thus, the throughput of the multiprocessor can be utilized at a maximum.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor-type video encoding device that performs encoding in units of blocks by having a plurality of unit processors share processing tasks.

[Conventional technology]

Figure 19 shows, for example, PCS '88 Pl5.2 "^
RCHITECTtJRE OF A FULL MO
TION 64KBIT/S VIDEO CODIE
Conventional multiprocessor type video encoding device W described in “C” (hereinafter sometimes referred to as “Conventional Example 1”)
FIG. 2 is a block diagram showing the configuration of FIG. As shown in the figure, C
A VME bus 5 linked to the PU 1 includes a shared memory 2 and unit processors (digital signal processing processors) 3a to 3.
3h is connected. Each unit processor 3a to 3h is provided with local memories 48 to 4h, and each local memory 4a to 4h and the shared memory 2 are connected to a memory bus 6.
are linked by. Input data 100 is input to the shared memory 2, and transmission data 101 is output to the CPU 1, respectively.

Note that this system has a parallel configuration using unit processors and performs fixed image region division processing.

In FIG. 19, six of the eight unit processors are designated as brightness signal unit processors,
The image is equally divided into 6 parts by vertical lines, each unit processor has an assigned area, and the 2 unit processors are responsible for 2 types of color difference signals, and each unit processor performs encoding processing for its own area. It looks like this.

Also, normally, in video encoding, an image frame is divided into L regions (L is an integer of 1 or more, 3 in the example of FIG. 20), and
The encoding control parameter (T
Feedback control such as setting CR) is performed, and FIG. 20 shows the region division of an image frame by a unit processor and the region division for feedback control. In order to simplify the explanation, FIG. 20 is an example in which three unit processors are used to divide the image into three areas, perform feedback control, and encode only the luminance signal. Each area is divided into three areas A, B, and C, and each area is further divided into three areas A1 to A3 and 81 to B.
3, it is divided into three closed regions c1 to c3.

Next, the operation will be explained.

Input data 100 is written into the shared memory 2 for one frame.

Then, the CPUI instructs the eight unit processors 3a to 3h to sequentially transfer the data, and each unit processor 3a to 3h receives the input data of its own area from the shared memory 2 via the memory bus 6 and the code of its own area. The feedback data that has already been encoded in the past in the area required for encoding is transferred to its own local memories 4a to 4h, respectively.

Then, the unit processors 3a to 3h that have completed the transfer next divide their first responsible area into blocks of processing units, sequentially execute multiple types of processing tasks for each block in a predetermined order, VM encoded data
The encoded data is transferred to the CPU 1 via the E bus 5, and the encoded data is locally decoded to create feedback data, which is then transferred to the shared memory 2 via the memory bus 6.

In this way, the unit processors 3a to 3h, which have finished processing the first area in charge, enter a waiting state until they receive an instruction from the CPU to start processing the next area (as shown in FIG. 21, all unit processors #1 ~Series of task processing in #3 (
The next process cannot be performed until TI, T2) is completed)
.

Then, the CPUI receives encoded data from each unit processor 3a to 3h via the VME bus 5, reconfigures the data in the order according to the transmission format, and adds multiplex information to create transmission data 101. Furthermore, each unit processor 3a to 3h monitors the completion of processing in its assigned processing area, and when it is detected that all unit processors 3a to 3h have finished processing in their assigned processing area, each unit processor 3a -3h, instructs to start processing the next processing area.

By the way, even in the case of fixed region-divided parallel processing as in this example, when each unit processor 3a to 3h transfers input data from the shared memory 2 to its own local memory 4a to 4h at the start of processing of a certain divided region, Also, when each unit processor 3a to 3h finishes processing in its own area and transfers feedback data from the local memory 4 to the shared memory 2, bus contention occurs on the memory bus 6.
At this time, each unit processor 3a to 3h is in a waiting state until it receives a shared memory access instruction.

Furthermore, in the case of task-distributed parallel processing in which variable areas and tasks are allocated to each unit processor 3a to 3h in a parallel configuration at any time according to the amount of calculation, a shared memory access request is issued every time a task is completed. In this case, as the number of parallel unit processors 3a to 3h increases, the above bus contention occurs frequently, and
The processing efficiency will be reduced.

The above is a description of the multiprocessor type video encoding device of Conventional Example 1.

FIG. 22 shows a conventional multiprocessor type video encoding device (hereinafter referred to as
FIG. 2 is a block diagram of a conventional example (sometimes referred to as "conventional example 2"). This multiprocessor type video encoding device has 1
A screen (frame) is divided into a plurality of divided screens A to C as shown in FIG. 23, for example, and one unit processor (unit signal processor) is assigned to each divided screen A to C. The aim is to achieve high-efficiency encoding of video signals (TV signals, etc.) by processing image signals in parallel.

In FIG. 22, 51 is an input bus for input image signals such as television signals (hereinafter referred to as TV signal input), 52 is a feedback bus for encoded/decoded partial screen signals, and 53 is a feedback bus for encoded/decoded partial screen signals.
1 is an output bus for encoding results, and 41 to 43 are unit processors, which respectively process the divided screens A to C. Each of the unit processors 41 to 43 includes an intake section 55,
It includes a processing section 56 and an output section 57. This capture unit 55 receives an input image signal (partial image signal) of the segmented screen area for which it is responsible from the input bus 51 in synchronization with a capture command for the segmented screen area for which it is responsible, and encodes it from the feedback bus 52 for neighborhood processing, which will be described later. - Capture and store the decoded signal. Regarding neighborhood processing, please refer to Japanese Unexamined Patent Publication No. 1986-
There is a method disclosed in No. 266678. The processing unit 56 performs processing such as encoding/decoding on the stored image data. The output unit 57 synchronizes with the next acquisition signal and sends the encoded signal as a processing result of the processing unit 56 to the output bus 53, and also sends the encoded/decoded signal described above to the feedback bus 52 as an input image auxiliary signal. to other unit processors.

Next, the operation will be explained. For convenience of explanation, here we will show a case where the entire screen is divided into three parts and processed by three unit processors.
-C, and each corresponds to unit processors 41 to 43 corresponding to #1 to #3.

On the input lotus 51, the input partial screen signals S1 to S3 as television signals corresponding to the partial screens A to C are displayed on the 27th screen.
As shown in the figure, the flow is continuous in time. For example, the #1 unit processor 41 receives the #1 signal on the input bus 51 in accordance with the timing of the import operation as shown in FIG.
1 input partial screen signal S1 is captured into the capturing section 55 and stored. Here, each input partial screen signal 81 to s3 is F(
natural number) is input at a constant speed of sheets/second. For this reason,
The processing of each of the captured input partial screen signals 81 to S3 must be completed before the next input partial screen signals s1 to s3 are captured.

On the other hand, the partially encoded signal obtained as a processing result is output to the output bus 53 at the same time as the next capture. Also,
In the motion compensated interframe coding method, which is often applied as a high-efficiency image coding technique, input images P and 1
Encoding is performed by taking the difference from the image Q shown in FIG. 28, in which the position on the screen is shifted by the amount of movement in the previous decoded screen. Therefore, for the encoding process, an encoded/decoded screen whose area has expanded by the amount of motion is required. In this way, for encoding, the input partial screen (No. 2 81 to
A signal with a wider range than S3 is required.

Further, the encoded/decoded partial screen signals F1 to F3 are output from the output section 57 to the feedback bus 52, and the 27th
The capture unit 55
captured and memorized.

At this time, since data in a wider range than the input partial screen signals 81 to S3 is captured, the capture time is lengthened by t time. In this way, the encoding process is executed while taking in encoded/decoded partial screen signals F1 to F3 in a wider range than the allocated partial screen, and signals 01 to 03 are output to the output bus 3.

FIGS. 24 and 25 show the relationship between the signal acquisition time and processing time of each unit processor 41 to 43 for signals on each bus in a simpler manner than in FIG. 27. , unit processors in charge of divided screens A to C are indicated by #1 to #3.

In FIG. 24, the total processing time of each unit processor #1 to #3 for encoding/decoding the image signal is less than the input cycle of one image frame on the input bus 51, so the above processing is stagnant. However, if a part of an image frame has more movement than other parts of the image, for example, unit processor #2 in charge of the part
As shown by diagonal lines in FIG. 25, the processing time of the unit processor #1 and #3 becomes longer than the processing time of the other unit processors #1 and #3, and a standby time occurs in the unit processors #1 and #3.

The above is a description of the multiprocessor type video encoding device of Conventional Example 2.

[Problem to be solved by the invention]

Since the multiprocessor-type video encoding device of Conventional Example 1 is configured as described above, when the amount of calculation required for processing fluctuates extremely due to spatial and temporal changes, such as video encoding ( (See FIG. 21), a unit processor that has finished processing its assigned area has to wait until all other unit processors have finished their processing, resulting in a problem that the processing efficiency per unit processor is low. Therefore, the number of parallel units of a unit processor must be set assuming the maximum processing amount of the area in charge, and the number of parallel units becomes extremely large.
As the number of parallel processing increases, the number of processing heads also increases, and if the processing block size differs depending on the task, the number of parallel processing per unit processor increases because it cannot be divided into smaller blocks than the maximum block size and allocated to the unit processor. There were problems such as there is a limit to the number of connections, the capacity of local memory becomes large when the number of parallels is small, and it is difficult to perform feed-back operations.

In addition, since a shared memory access request is issued when shared memory access is required, bus contention occurs when two or more processors issue shared memory access requests at the same time, resulting in processors that are not given permission to use the memory. will not be able to perform any action until permission is granted.)<
There is a problem in that processing efficiency is reduced due to sune and sok. For example, in order to perform motion compensation and discrete cosine transform encoding on a 16x16 pixel image as a unit of processing, approximately 1,400 words of data are required to be transferred, and there is a fairly high probability that nokusune/soku will occur. Put it away.

On the other hand, since the multiprocessor type video encoding device of Conventional Example 2 is configured as described above, the unit processor 41
A type of pipeline processing is performed on the premise that the processing time of ~43 will be within a certain time of 17F, so in image processing such as high-efficiency encoding, the processing time varies depending on the input image. However, as mentioned above, the number of screen divisions must be set based on the longest processing time. However, if the divided screens handled by unit processors #1 to #3 are continuous, local bias in image properties (difference in the amount of data to be processed) may occur in one image frame. Since this phenomenon occurs intensively in the image signals handled by one unit processor, it is difficult to reduce the maximum processing time. Therefore, even if the average processing time is considerably shorter than the maximum value, the number of divisions cannot be reduced, and there are problems in that it is necessary to prepare a large number of unit processors 41 to 43. Another problem arises in that increasing the number of unit processors increases the cost of the image processing processor.

This invention was made in order to solve the above-mentioned problems, and it is a multi-processor type video that can utilize the processing power of a multiprocessor consisting of a plurality of unit processors to the maximum extent possible. The purpose is to obtain an image code fhi device.

[Means to solve the problem]

According to claim 1 of the present invention, there is provided a digital signal processing unit processor for processing a digital signal that executes encoding according to an encoding program C; Arbitrates interrupt signals sent from the connected local memory and control bus and delivers them to the unit processor. : Consists of an interrupt control section that receives the address and data of the unit processor via the control node, decodes it, generates an interrupt signal, and sends it to the control node, each of which operates in parallel. locally decoded data or data in the middle of encoding and/or data connected to each of the plurality of unit processor modules via a plurality of independently installed memory spaces; It has a plurality of shared memories for storing parameters and a plurality of nodes/nofa structure, with one side being left open to the circuit for writing input data and the other side being open to the unit processor module, so that writing and reading are asynchronous. an input frame memory that can be used, a task table that stores past history, current situation, future predictions, etc. regarding the processing task contents of each of the unit processor/nosa modules, and a task table that divides the image into multiple blocks. The optimal processing block and processing task for each unit processor/source module are determined by referring to and a task control section that performs encoding by causing the plurality of unit processor/source modules to share the processing task almost equally in response to an instruction.

The bus control method according to claim 2 provides a method for controlling a memory when two or more unit processors for digital signal processing are connected to a shared memory that can be accessed via a single memory bus in a time-sharing manner. In the bus control method, each of the unit processors/sources issues an access request to the shared memory a certain period of time before the end of processing, and in response, the unit processors/sources issue access requests to the shared memory in order from the unit processor/source with the highest priority. Access requests are granted.

Further, the multiprocessor type moving image encoding device according to claim 3 shares a specific screen position area on one screen and captures a partial image signal corresponding to the specific screen position area of the input image signal. It has a plurality of unit processors for digital signal processing that performs signal processing and sends it to the output bus, and each unit processor can take in the signal-processed signals of other unit processors as input image auxiliary signals for nearby processing. After each of the unit processors shares a plurality of discontinuous screen position areas, and all unit processors take in the input partial image signals of the screen position areas shared, the signals of the input partial image signal and the input image auxiliary signal are input. Start processing all at once.

Furthermore, the multiprocessor type moving image encoding device according to claim 4 further includes a capture unit that captures the input partial screen signal inputted to the input bus in units of frames, and a capture unit that captures the input partial screen signal input to the input bus in units of frames, and encodes/decodes the input partial screen signal. a processing unit that performs processing, an output unit that outputs an encoded/decoded partial screen signal that is a processing result of partial encoding in the processing unit, and a storage that stores the encoded/decoded partial screen signal. a control section that controls the acquisition, processing, storage, and output in each of the unit processors, and a storage section that stores the encoded/decoded partial screen signal. When storing a part of the encoded/decoded partial screen signal necessary for processing the next frame, it is stored so that it can be read and written from at least one of the own unit processor and the other unit processors. A shared storage section is provided.

[Effect]

In the multiprocessor type video encoding device according to claim 1, the task control unit divides the image into a plurality of blocks and refers to a task table in which information necessary for controlling the unit brosses and saucers is stored. The optimum processing block and processing task for each unit processor module are determined, and the processing tasks are shared approximately equally among the plurality of unit processor modules to perform encoding and thereby shorten the waiting time. Further, a plurality of shared memories for storing locally decoded data or data and parameters being encoded are connected to each of the plurality of unit processor modules via a plurality of independently provided memory buses, and access to the shared memory is provided. Because multiple memory buses are available in the system, there are no bus necks when accessing shared memory.

In the bus control method according to claim 2, since each unit processor always issues a bus usage request a certain period of time before completing the previous process, even if bus contention occurs when outputting a bus usage request, , the unit processor does not go into a waiting state and continues executing the previous process, so the processing efficiency of the processor does not decrease.

In the multiprocessor type video encoding device according to claim 3, one unit processor is in charge of image signals of a plurality of divided screens, and since the divided screens are separate areas that are not continuous, one image frame is It is unlikely that local deviations in image properties will appear concentrated in the image signal handled by one unit processor, and even if the processing time for the partial image signal of one divided screen is long, the If the processing time for an image signal is short, the processing time for one frame is averaged. In addition, the encoding process is performed by all unit processors waiting for the start of a new screen, and the exit of the encoded signal to the output bus and the transfer of the input image auxiliary signal to other unit processors are performed at the end of all unit processors. Therefore, even if the encoding process for a certain frame exceeds the input cycle, it can be absorbed by other frames that can be processed within the input cycle, and the processing time is averaged out from the perspective of the entire frame process. .

In the multiprocessor type video encoding device according to claim 4, one screen is divided into a plurality of partial screens, each partial screen is processed by a dedicated unit processor, and in this process, the encoded/decoded partial screen is processed by a dedicated unit processor. storing the signal in a storage section within its own unit processor, and at the same time storing a portion of the signal that needs to be referenced from other unit processors in a shared storage section that is also accessible from other unit processors; This allows the encoded/decoded partial screen signals written by other unit processors to be used in the shared storage during encoding processing, allowing the number of partial screen divisions to be determined based on the average processing time. If the processing time is longer than the average value, the input speed of the input partial screen signal is reduced, thereby reducing the number of unit processors used.

Note that the relationship between the first to fifth embodiments described in detail below and each claim is shown below.

First and second embodiments: Multiprocessor type video encoding device according to claim 1 Third embodiment: Bus control method according to claim 2 Fourth embodiment: Multiprocessor type according to claim 3 Fifth Embodiment of Moving Image Coding Device: Multiprocessor type moving image coding device according to claim 4 [Embodiment] First to fifth embodiments of the present invention will be described below.

Note that the first to third embodiments are embodiments corresponding to the first conventional example, and the fourth and fifth embodiments are embodiments corresponding to the second conventional example.

FIG. 1 is a block diagram showing the configuration of a multiprocessor type moving image encoding apparatus, which is a first embodiment of the present invention.

As shown in the figure, the task control unit 7 connects a control bus 12 ( (corresponding to the VME bus 5 of Conventional Example 1), and refers to the task table 8 to instruct each unit processor module 11 with commands regarding the block position and processing task content. The task table 8 indicates that the task control unit 7 is in the middle. Information necessary to control the processor module 11, such as past history, current status, and future predictions regarding various task processing, is stored.

In addition, 9 has a plurality of buffers, one side of which is open to a circuit for writing input data, and the other side of which is open to unit processors so that writing and reading can be performed asynchronously. 10a to 10n are connected to each unit processor module 11. This is a shared memory that stores locally decoded data or data and parameters that are being encoded. These input frame memories 9, shared memories 10a to 10n
are respectively connected to unit processor modules lla-llk via memory buses 13, 14a-14n. Note that 15 is an I/O bus, and 16 is a multiprocessor module.

Figure 2 is the unit processor module shown in Figure 1]1
1 is a block diagram showing an instruction memory 17 in which an encoded program is written, and 18 an instruction memory 18 for arbitrating an interrupt signal 102 sent from the outside via a control bus 12 and floating it in the unit processor 3. At the same time, the address and data 10 are transferred from the local bus 19 of the unit processor 3.
4, decodes it, generates an interrupt signal, and sends it to the control bus 12.

Further, 20 is a command port for transferring command data between the control bus 12 and the unit processor 3;
21n+2 is a bidirectional buffer provided between the memory buses 13, 14a to 14n and the unit processor 3;
Output enable and direction are controlled by instructions from unit processor 3.

22 is a local RAM connected to the local bus 19 of the unit processor 3, and 23 is a local ROM in which encoding parameters used in encoding executed by the unit processor 3 are written.

In such a structure, input data 100 is written on one side of the input frame memory 9 in units of frames, and already written input data is read out in units of frames from the other side.

Then, the task control unit 7 learns of the end of input frame memory writing from the frame synchronization pulse 103 from the input frame memory 9, refers to the task table 8, arbitrates with the encoding process, and stores data in the input frame memory as necessary. 7 buffer switching is prohibited.

The task control unit 7 searches the task table 8 during encoding, and selects each unit processor module 11a to 1. 1.
The optimal processing block and processing task for k are determined, and these are used as commands to be sent to each unit processor module 11a to 1.k via the control lot 12. 1k, and each unit processor module 11a to 1k. 1k
decodes the command and executes the command.

Further, each unit processor module 11a to 11k notifies the task control unit 7 of the completion of the processing each time it completes the instructed processing, and enters a standby state until receiving the next instruction.

Note that the processing tasks include, for example, the shared memories 10a to 1.
Data transfer from On, DCT of 8x8 pixel block
These range from small processing units such as calculations to combinations of these or expanded processing block sizes. In addition, in the case of a combination task, when the unit processor modules lla to 11k need to access the shared memories 10a to 10n during processing,
The unit processor modules lla to llk output a shared memory access request to the task control unit 7, and remain in a standby state until permission for the request is granted.

At this time, since a plurality of independently provided memory buses 13, 14a to 14n are provided between each of the shared memories 10a to 10n and the unit processor modules lla to llk, the probability of a path neck occurring is low. . For example, the three middle-level processor modules #1 to
As shown in the explanatory diagram from #3 showing the access status to the three shared memories, each shared memory can be accessed via three independently provided memory buses a to C, so there are almost no path necks. do not have.

On the other hand, the unit processor 3 is initially in a standby state, and the task control unit 7 determines the task to be instructed to the unit processor 3, and determines the processing block position, processing block size, processing content, etc.
The attributes of the block, etc. are written to the command port 20, and an interrupt is issued to the interrupt control unit 18.

Then, the interrupt control unit 18 outputs an interrupt signal 102 to the unit processor 3, and the unit processor 3 reads the command port 20, decodes the command and follows the instructed task, and if necessary, bidirectional buffer 2 1 ．．
A to 21n+2 are opened to access the shared memories 102 to Ion, or the local RAM 22 and local ROM 23 are accessed to execute processing.

When the processing is completed, the unit processor/source 3 writes the data to be passed to the task control unit 7, and writes the data to be passed to the task control unit 7, and
04 and enters the standby state.

Then, the interrupt control unit 18 decodes the address 104, generates an interrupt signal, and sends it to the control bus 2.

For example, in order to simplify the explanation, in the case of task processing with three unit processors and two types of encoding processing, as shown in FIG. The area is divided into three areas A, B, and C, and task 1 processing is instructed. Based on the result of task 1, it is determined that the amount of calculation required for task 2 processing in area B is large, and area B is further divided. It is subdivided and instructs each unit processor to perform processing. In other words, as shown in FIG. 4, task T2, which would have traditionally been executed by unit processor #2, is distributed to unit processor #1 and unit processor #3, and task T2, which has been executed by unit processor #1 and #3, is Reduce time and increase processing efficiency.

In the above embodiment, the task control unit 7 is independent, but the present invention is not limited to this, and the task control unit H7 may be omitted by providing that function to one of the unit processors.

Furthermore, depending on the scale and specifications of the system, it may be effective to simply divide the area into small blocks without dividing the task, and then allocate new blocks one after another to the unit processors that have completed processing.

Although the first embodiment described above has been described using a single multiprocessor module 16 of the multiprocessor type video encoding device, the present invention is not limited to this, and as shown in FIG. Module 16 16a~
16m may be connected in series for pipeline processing. In FIG. 5, 25a, 25b, . . . are ports connecting each task control section 7, and 26a, 26b, . . . are two-port memories connected to the I/O bus 15 of each unit processor module.

FIG. 7 is a block diagram showing a multiprocessor type moving image encoding device according to a second embodiment of the present invention. As shown in the figure, in addition to the structure of the first embodiment, a memory bus control table 24 is provided so as to be accessible from the task control section 7. In the memory bus control table 24, the usage status of the memory buses 13, 14a to 14n, the task priority of the unit processor module 1, etc. are written.

Note that the other configurations are the same as those of the first embodiment, so a description thereof will be omitted. The task control unit 7 updates the memory bus control table 24 as needed and newly updates the shared memories 10a to 10a.
10n, the memory bus control table 24 is referred to to determine whether the memory bus used to access the shared memory is free, and if it is free, the memory bus is used. It outputs a permission signal to permit the access request, and if it is in a used state, it waits until it becomes an empty state, and when it becomes in a used state, it outputs a use permission signal and permits the access request. In addition, when access requests are generated from two or more unit processor modules 11 to the same memory bus that is in use, the task priority of the unit processor module 11 written in the memory bus control table 24 is changed the next time the memory bus becomes free. Based on this, the access request of the unit processor module l1 having a high priority is granted preferentially.

The multiprocessor type video encoding device of the second embodiment having such a configuration can efficiently control access to the memory bus in addition to the effects of the first embodiment.

FIGS. 8 and 9 are a block diagram and a time table showing a method of controlling a memory bus in a multiprocessor type moving picture encoding device according to a third embodiment of the present invention.

In FIG. 8, input data 100 provided from an external circuit is written into the shared memory 2 for one frame, and when the writing is completed, a write end signal 3 is sent to the task control unit 7.
0 is output.

The bus control unit 37 arbitrates shared memory access requests from the unit processors 3a to 3h and instructs shared memory access permission. Each unit processor 38 to 3h exchanges a shared memory access request signal and a shared memory access permission signal 32a to 32h from the bus control unit 37 to each unit processor 3a to 3h with the task control unit 7, exchanging human output data signals and control signals 33a to 33h with the shared memory 2 via the memory bus 6;
Shared memory access permission signals 35a to 35h are exchanged with the lotus control unit 37.

The shared memory 2 exchanges human output data and control signals 34 with the memory bus 6. Also, transmission data 1
01 is output via the memory bus 6.

Next, the operation will be explained with reference to FIG.

This example is an example of task distributed parallel processing in which variable areas and tasks are allocated to each unit processor 3a to 3h in a parallel configuration at any time.

Input data 100 is transferred to shared memory 2 by an external circuit.
The frame is written, and a write end signal 30 is output to the task control unit 7. When the conditions for the end of encoding the previous frame and the end of writing input data are met, the task control unit 7 divides the next frame into processing blocks and sequentially outputs instructions to the unit processors 3a to 3h in the parallel configuration. Allocate. Each of the unit processors 3a to 3h sequentially processes tasks according to a predetermined program written in the instruction memory, and notifies the task control unit 7 of the completion of the processing when the target processing is completed. By repeating this process, moving image n-coding is executed sequentially. At this time, when each unit processor 3a to 3h performs a shared memory access task, it outputs a shared memory access request to the bus control unit 37 before the processing ends. The bus control unit 37 determines the use state of the memory bus 6, and if it is free, it immediately outputs a use permission signal to the unit processors 3a to 3h, and if it is in use, it waits until it becomes free and then outputs a use permission signal. Performs bus arbitration such as output.

By the way, in the instruction memory of each unit processor 3a to 3h, a data transfer task for accessing the shared memory and a calculation task for calculating and encoding the transferred data are alternately written. In the embodiment No. 3, the shared memory 2 or the unit processors 3a to 3h are already installed.
When a transfer task for data existing in the internal memory of the computer comes next, the next transfer task is arranged so that it comes at a special point a certain time before the end of the immediately preceding calculation task.

FIG. 9 shows the three unit processors 3a,
A parallel configuration of 3b and 3c (indicated by #1 to #3 in the figure) is adopted, and each unit processor #1 to #3 when bus contention occurs.
This is an example of processing, and time is shown on the horizontal axis. Note that the bus access priority order is #1, #2, and #3. In FIG. 9, intermediate processor #1 executes a data transfer task to execute task 2 before task 1 ends (t6t4), then performs the remaining processing of task 1, and task 1 ends. At time t6, from time tl to t
Using the data transferred during period 4, the task 2 is executed. Unit processor #2 issued a transfer request at time t2, but due to bus contention, it continued to execute task 1, and at time t
4, it receives permission to use the bus, transfers data for executing task 2 during the period t4 to t6, and performs the remaining processing of task 1 from time t6 when the transfer ends. Unit processor #3 issues a transfer request at time t3, but due to bus contention, it continues to execute task] and after completing task 1, transfers the data of unit processor #2, which has a higher priority than unit processor #3. It is in a waiting state until time t6 when the transfer ends, and data transfer is executed from t6.

Thus, according to this third embodiment, the first and second
Unlike the embodiment shown in FIG. 1, even if there is a conventional memory bus structure with the same symbol, in which a plurality of unit processors 3 are linked to a shared memory 2 that can be accessed in a time-sharing manner via a single memory bus 6, bus control is not required. In , each unit processor 3 issues a shared memory access request a certain period of time before the end of processing,
In contrast, by adopting a path control method in which the unit processor 3 with the highest priority instructs shared memory access permission, the wait state of the unit processor 3 is almost eliminated, and even if a wait state occurs, it is extremely Since the time is short, processing efficiency is improved.

Although the third embodiment described above shows an example of task-distributed parallel processing, the present invention is not limited to the above-mentioned embodiment. Even in the case of pipeline processing in which two-port memories are connected in series, this is effective in cases where bus contention occurs when a plurality of unit processors 3 access the shared memory 2.

Further, the number of unit processors is effective if it is two or more.

FIG. 10 is a block diagram showing a multiprocessor type moving image encoding device according to a fourth embodiment of the present invention. In the figure, unit processors #] (41) to #3 (4B)
has a storage section 58 in addition to an acquisition section 55, a processing section 56, and an output section 57 that are connected via a local bus 5, and this storage section 58 is used for dividing screen No. 1 to be described later. 1~No. It has storage areas for storing encoded and decoded signals (data) of nine partial screen signals, respectively.

Unit processors #1 to #3 are divided into nine divided screens No. 1 in FIG. 1~NO. In charge of 9. That is, the screen is divided into nine sections, upper and lower, and unit processor #1 (41) is assigned to No. 1 of the divided screen. 1, No. 4 and no. 7,
Unit processor #2 (42) is No. 2 on the divided screen. 2,
No. 5 and N(L 8, unit processor #3(
43) is the number on both sides of the classification. 3.No. 6 and the island,
In charge of 9. 6o is a transfer control unit, and a common bus 61
and controls data transfer between unit processors #1 to #3. Note that the unit processor # in the fourth embodiment is
#3 import unit 55 is No.3. While capturing partial screen signals related to N frames, No. (N-1.)
Partial screen signals related to frames are read out for data processing, so configurations that allow simultaneous reading and writing (e.g.
Tufflehaffa configuration).

Next, the operation of the fourth embodiment will be explained with reference to the dynamic timing diagram shown in FIG. 12.

Each of the 11th place Brocenosa #1 to #3 The partial screen signal assigned by itself is fetched from the input image signal (supposed to be the first frame) on the input bus 51 to the capture unit 55, and processed by each unit processor #1 to #3. The unit 56 reads the data from the capture unit 55 all at once upon completion of capturing the first frame, and starts the above-described process.

Taking the 11th processor #1 as an example, the 11th
Division screen No. in the figure. 1, the encoded signal as the result is stored in the output section 57, the input image auxiliary signal (encoded/decoded partial screen signal) is stored in the storage section 58 via the local bus 59, and then the partial Screen no.
4. Perform processing for partial screen demon 7. The total processing time of unit processor #1 within one frame is 1, N
o. 4 and no. 70) This is the total processing time for the three divided screens. Since these partial screens are discontinuous with each other, their correlation with each other is clear. For example, as shown in FIG. 12, partial screen NO. Even if the processing time for partial screen No. 4 is longer, partial screen No. 1, No. The processing time for 7 is often short, and the total processing time is averaged as a whole, making it possible to finish the processing with plenty of time to spare for the input cycle of one frame. When the processing section 56 of the unit processor #1 finishes the processing, the encoded/decoded partial screen signal of the partial screen signal is stored in the storage section 58, as shown in FIG. The same applies to unit processors #2 and #3, and when unit processors #1 to #3 complete processing for the first frame, transfer control unit 10
3, the encoded/decoded partial screen signals are sequentially read out onto the common bus 61 as shown in FIG. will be sent to. Each unit processor #1 to #3
If the data necessary for processing the next screen frame exists on the common bus 61 among the processing data of other unit processors, the data is taken into the storage section 58. If encoded/decoded partial screen signals of adjacent divided screens are required for processing each divided picture quotient, after the capture is completed, the storage unit 58 stores divided screens N as shown in FIG.
O. 1~NO. This means that encoded and decoded signals related to No. 9 are stored.

Since the transfer of encoded/decoded partial screen signals through this common bus 61 is a simple transfer between memories, it is faster than the input cycle of the input image signal (1/30, 1/15, 1/10 seconds, etc.). As shown in Figure 12,
The processing for the first frame and the transfer using the common bus 61 can be completed while the image signal of the second frame is being input, and the processing for the second frame can be started at the time when the input of the second frame is started. be done.

If the sum of the processing time of the first frame and the transfer time of the encoded/decoded partial image signal, which is the input image auxiliary signal, via the common bus 61 exceeds the input period of the input image signal, as shown in FIG. If the processing time for the input image signal of the second frame is started after the end of the above-mentioned transfer, and the processing time for the input image signal is short, the time point at which the capture of the input image signal of the third frame ends. by the second
The processing and transfer of the input image signal of the first frame can be completed, and the processing of the input image of the first and second frames can be averaged between frames. The above processing delay is the third
frame processing is no longer affected.

In the task execution process of the fourth embodiment, one unit processor is in charge of the image signals of a plurality of divided screens, and the divided screens are separate areas that are not continuous, and the image characteristics are localized in one image frame. Bias (disparity in the amount of data to be processed)
Even if this occurs, the degree to which it appears concentrated on the segmented screen of one unit processor will be low, and even if the processing time for the partial image signal of one segmented screen becomes long, the processing of the segmented image signal of other segmented image processors will be reduced. When the time is short, the processing time within one frame is averaged, so that processing can be performed within the input cycle of one frame of input image signals with high probability.

Furthermore, since the unit processor is executed at the beginning of a new screen, and the sending of the encoded signal to the output bus and the transfer of the input image auxiliary signal to other unit processors are executed at the end of all unit processors. , in a certain frame, even if it cannot be processed within the input period of the input image signal,
By absorbing it with another frame that can be processed within the human cycle of the input image signal, it is possible to process it within the input cycle of the input image signal for one frame from the perspective of processing all frames.

FIG. 17 is a block diagram showing a multiprocessor type moving picture encoding device according to a fifth embodiment of the present invention. In the figure, 51 is an input bus for the input partial screen signal, 53 is an output bus, 41, 42 and 43 are unit processors, and therein there is a processing section 56 and an acquisition section that can store input partial screen signals for two frames. 72, a shared storage section 71 for storing a part of the encoded/decoded partial screen signal, a storage section 58 for the encoded/decoded partial screen signal, outputting the partial n coded signal of the encoding result. Output section 57 and each of these sections 56, 5
7, 58, 71, and 72 local buses 59 for data transfer. Note that 70 is a control unit that controls the plurality of unit processors 41 to 43, respectively. In the fifth embodiment, as in the conventional example 2, the entire screen is divided into three partial screens A, B, and C as shown in FIG. 26, and dedicated unit processors 41, 42, and 43 are assigned to each. It performs processing.

Next, the operation will be explained.

As shown in the timing diagram of FIG. 18, input partial screen signals S1 to S3 are supplied to the input bus 51 in a time-division manner.

Furthermore, the input section 72 for the input partial screen signals 81 to S3 is a double buffer 11512 that can be read and written at the same time, and the input partial screen signal Sl-53 flows without stagnation onto the input bus 51 at a constant period. Therefore, one side of the double buffer is always connected to the write side, and all input frames are necessarily captured. Now, when the input partial screen signals 51 to S3 of m frames are input, the control unit 70 monitors the operation of each unit processor 41 to 43, and when all unit processors 41 to 43 have finished inputting m frames. Then, all unit processors 41 to 43 are notified of the start of processing.

The time required for processing by each unit processor 41-43 differs depending on the input partial screen signals 51-S3. Here, the processing by the unit processor 41 for m frames takes the longest time. When the processing of all unit processors is completed, the control unit 70 controls each unit processor. ! P-rank processors 41 to 43
An instruction is sequentially given to output encoded signals from the output unit 57 of the output bus 53 to the output bus 53. At the same time, the control unit 70 monitors the input state of the m+1 frame, and when input to all unit processors is completed, notifies all unit processors of the start of processing of the m+l frame, and causes them to carry out the same processing as above. . Here, the processing for m+1 frames by the unit processors 41.43 is longer than the input period of the input partial screen signals S1 to S3, but all the unit processors perform m+1 frames.
When the processing of one frame is finished, the input of m + 2 frames to all unit processors has already been completed, and the processing of m12 frames can be started immediately.

Next, the processing inside each of the unit processors 41 to 43 will be described starting from the point in time when processing of m frames is started, taking the unit processor 41 as an example.

However, at this point, partial screen A of frame m-1 has already been displayed.
The encoded/decoded partial screen signal corresponding to
, and the encoded/decoded partial screen signal corresponding to the sub-area 82a (see FIG. 26) indicated by the hatched area of the adjacent partial screen B is stored in the shared storage section 71. do. The control unit 70 extracts the input partial screen signals 81 to S3 from the acquisition unit 72 into blocks, and extracts the encoded/decoded partial screen signals of the previous screen stored in the storage unit 58 and the shared storage unit 71. Motion-compensated interframe encoding is performed using the encoder, the encoded output is output to the output unit 57, and the encoded/decoded partial screen signal obtained at the same time is stored in the storage unit 58. At this time, sub-area 8 in FIG.
The signal of the part corresponding to 1a is necessary for the unit processor 42 to process the next frame, so the unit processor 42
They are simultaneously stored in a shared storage section 71 that can also be accessed from B.

Through the above-described operations, the processing results of other unit processors can be fetched from the shared storage section 71 and used for processing the next frame. Moreover, as in the processing part of the m+1 frame in FIG. 18, the input partial screen signals S1 to S3 are
Even if the processing time is longer than the cycle of , it is possible to average the processing times of the previous and subsequent m and m+27 rems. Therefore, even if the processing time is longer than the average value, the number of unit processors used can be reduced by reducing the input speed of the input partial screen signal, and image processing can be performed at low cost.

In the above embodiment, one common storage section 71 is arranged between adjacent unit processors 41, 42 and 42, 43, but if three or more unit processors 41
43 may be provided with one shared storage section 71.

〔Effect of the invention〕

As described above, according to the multiprocessor type video encoding device according to claim 1, the task control unit stores information necessary for dividing an image into a plurality of blocks and controlling the unit processor. The optimal processing block and processing task for each unit processor module are determined by referring to the task table created by the processor module, and the processing tasks are distributed approximately equally among the multiple unit processor modules for encoding to shorten the waiting time. Therefore, efficient processing operations can be performed and the processing power of the multiprocessor can be utilized to its fullest.

Furthermore, according to the bus control method according to claim 2, since each unit processor always issues a bus use request a certain period of time before completing the previous process, if bus contention occurs when outputting a bus use request, However, the intermediate processor does not go into a wait state and continues executing the previous process, so the processing efficiency of the processor does not decrease. As a result, the reduction in processing efficiency due to bus contention can be minimized, and the processing power of the multiprocessor can be utilized to the fullest.

According to the multiprocessor type moving image encoding device according to claim 3, one unit processor is in charge of image signals of a plurality of divided screens, and since the divided screens are separate areas that are not continuous, one Local biases in image properties in image frames are unlikely to appear concentrated in the image signals handled by one unit processor, and even if the processing time for partial image signals of one segment screen becomes longer, it is unlikely that local biases in image properties will appear concentrated in the image signals handled by one unit processor. If the processing time for the segmented image signal of the screen is short], the processing time of the frame is averaged. In addition, the n-encoding process is performed by all unit processors while waiting for the start of a new screen, and the exit of the encoded signal to the output bus and the transfer of the input image auxiliary signal to other unit processors are performed by all unit processors. Even if the encoding process of a certain frame exceeds the input period, it can be absorbed by other frames that can be processed within the input period, and from the perspective of the entire frame processing, the processing time is reduced. Since averaging can be performed, it is possible to minimize the decline in processing performance due to bias in screen properties, and it is possible to make maximum use of the processing performance of the multiprocessor.

Furthermore, according to the multiprocessor type video encoding device according to claim 4, one screen is divided into a plurality of partial screens, each partial screen is processed by a dedicated unit processor, and in this processing, encoding/decoding is performed. At the same time, the processed partial screen signals are stored in the storage section of the own unit processor, and at the same time, the signals of the portions that need to be referenced from other unit processors are also stored in a shared storage section that can be accessed from other unit processors as well. By storing the encoded/decoded partial screen signals written to the shared storage by other unit processors during encoding processing, the number of partial screen divisions can be reduced to the average processing time. If the processing time is longer than the average value, the input speed of the input partial screen signal is reduced, thereby reducing the number of unit processors used, thereby maximizing the processing power of the multiprocessor. It can be used only for a limited time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a single multiprocessor module of a multiprocessor type video encoding device according to a first embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a unit processor module shown in FIG. 1. Block diagram showing 3rd
4 and 4 are explanatory diagrams of task processing operations of each unit processor of the first embodiment, and FIG. 5 shows the configuration of a plurality of multiprocessor modules of the multiprocessor type video encoding device according to the first embodiment. A block diagram, FIG. 6 is a timing diagram showing memory bus access operations of unit processor modules, and FIG. 7 is a single multiprocessor module configuration of a multiprocessor type video encoding device according to a second embodiment of the present invention. FIG. 8 is a block diagram showing a memory bus control method in a multiprocessor type video encoding device according to a third embodiment of the present invention, and FIG. 9 is a block diagram showing a third embodiment of the present invention. FIG. 10 is a block diagram showing a multiprocessor video encoding device according to a fourth embodiment of the present invention, and FIG. 11 is a unit processor of the fourth embodiment. 12 and 13 are timing diagrams showing the operation of the fourth embodiment, and FIGS. 14 and 15 show the internal state of the storage section in the fourth embodiment. An explanatory diagram, FIG. 16 is an explanatory diagram showing the transfer order of input image auxiliary signals in the fourth embodiment, and FIG. 17 is a block diagram showing a multiprocessor type moving image encoding device according to the fifth embodiment of the present invention. 18 is a timing diagram showing the signals of each part of the block shown in FIG. 17, FIG. 19 is a block diagram showing the structure of a conventional multiprocessor type video encoding device, and FIGS. 20 and 21 are An explanatory diagram of the operation of each unit processor of a conventional multiprocessor type video encoding device, FIG. 22 is a block diagram showing the conventional multiprocessor type video encoding device, and FIG. 24 and 25 are timing diagrams showing the operation of the conventional example shown in FIG. 22, and FIG. FIG. 27 is an explanatory diagram showing an example of dividing a partial screen in the embodiment, FIG. 27 is a timing chart diagram showing signals of each part of the block shown in FIG. 22, and FIG. 28 is an explanatory diagram showing operations in the motion compensation interframe coding method. be. In the figure, 2 is a shared memory, 3, 3a to 3h are unit processors, 48 to 4h are local memories, 6 is a memory bus, 7, 7a to 7m are task control units, 8.8a to 8m are task tables, and 9 is a Input frame memory, 102-1
0n is a shared memory, 11a to llk are unit processor modules, 12 is a control bus, 13.14a to 14n are memory nodes, 1.6, 1.6a to 16m are multiprocessor modules, and 18 is an interrupt control unit. , 22 is a local RAM, 23 is a local ROM, 24 is a memory bus control table, 37 is a bus control unit, 41 to 43 are unit processors, 51 is an input bus, 55 is a capture unit, 56 is a processing unit, 57 is a 5 is a local bus, 60 is a transfer control unit, 61 is a common bus, 70 is a control unit, and 71 is a shared storage unit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (4)

[Claims] (1) A unit processor for digital signal processing that executes encoding according to an encoding program, a local memory connected to the unit processor via a local bus, and an interrupt signal sent from the control bus to arbitrate the unit The interrupt controller includes an interrupt control section that delivers the address and data of the unit processor to the processor, receives the address and data of the unit processor via the local bus, decodes it, generates an interrupt signal, and sends it to the control bus, each of which is arranged in parallel. a plurality of unit processor modules, each connected to each of the plurality of unit processor modules via a plurality of independently provided memory buses, and a plurality of shared memories for storing locally decoded data or data in the middle of encoding and parameters; an input frame memory having a plurality of buffers, one side of which is open to a circuit for writing input data, and the other side of which is open to the unit processor module so that writing and reading can be performed asynchronously; A task table that stores past history, current situation, future prediction, etc., and an image are divided into a plurality of blocks, and the optimal processing block and processing task for each unit processor module are determined by referring to the task table. and instructing the processing block position and the processing task contents to the unit processor module via the control bus, thereby causing the plurality of unit processor modules to share the processing task almost equally. A multiprocessor-type video encoding device comprising a task control unit that performs processing. (2) A memory bus control method when two or more unit processors for digital signal processing are connected to a shared memory that can be accessed via a single memory bus in a time-sharing manner, comprising: The processor issues an access request to the shared memory a certain period of time before the end of the processing,
In contrast, the bus control method is characterized in that the access requests are acknowledged in order from the unit processor having the highest priority. (3) Digital signal processing that allocates a specific screen position area on one screen, captures a partial image signal corresponding to the specific screen position area of the input image signal, performs signal processing, and then sends it to the output bus. has multiple unit processors for
In a multiprocessor-type video encoding device, each of the unit processors is capable of taking in processed signals of other unit processors as input image auxiliary signals for neighboring processing, and each of the unit processors is configured to take in a plurality of non-contiguous screens. A multiprocessor characterized in that after all unit processors share the position area and take in the input partial image signals of the screen position area shared by all unit processors, they start signal processing of the input partial image signal and the input image auxiliary signal all at once. type video encoding device. (4) A capture unit that captures the input partial screen signal input to the input bus frame by frame, a processing unit that performs encoding/decoding processing on the input partial screen signal, and partial encoding in the processing unit A multiprocessor comprising a plurality of unit processors, each comprising an output unit that outputs an encoded/decoded partial screen signal that is a processing result of the process, and a storage unit that stores the encoded/decoded partial screen signal. type video encoding device, comprising: a control unit that controls the capture, processing, storage, and output in each unit processor; and a control unit that controls the capture, processing, storage, and output in each unit processor; A part of this encoded/decoded partial screen signal necessary for processing is transmitted to at least one of the own unit processor and the other unit processor.
1. A multiprocessor type video encoding device, comprising: a shared storage section for storing data in a readable and writable manner.