JPH03205699A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To accurately decide a semiconductor memory as a good or defective memory in a short test time by providing a switch circuit for test and a signal input means for test for input of a test signal which sets a row address decoder and a column address decoder to the selective set operation release state. CONSTITUTION:When a potential in the high level is given to a signal input terminal 18 for test at the time of test, an X decoder 15 and a Y decoder 16 are set to the operation stop state. If a defect exists in a gate oxide film or the like and a leak current flows to the ground from the defect part, a current I flows to transistors TRs Qio to Qik for memory cells from the signal input terminal 18 for test through NMOS TRs Q0 to Q(k+1) of a switch circuit 17 for test though the leak current is minute. This current I is confirmed to decide a mask ROM (read only memory) as a good or defective memory. Thus, it is accurately decide as a good or defective memory in a short test time.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to read-only memories (Read Only Memories).
The present invention relates to semiconductor memory devices such as ROM (hereinafter abbreviated as ROM).

Conventional Technology A common test method for determining whether a semiconductor memory device is good or defective is to determine whether a desired data output can be obtained in response to an address signal input to the semiconductor memory device. .

A specific example will be described below in which the semiconductor memory device to be tested is a mask ROM shown in FIG. 2 in which data is written in the manufacturing stage.

In the 212th transistor, transistors QNI and QN2 (here,
For convenience of explanation, only 2 bits are shown) are composed of N-channel MOS transistors (hereinafter referred to as NMoS transistors), and the gates of these memory cell transistors are connected to the corresponding word! i W Li connected to i.

A bit line BL is connected to the drain, which is an output terminal, of each of the memory transistors QNI and QN2, and the bit line BL is connected to the sense amplifier 1 via an NMOS transistor QN4. This Sense Ambu 1 is
Memory cell transistor QN1. This is an amplifier that amplifies output data read out from QN2, and the amplified output data is output via output buffer 2.

Furthermore, each memory cell transistor QN1. The sources of QN2 are connected to virtual ground lines VGLl and VGL2, respectively.
is connected, and one virtual ground line VGLI is NMOS
Connected to one charging circuit 3 via transistor QN3 and connected to the other ground! VGL2 is connected to another charging circuit 4 via an NMOS transistor QN5. These charging circuits 3.4 are circuits for charging the potentials of the corresponding virtual ground lines VGLI and VGL2 to the same high level potential as the bit line BL.

Each NMOS transistor QN3, QN inserted in the middle of the bit line BL and virtual ground line VGLIVGL2
A column line CSELj is connected to the gate of 4 and QN5. Moreover, between the output terminal of each charging circuit 3.4 and the ground, there is a corresponding virtual ground! IVGL
NMOS} transistors QN6 and QN7 are connected to switch and set the potentials of I and VGL2 to the ground potential (OV).

In the mask ROM having the above configuration, the reading operation of data written in the memory cell transistor QNI is performed as follows.

A high-level potential is applied to the word line WLi as a row address signal, a high-level column selection signal is applied to the column line CSELj as a column address signal, and a high-level potential is applied to the gate of the NMOS transistor QN6 and the charging circuit 3 as a virtual ground selection signal VGSELI. When a low-level potential is applied to the gate of the NMOS transistor QN7 and the charging circuit 4 as the virtual ground selection signal VGSEL2, the bit line BL and the virtual ground line VG
Each NMOS inserted in the middle of LI VGL2}
- The transistors QN3, QN4, and QN5 are turned on, the NMOS transistor QN6 on the side of the charging circuit 3 is turned on, and the NMOS transistor QN7 on the side of the charging circuit 4 is turned off.

As a result, the potential of the virtual ground fiVGL1 becomes low level, and the charging circuit 4 is connected to the virtual ground line VGL2.
A charging level (high level) potential set by is applied, and memory cell transistor QNI is selected. That is, the drain of the memory cell transistor QNI is at a high level, and the source thereof is at a low level (in contrast, the drain and source of the memory cell transistor QN2 are both at a high level).

When logic r1j data is written in the memory cell transistor QNI (a low threshold is set and a voltage is applied to the gate to turn it on like a normal enhancement transistor), the memory cell transistor QNI The charge on the bit line BL (bit iiB
The charge accumulated in the stray capacitance C of L is discharged, and as a result, the potential of the bit line BL is lowered, and the sense amplifier 1 reads out logic "1" data.

On the other hand, when logical "O" data is written in the memory cell transistor QNI (a high threshold value is set and it does not turn on even if a voltage is applied to the gate),
Since the memory cell transistor QNI is off, a discharge path is not formed and the potential of the bit line BL does not decrease. As a result, the sense amplifier 1 reads logic "0" data.

In the conventional test method, the test is performed by evaluating whether the data read from the input address as described above matches the predetermined data that has been written.

Problems to be Solved by the Invention However, the above-described testing method has the problem of overlooking the following defects.

In other words, leakage current from the bit line BL to the ground may occur due to manufacturing reasons in the mask ROM, such as a defect at the source or drain junction of the memory cell transistor QNI connected to the bit line BL. In this case, even if the write data of the memory cell transistor QNI is logic "O", the potential of the bit liBL when this memory cell transistor QNI is selected decreases, and in the worst case, it becomes logic "1". When the temperature drops to a corresponding level, the product becomes defective. However, even in this case,
When the leakage current is relatively small, the bit line BL potential decreases slowly, so there is a possibility that this product may be erroneously determined as a non-defective product during a normal test time.

For this reason, in order to reliably detect defective products as described above, it is necessary to take a longer test time per address than the normal test time, and as memory capacity increases, Testing times will be longer, resulting in significantly higher testing costs.

Therefore, it is an object of the present invention to provide a semiconductor memory device that allows a test to accurately determine whether a product is good or defective in a short period of time. Means for Solving the Problems The present invention provides a memory cell array in which a plurality of memory cell transistors are arranged in a matrix, and selectively sets any one row of memory cell transistors to a state corresponding to an on operation. In a semiconductor memory device including a row address decoder and a column address decoder that sets an output line corresponding to an arbitrary column of memory cell transistors to a selected state in which output is possible, at least on the output terminal side of each memory cell transistor, Turn on the connected test switch circuit and test switch circuit, set the potential of at least the output terminal side of each memory cell transistor to high level, and select and set the row address decoder and column address decoder. A semiconductor memory device characterized in that it is provided with a test signal input means for inputting a test signal for setting the semiconductor memory device to a release state.

According to the present invention, if there is a defect that causes a leakage current in the output terminal of a memory cell transistor, the test signal is turned on by the test signal input from the test signal input means during the test. Current flows into the memory cell transistor through the switch circuit.

By detecting this current, defects in the semiconductor memory device can be confirmed within a short test time.

Embodiment FIG. 1 is a circuit diagram schematically showing a semiconductor memory device according to an embodiment of the present invention. The semiconductor memory device shown in FIG. 1 is a mask ROM, and the configurations of the sense amplifier 11, output buffer 12, charging circuits 13, 14, etc. are the same as those of the conventional semiconductor memory device described above.

That is, in FIG. 1, the transistors QOO to Q i k constituting the memory cells arranged in a matrix are composed of NMOS transistors, and the gates of the memory cell transistors in each row are connected to the X decoder 15, which is a row address decoder. They are connected to corresponding word lines WLO to WLi, respectively.

A bit line BL is connected to the drain, which is an output terminal, of each of the memory transistors QO○ to Qik, and
The bit line BL is NMOS} transistor QNI~QN
It is connected to the sense amplifier 11 via k. This sense amplifier 11 is a memory cell transistor QOO~Q
This is an amplifier that amplifies the output data read from the ik, and the amplified output data is outputted via the output buffer 12. In addition, virtual ground lines VGLO and VGL2 are connected to the sources of each memory cell transistor QOO to Qik, respectively.
~VGL(k+1) is connected, and one virtual ground line VGLO~ is connected to NMOS} run transistor QVO~QV(k-
1> to one charging circuit 13, and the other virtual ground line VGL2 to VGL (k+1) is NM
It is connected to another charging circuit 14 via os transistors QV2 to QV(k+1). These charging circuits 13
, 14 are the corresponding virtual ground lines VGLO~
This is a circuit for charging the potential of VGL (k+1>) to the same high level potential as the bit line BL.

The above bit line BL, virtual ground lines VGLO to VGL (
Each NMOS transistor Q inserted in the middle of
VO, QNI~QV (The gate of k+1> is a column address decoder)? Corresponding column lines CSELO to CSELj of the decoder 16 are connected to each other. Further, between the output terminals of each of the charging circuits 13 and 14 and the ground, corresponding virtual ground lines VGLO to VGL are connected.
NMOS transistors QMI and QM2 are connected to switch and set the potential of (k+1) to the ground potential (OV).In the mask ROM of this embodiment, each memory cell transistor QOO~ A test switch circuit 17 consisting of a plurality of NMOS}-run transistors QO to Q(k+1> whose sources are respectively connected to the source and drain of Qik is provided.
The gate and drain of the transistor QO10 (k+1) are connected to the test signal input terminal 18.

Further, the test signal input terminal 18 is also connected to the X decoder 15 and the Y decoder 16.

This test signal input terminal 18 is a terminal used to input a test signal TEST when testing the mask ROM, and upon receiving the test signal TEST, the operations of the X decoder 15 and Y decoder 16 are stopped. and each NMOS of the test switch circuit 17}
Transistors QO to Q(k+1) are turned on.

Next, the operation of the mask ROM during testing will be explained.

When a high-level potential is applied to the test signal input terminal 18 as the test signal TEST during a test, the X decoder 15 and Y decoder 16 stop operating, and the bit lines BL and virtual ground lines VGLO to VGL
(k+1) NMOS transistor QVo. QN
1 to QK(k+1) are turned off, and each NMOS} transistor QO to Q(k+1) of the test switch circuit 17 is turned off.
+1) is turned on. As a result, the potentials on the source side and drain side of the memory cell transistors QOO~Qik, that is, the bit line BL and the virtual ground line VGLO~V
The potential of GL(k+1) becomes high level. At this time, if there is a defect in the junction of the bit line BL or the gate oxide film of the memory cell transistors QOO to Qik, and a leak t current flows from the defect to the ground, even if the leak t current is small, A $ current (2) flows from the test signal input terminal 18 to the memory cell transistors QO to Qikfll through the NMOS} transistors QO to Q(k+1) of the test switch circuit 17. Therefore, by checking the presence or absence of this current, the mask ROM
A judgment is made as to whether the products are good or defective.

Note that the data read operation in the mask ROM during actual use is performed in the same manner as in the prior art example (at this time, the potential of the test signal input terminal 18 is set to a low level). ．． That is, for example, the word line WLO is used as a row address signal.
The signal that sets the potential of column line CSELO to high level is the column address signal, and the signal that sets the potential of column line CSELO to high level is the virtual ground selection signal VGSELI.
MOS} transistor QMI gate and charging circuit 13
A high level potential is also applied to the virtual ground selection signal VG.
When a low level potential is applied to the gate of NMOS} transistor QM2 as SEL2 and the charging circuit 14,
Each NMOS transistor QVO, which is inserted in the middle of the bit line BL and the virtual ground lines VGLO and VGL2,
When QNI and QV2 are turned off, the charging circuit 13
Side NMOS transistor QMI is on, charging circuit 14
NMOS} transistor QM2 on the side is turned off.

As a result, the potential of the virtual ground line VGLO becomes low level, and the charging circuit 14 is connected to the virtual ground line VGL2.
A charge level (high level) potential set by is applied, and memory cell transistor QOO is selected. That is, the drain of the memory cell transistor QOO is at high level, and the source is at low level.

When logic "1" data is written in the memory cell transistor QOO (when a low threshold value is set), the charge on the bit line BL is discharged through the memory cell transistor QOO, As a result, bit line B
The potential of L decreases and the sense amplifier 11 changes the logic to
” data is read out.

On the other hand, when logic "O" data is written to the memory cell transistor QOO (when a high threshold is set), the discharge path is not formed because the memory cell transistor QOO is off. First, the potential of the bit line BL does not drop. As a result, the sense amplifier 11 reads the data of logic rQJ.

Effects of the Invention As described above, according to the semiconductor memory device of the present invention, a high-level potential is applied to the output terminal side of the memory cell transistor through the test switch circuit by the test signal input means during testing, and at this time, Since the semiconductor memory device is determined to be defective when there is a current flowing into the memory cell transistor side, it is possible to accurately determine whether the semiconductor memory device is good or defective in a short test time.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the general structure of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing the general structure of a conventional semiconductor memory device. 11...Sense amplifier, 12...Output buffer, 1
3 14...Charging circuit, 15...X decoder, 16
... Y decoder, 17... Test switch circuit,
18 Test signal input terminal

Claims (1)

[Scope of Claims] A memory cell array in which a plurality of memory cell transistors are arranged in a matrix; a row address decoder that selectively sets any one row of memory cell transistors to a state corresponding to an on operation; In a semiconductor memory device including a column address decoder that sets an output line corresponding to an arbitrary column of memory cell transistors to a selected state in which output is possible, a test device connected to at least the output terminal side of each memory cell transistor. Turn on the switch circuit and the test switch circuit, set the potential of at least the output terminal side of each memory cell transistor to a high level, and set the row address decoder and column address decoder to a state where selection setting operation is canceled. 1. A semiconductor memory device comprising test signal input means for inputting a test signal.